Unified Coverage Report :: Cond split page

Go back

 LINE       16856
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T94,T95,T96
1	0	Covered	T280,T281,T322
1	1	Covered	T2,T5,T8

 LINE       16856
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T127,T128,T280
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T171,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T129,T280,T120
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T404,T169,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T64,T65,T280
1	1	Covered	T170,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T29,T66,T280
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T169,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T30,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T14,T30,T11
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T14,T280,T120
1	1	Covered	T404,T574,T576

 LINE       16856
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T14,T280,T120
1	1	Covered	T404,T574,T576

 LINE       16856
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T14,T11,T12
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T14,T11,T12
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[74] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T14,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[75] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[76] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[77] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T60,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[78] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T60,T280,T120
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[79] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T170,T404,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[80] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T60,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[81] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T60,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[82] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T60,T280,T120
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T60,T280,T120
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[84] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T60,T280,T120
1	1	Covered	T404,T169,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T404,T171,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T60,T280,T120
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[87] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[88] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T404,T169,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T170,T404,T171

 LINE       16856
 SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T62,T280,T120
1	1	Covered	T404,T574,T576

 LINE       16856
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T62,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T280,T120,T323
1	1	Covered	T404,T574,T575

 LINE       16856
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T62,T280,T120
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T62,T280,T120
1	1	Covered	T170,T404,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T62,T280,T120
1	1	Covered	T404,T169,T574

 LINE       16856
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T62,T280,T120
1	1	Covered	T404,T574,T575