Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T127 T128 T323 | T127 T128 T323 | T127 T128 T323 | T127 T128 T323 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T127 T128 T323 | T129 T323 T130 | T129 T323 T130 | T129 T323 T130 | T129 T323 T130 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T129 T323 T130 | T64 T65 T323 | T64 T65 T323 | T64 T65 T323 | T64 T65 T323 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T64 T65 T323 | T29 T66 T323 | T29 T66 T323 | T29 T66 T323 | T29 T66 T323 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T29 T66 T323 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T11 T120 T223 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T14 T120 T49 | T120 T183 T184 | T120 T183 T184 | T60 T329 T122 | T60 T329 T122 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T60 T329 T122 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T62 T329 T137 | T62 T329 T137 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T61 T62 T329 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T63 T329 T123 | T63 T329 T123 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T63 T329 T123 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T32 T120 T183 | T120 T134 T183 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T44 T332 T345 | T334 T186 T329 | T329 T291 T297 | T43 T81 T185 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T2 T6 T13 | T67 T323 T232 | T138 T329 T139 | T266 T288 T329 | T265 T266 T345 | T172 T120 T335 | T120 T183 T184 | T5 T307 T144 | T5 T307 T144 | T307 T144 T329 | T307 T144 T329 | T5 T307 T144 | T329 T330 T331 | T324 T325 T329 | T329 T330 T331 | T329 T330 T331 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T326 T120 T143 | T120 T183 T184 | T329 T330 T331 | T336 T329 T337 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T336 T329 T337 | T329 T330 T331 | T336 T329 T337 | T329 T330 T331
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T280 T281 T322 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T14 T30 T11 | T14 T280 T120 | T14 T280 T120 | T14 T11 T12 | T14 T11 T12 | T14 T280 T120 | T280 T120 T323 | T280 T120 T323 | T60 T280 T120 | T60 T280 T120 | T280 T120 T323 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T280 T120 T323 | T60 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T62 T280 T120 | T62 T280 T120 | T280 T120 T323 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T280 T120 T323 | T61 T62 T280 | T61 T280 T120 | T280 T120 T323 | T61 T280 T120 | T61 T280 T120 | T61 T280 T120 | T63 T280 T120 | T63 T280 T120 | T280 T120 T323 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T280 T120 T323 | T63 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T32 T280 T120 | T32 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T43 T44 T81 | T43 T44 T81 | T43 T44 T81 | T43 T44 T81 | T11 T12 T280 | T11 T12 T280 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T2 T8 T6 | T67 T280 T120 | T138 T280 T120 | T43 T44 T81 | T265 T43 T44 | T172 T280 T120 | T280 T120 T323 | T5 T307 T144 | T5 T307 T144 | T5 T307 T144 | T5 T307 T144 | T5 T307 T144 | T280 T120 T323 | T324 T325 T280 | T324 T325 T280 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T326 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T2 T5 T6 | T32 T14 T29 | T29 T30 T127 | T32 T14 T30 | T2 T5 T6 | T29 T127 T64 | T29 T30 T66 | T14 T30 T11 | T32 T61 T44 | T2 T6 T265 | T5 T307 T144 | T127 T129 T128 | T29 T64 T129 | T29 T30 T66 | T30 T280 T120 | T14 T30 T11 | T60 T62 T280 | T61 T62 T63 | T32 T44 T63 | T43 T44 T81 | T2 T6 T265 | T5 T307 T144 | T280 T120 T323 | T127 T128 T280 | T127 T129 T128 | T64 T129 T65 | T29 T64 T65 | T29 T30 T66 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T11 T280 | T14 T11 T12 | T60 T280 T120 | T62 T280 T120 | T61 T62 T280 | T61 T63 T280 | T63 T280 T120 | T32 T44 T332 | T43 T11 T44 | T280 T120 T323 | T280 T120 T323 | T2 T6 T265 | T5 T307 T144 | T326 T280 T120 | T280 T120 T323 | T127 T128 T280 | T127 T128 T280 | T127 T129 T128 | T129 T280 T120 | T64 T129 T65 | T64 T65 T280 | T64 T65 T280 | T29 T66 T280 | T29 T66 T280 | T29 T30 T66 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T14 T30 T11 | T14 T11 T12 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T280 T120 T323 | T62 T280 T120 | T62 T280 T120 | T61 T62 T280 | T61 T63 T280 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T32 T280 T120 | T44 T332 T345 | T43 T44 T81 | T11 T12 T280 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T2 T6 T13 | T265 T43 T44 | T5 T307 T144 | T5 T307 T144 | T280 T120 T323 | T326 T280 T120 | T280 T120 T323 | T280 T120 T323 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T64 T129 T65 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T30 T66 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T14 T30 T11 | T14 T280 T120 | T14 T11 T12 | T14 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T280 T120 T323 | T280 T120 T323 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T61 T62 T280 | T61 T280 T120 | T61 T280 T120 | T61 T63 T280 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T280 T120 T323 | T280 T120 T323 | T32 T280 T120 | T280 T120 T323 | T43 T44 T81 | T43 T44 T81 | T43 T11 T44 | T11 T12 T280 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T2 T8 T6 | T138 T67 T280 | T265 T43 T44 | T172 T280 T120 | T5 T307 T144 | T5 T307 T144 | T5 T307 T144 | T324 T325 T280 | T280 T120 T323 | T280 T120 T323 | T326 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T2 T5 T6 | T32 T14 T29 | T2 T5 T6 | T29 T30 T127 | T32 T14 T30 | T2 T5 T6 | T29 T127 T64 | T29 T30 T66 | T14 T30 T11 | T32 T61 T44 | T2 T6 T265 | T5 T307 T144 | T127 T129 T128 | T29 T64 T129 | T29 T30 T66 | T30 T329 T41 | T14 T30 T11 | T60 T62 T329 | T61 T62 T63 | T32 T44 T63 | T43 T81 T185 | T2 T6 T265 | T5 T307 T144 | T336 T329 T337 | T127 T128 T323 | T127 T129 T128 | T64 T129 T65 | T29 T64 T65 | T29 T30 T66 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T11 T120 | T14 T60 T120 | T60 T329 T122 | T62 T329 T137 | T61 T62 T329 | T63 T329 T123 | T63 T329 T123 | T32 T44 T332 | T43 T81 T185 | T323 T327 T328 | T323 T327 T328 | T2 T6 T265 | T5 T307 T144 | T326 T120 T336 | T336 T329 T337 | T336 T329 T337 | T127 T128 T323 | T127 T128 T323 | T127 T129 T128 | T129 T323 T130 | T64 T129 T65 | T64 T65 T323 | T64 T65 T323 | T29 T66 T323 | T323 T327 T328 | T29 T30 T66 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T11 T120 | T14 T120 T49 | T60 T120 T329 | T329 T330 T331 | T60 T329 T122 | T329 T330 T331 | T62 T329 T137 | T329 T330 T331 | T61 T62 T329 | T63 T329 T123 | T63 T329 T123 | T329 T330 T331 | T63 T329 T123 | T32 T120 T329 | T44 T332 T345 | T43 T81 T185 | T120 T323 T183 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T2 T6 T13 | T265 T266 T288 | T5 T307 T144 | T5 T307 T144 | T120 T329 T183 | T326 T120 T336 | T329 T330 T331 | T336 T329 T337 | T336 T329 T337 | T127 T128 T323 | T127 T128 T323 | T127 T128 T323 | T323 T327 T328 | T127 T128 T323 | T129 T323 T130 | T129 T323 T130 | T323 T327 T328 | T323 T327 T328 | T64 T129 T65 | T64 T65 T323 | T64 T65 T323 | T323 T327 T328 | T64 T65 T323 | T29 T66 T323 | T29 T66 T323 | T323 T327 T328 | T323 T327 T328 | T29 T30 T66 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T11 T120 | T120 T183 T184 | T120 T183 T184 | T14 T120 T49 | T60 T120 T329 | T60 T329 T122 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T60 T329 T122 | T329 T330 T331 | T329 T330 T331 | T62 T329 T137 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T61 T62 T329 | T329 T330 T331 | T329 T330 T331 | T63 T329 T123 | T63 T329 T123 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T63 T329 T123 | T329 T330 T331 | T329 T330 T331 | T32 T120 T134 | T120 T183 T184 | T44 T332 T345 | T334 T186 T329 | T43 T81 T185 | T120 T183 T184 | T120 T323 T183 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T2 T6 T13 | T138 T67 T323 | T265 T266 T288 | T172 T120 T335 | T5 T307 T144 | T307 T144 T329 | T5 T307 T144 | T324 T325 T329 | T120 T329 T183 | T120 T183 T184 | T326 T120 T143 | T336 T329 T337 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T336 T329 T337 | T336 T329 T337
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T2 T5 T6 | T32 T14 T29 | T2 T5 T6 | T29 T30 T127 | T32 T14 T30 | T2 T5 T6 | T29 T127 T64 | T29 T30 T66 | T14 T30 T11 | T32 T61 T44 | T2 T6 T265 | T5 T307 T144 | T127 T129 T128 | T29 T64 T129 | T29 T30 T66 | T30 T329 T41 | T14 T30 T11 | T60 T62 T329 | T61 T62 T63 | T32 T44 T63 | T43 T81 T185 | T2 T6 T265 | T5 T307 T144 | T336 T329 T337 | T127 T128 T323 | T127 T129 T128 | T64 T129 T65 | T29 T64 T65 | T29 T30 T66 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T11 T120 | T14 T60 T120 | T60 T329 T122 | T62 T329 T137 | T61 T62 T329 | T63 T329 T123 | T63 T329 T123 | T32 T44 T332 | T43 T81 T185 | T323 T327 T328 | T323 T327 T328 | T2 T6 T265 | T5 T307 T144 | T326 T120 T336 | T336 T329 T337 | T329 T330 T331 | T127 T128 T323 | T323 T327 T328 | T127 T129 T128 | T129 T323 T130 | T64 T129 T65 | T64 T65 T323 | T64 T65 T323 | T29 T66 T323 | T323 T327 T328 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T11 T120 T223 | T14 T120 T49 | T60 T329 T122 | T329 T330 T331 | T60 T329 T122 | T329 T330 T331 | T62 T329 T137 | T329 T330 T331 | T61 T62 T329 | T63 T329 T123 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T32 T120 T329 | T44 T332 T345 | T43 T81 T185 | T120 T323 T183 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T2 T6 T13 | T265 T266 T345 | T5 T307 T144 | T324 T325 T329 | T120 T183 T184 | T120 T336 T329 | T329 T330 T331 | T336 T329 T337 | T329 T330 T331 | T127 T128 T323 | T127 T128 T323 | T323 T327 T328 | T323 T327 T328 | T127 T128 T323 | T129 T323 T130 | T129 T323 T130 | T323 T327 T328 | T323 T327 T328 | T64 T65 T323 | T64 T65 T323 | T323 T327 T328 | T323 T327 T328 | T64 T65 T323 | T29 T66 T323 | T29 T66 T323 | T323 T327 T328 | T323 T327 T328 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T11 T120 T223 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T60 T329 T122 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T62 T329 T137 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T61 T62 T329 | T329 T330 T331 | T329 T330 T331 | T63 T329 T123 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T120 T134 T183 | T120 T183 T184 | T44 T332 T345 | T329 T291 T297 | T120 T183 T184 | T120 T183 T184 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T2 T6 T13 | T138 T329 T139 | T265 T266 T345 | T120 T183 T184 | T5 T307 T144 | T307 T144 T329 | T329 T330 T331 | T329 T330 T331 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T336 T329 T337 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T2 T5 T6 | T32 T14 T29 | T2 T5 T6 | T29 T30 T127 | T32 T14 T30 | T2 T5 T6 | T29 T127 T64 | T29 T30 T66 | T14 T30 T11 | T32 T61 T44 | T2 T6 T265 | T5 T307 T144 | T127 T129 T128 | T29 T64 T129 | T29 T30 T66 | T30 T280 T120 | T14 T30 T11 | T60 T62 T280 | T61 T62 T63 | T32 T44 T63 | T43 T44 T81 | T2 T6 T265 | T5 T307 T144 | T280 T120 T323 | T127 T128 T280 | T127 T129 T128 | T64 T129 T65 | T29 T64 T65 | T29 T30 T66 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T11 T280 | T14 T11 T12 | T60 T280 T120 | T62 T280 T120 | T61 T62 T280 | T61 T63 T280 | T63 T280 T120 | T32 T44 T332 | T43 T11 T44 | T280 T120 T323 | T280 T120 T323 | T2 T6 T265 | T5 T307 T144 | T326 T280 T120 | T280 T120 T323 | T280 T120 T323 | T127 T128 T280 | T127 T128 T280 | T127 T129 T128 | T129 T280 T120 | T64 T129 T65 | T64 T65 T280 | T64 T65 T280 | T29 T66 T280 | T29 T66 T280 | T29 T30 T66 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T14 T30 T11 | T14 T11 T12 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T280 T120 T323 | T62 T280 T120 | T62 T280 T120 | T61 T62 T280 | T61 T63 T280 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T32 T280 T120 | T44 T332 T345 | T43 T44 T81 | T11 T12 T280 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T2 T6 T13 | T265 T43 T44 | T5 T307 T144 | T5 T307 T144 | T280 T120 T323 | T326 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T64 T129 T65 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T30 T66 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T14 T30 T11 | T14 T280 T120 | T14 T11 T12 | T14 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T280 T120 T323 | T280 T120 T323 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T61 T62 T280 | T61 T280 T120 | T61 T280 T120 | T61 T63 T280 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T280 T120 T323 | T280 T120 T323 | T32 T280 T120 | T280 T120 T323 | T43 T44 T81 | T43 T44 T81 | T43 T11 T44 | T11 T12 T280 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T2 T8 T6 | T138 T67 T280 | T265 T43 T44 | T172 T280 T120 | T5 T307 T144 | T5 T307 T144 | T5 T307 T144 | T324 T325 T280 | T280 T120 T323 | T280 T120 T323 | T326 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T2 T5 T6
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T2 T5 T6
101 1/1 assign max_value_o = max_tree[0];
Tests: T2 T5 T6
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);