Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143079	1			T94	3		T95	3		T96	10
values[2]	8808	1			T524	2		T535	1		T419	1
values[3]	3294	1			T520	111		T522	12		T582	1
values[4]	1837	1			T520	39		T522	3		T621	28
values[5]	1237	1			T520	25		T522	9		T621	21
values[6]	980	1			T520	2		T522	9		T621	27
values[7]	719	1			T522	8		T621	18		T488	16
values[8]	602	1			T522	7		T621	22		T488	18
values[9]	506	1			T522	4		T621	14		T488	9
values[10]	502	1			T522	5		T621	18		T488	13
values[11]	392	1			T522	3		T621	17		T488	4
values[12]	423	1			T522	5		T621	33		T488	5
values[13]	370	1			T522	6		T621	25		T488	3
values[14]	364	1			T522	15		T621	17		T488	2
values[15]	319	1			T522	4		T621	24		T488	2
values[16]	393	1			T522	23		T621	8		T488	2
values[17]	356	1			T522	4		T621	8		T488	4
values[18]	316	1			T522	3		T621	3		T488	7
values[19]	310	1			T522	4		T621	6		T488	1
values[20]	299	1			T522	3		T621	7		T488	2
values[21]	375	1			T522	3		T621	7		T488	1
values[22]	316	1			T522	8		T621	4		T488	3
values[23]	315	1			T522	6		T621	9		T488	3
values[24]	321	1			T522	6		T621	7		T488	1
values[25]	333	1			T522	10		T621	6		T488	2
values[26]	347	1			T522	9		T621	8		T488	1
values[27]	326	1			T522	10		T621	9		T488	2
values[28]	277	1			T522	8		T621	3		T488	2
values[29]	317	1			T522	22		T621	3		T488	3
values[30]	327	1			T522	7		T621	3		T488	7
values[31]	346	1			T522	5		T621	7		T488	5
values[32]	360	1			T522	4		T621	15		T488	1
values[33]	362	1			T522	9		T621	30		T488	1
values[34]	359	1			T522	4		T621	4		T488	3
values[35]	357	1			T522	5		T621	7		T488	3
values[36]	320	1			T522	4		T621	5		T488	1
values[37]	309	1			T522	5		T621	5		T488	1
values[38]	359	1			T522	5		T621	11		T488	4
values[39]	307	1			T522	6		T621	6		T488	7
values[40]	270	1			T522	5		T621	9		T488	1
values[41]	287	1			T522	11		T621	2		T488	3
values[42]	288	1			T522	8		T488	3		T452	3
values[43]	272	1			T522	6		T488	8		T452	2
values[44]	286	1			T522	17		T488	2		T452	4
values[45]	243	1			T522	5		T488	1		T452	3
values[46]	361	1			T522	3		T488	2		T452	2
values[47]	295	1			T522	5		T488	2		T452	1
values[48]	273	1			T522	9		T488	2		T452	2
values[49]	276	1			T522	4		T488	1		T452	3
values[50]	316	1			T522	3		T488	3		T452	13
values[51]	253	1			T522	4		T488	1		T452	3
values[52]	287	1			T522	10		T488	1		T452	1
values[53]	275	1			T522	7		T488	1		T452	2
values[54]	269	1			T522	9		T452	2		T773	1
values[55]	306	1			T522	8		T452	6		T773	1
values[56]	258	1			T522	6		T452	7		T773	1
values[57]	273	1			T522	23		T452	5		T773	1
values[58]	225	1			T522	5		T452	7		T773	1
values[59]	222	1			T522	3		T452	5		T773	1
values[60]	225	1			T522	11		T452	3		T773	1
values[61]	191	1			T522	11		T452	8		T773	1
values[62]	175	1			T452	3		T773	1		T794	7
values[63]	213	1			T452	2		T773	1		T794	18
values[64]	197	1			T452	3		T773	1		T794	14
values[65]	176	1			T452	7		T773	1		T794	7
values[66]	162	1			T452	11		T773	1		T794	7
values[67]	158	1			T452	9		T773	1		T794	13
values[68]	157	1			T452	7		T773	1		T794	11
values[69]	87	1			T452	4		T773	1		T794	8
values[70]	73	1			T452	2		T773	1		T468	4
values[71]	84	1			T452	6		T773	1		T468	6
values[72]	62	1			T452	3		T773	1		T468	9
values[73]	70	1			T452	10		T773	1		T468	6
values[74]	71	1			T452	10		T773	1		T468	4
values[75]	82	1			T452	10		T773	1		T468	1
values[76]	81	1			T452	10		T773	1		T767	1
values[77]	43	1			T773	1		T767	1		T812	3
values[78]	41	1			T773	1		T767	1		T812	2
values[79]	27	1			T773	1		T767	1		T812	1
values[80]	26	1			T773	1		T767	1		T812	4
values[81]	23	1			T773	1		T767	1		T812	3
values[82]	23	1			T773	1		T767	1		T812	3
values[83]	24	1			T773	1		T767	1		T812	3
values[84]	24	1			T773	1		T767	1		T812	1
values[85]	30	1			T773	1		T767	1		T812	4
values[86]	30	1			T773	1		T767	1		T812	3
values[87]	25	1			T773	1		T767	1		T812	3
values[88]	32	1			T773	1		T767	1		T812	3
values[89]	30	1			T773	1		T767	1		T812	1
values[90]	29	1			T773	1		T767	1		T812	2
values[91]	34	1			T773	1		T767	1		T812	1
values[92]	31	1			T773	1		T767	1		T812	2
values[93]	31	1			T773	1		T767	1		T812	3
values[94]	43	1			T773	1		T767	1		T812	5
values[95]	41	1			T773	5		T767	1		T812	7
values[96]	36	1			T773	1		T767	1		T812	2
values[97]	43	1			T773	6		T767	1		T812	4
values[98]	51	1			T773	1		T767	1		T812	4
values[99]	41	1			T773	1		T767	1		T812	1
values[100]	58	1			T773	3		T767	1		T812	2
values[101]	56	1			T773	3		T767	1		T812	3
values[102]	51	1			T773	4		T767	1		T812	5
values[103]	44	1			T773	5		T767	1		T812	3
values[104]	40	1			T773	4		T767	1		T812	1
values[105]	30	1			T773	1		T767	1		T812	2
values[106]	43	1			T773	2		T767	1		T812	3
values[107]	49	1			T773	2		T767	1		T812	3
values[108]	37	1			T773	2		T767	1		T812	5
values[109]	39	1			T773	6		T767	1		T812	3
values[110]	35	1			T773	2		T767	1		T812	1
values[111]	35	1			T773	2		T767	2		T812	2
values[112]	29	1			T773	1		T767	1		T812	1
values[113]	29	1			T773	1		T767	1		T812	1
values[114]	45	1			T773	2		T767	1		T812	2
values[115]	41	1			T773	2		T767	2		T812	2
values[116]	55	1			T773	11		T767	1		T812	2
values[117]	46	1			T773	1		T767	4		T812	6
values[118]	61	1			T773	1		T767	1		T812	6
values[119]	49	1			T773	4		T767	1		T812	3
values[120]	57	1			T773	4		T767	10		T812	2
values[121]	64	1			T773	5		T767	6		T812	4
values[122]	37	1			T773	3		T767	3		T812	4
values[123]	48	1			T773	1		T767	5		T812	3
values[124]	54	1			T773	2		T767	1		T812	1
values[125]	66	1			T773	3		T767	1		T812	14
values[126]	114	1			T773	1		T767	1		T812	26
values[127]	651	1			T773	32		T767	27		T812	101
values[128]	4401	1			T773	306		T767	290		T812	50