Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.46 93.77 95.47 94.50 97.53 99.58


Total tests in report: 2919
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.11 40.11 45.12 45.12 46.68 46.68 27.59 27.59 63.23 63.23 57.87 57.87 0.14 0.14 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3221824895
47.82 7.72 49.41 4.29 56.17 9.49 27.82 0.23 69.58 6.35 83.04 25.17 0.92 0.78 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3244388868
53.02 5.20 60.60 11.18 63.53 7.36 30.33 2.51 79.70 10.12 83.04 0.00 0.92 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3837964890
57.18 4.16 69.58 8.98 64.55 1.02 37.83 7.50 79.94 0.24 83.04 0.00 8.13 7.21 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.1288460791
60.76 3.58 75.85 6.27 68.45 3.90 45.08 7.25 82.26 2.31 84.62 1.57 8.33 0.20 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.348309031
64.17 3.41 75.85 0.00 68.87 0.42 45.08 0.00 82.29 0.03 84.62 0.00 28.34 20.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.2553284475
67.24 3.07 80.75 4.90 72.60 3.73 48.58 3.50 84.00 1.71 89.16 4.55 28.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2863093927
69.86 2.62 80.75 0.00 72.60 0.00 64.33 15.75 84.00 0.00 89.16 0.00 28.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1346122377
72.27 2.41 80.75 0.00 72.60 0.00 64.33 0.00 84.00 0.00 89.16 0.00 42.80 14.46 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.892323880
74.46 2.19 81.95 1.20 75.10 2.50 69.38 5.05 85.74 1.74 89.34 0.17 45.25 2.44 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.4086273927
76.44 1.99 81.95 0.00 75.10 0.00 69.38 0.00 85.74 0.00 89.34 0.00 57.16 11.91 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3770057822
77.99 1.54 81.99 0.04 77.06 1.96 69.38 0.00 85.76 0.02 89.34 0.00 64.40 7.24 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.3455561861
79.43 1.45 82.10 0.12 77.16 0.10 77.48 8.11 85.93 0.17 89.51 0.17 64.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.2034607783
80.87 1.44 84.54 2.43 79.27 2.11 79.06 1.58 88.43 2.50 89.51 0.00 64.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3813784518
82.15 1.28 86.35 1.81 80.42 1.15 80.61 1.55 89.53 1.10 91.61 2.10 64.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.2612216385
83.33 1.18 86.35 0.00 80.59 0.17 80.61 0.00 89.56 0.03 91.61 0.00 71.25 6.85 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.243295858
84.48 1.15 88.30 1.95 81.69 1.11 82.96 2.35 90.36 0.80 92.31 0.70 71.25 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3098667704
85.48 1.00 88.30 0.00 81.69 0.00 82.96 0.00 90.36 0.00 92.31 0.00 77.26 6.02 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3728963802
86.37 0.89 89.07 0.77 82.00 0.31 82.98 0.01 90.73 0.37 96.15 3.85 77.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3100637539
87.23 0.87 89.07 0.00 82.00 0.00 82.98 0.00 90.73 0.00 96.15 0.00 82.46 5.19 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.968838992
88.04 0.80 89.92 0.84 82.72 0.72 85.34 2.36 91.62 0.88 96.15 0.00 82.47 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.793495153
88.81 0.77 89.92 0.01 83.40 0.68 85.37 0.03 91.71 0.09 96.15 0.00 86.30 3.83 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.1700536629
89.41 0.60 90.64 0.73 85.40 2.00 85.77 0.39 92.11 0.41 96.15 0.00 86.36 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1735208213
89.98 0.57 90.64 0.00 85.40 0.00 85.77 0.00 92.11 0.00 96.15 0.00 89.78 3.42 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2047827218
90.44 0.46 90.64 0.00 85.40 0.01 85.77 0.00 92.11 0.00 96.15 0.00 92.56 2.78 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.812697125
90.88 0.44 90.66 0.01 87.61 2.21 85.77 0.00 92.11 0.00 96.15 0.00 92.97 0.41 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.247659966
91.25 0.37 91.46 0.81 87.95 0.34 86.46 0.70 92.31 0.19 96.33 0.17 92.97 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1597280224
91.54 0.29 91.46 0.00 87.95 0.00 88.22 1.76 92.31 0.00 96.33 0.00 92.97 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.4164579275
91.82 0.27 91.47 0.01 87.96 0.01 89.85 1.63 92.31 0.00 96.33 0.00 92.97 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.462306979
92.08 0.26 91.47 0.00 87.97 0.01 89.85 0.00 92.31 0.00 96.33 0.00 94.55 1.57 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.2709264593
92.34 0.26 92.25 0.77 88.26 0.29 90.17 0.32 92.48 0.17 96.33 0.00 94.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.1988090348
92.59 0.25 92.69 0.45 88.79 0.53 90.40 0.23 92.75 0.27 96.33 0.00 94.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4009189001
92.83 0.24 92.69 0.00 88.79 0.00 90.40 0.00 92.75 0.00 96.33 0.00 96.01 1.46 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1417156120
93.04 0.22 92.69 0.00 88.79 0.00 91.70 1.30 92.75 0.00 96.33 0.00 96.01 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1127775380
93.25 0.21 93.08 0.39 89.20 0.41 91.77 0.07 93.14 0.39 96.33 0.00 96.01 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3916692741
93.46 0.21 93.08 0.00 89.35 0.15 91.77 0.00 93.14 0.00 96.33 0.00 97.10 1.09 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2345489746
93.66 0.20 93.29 0.21 90.30 0.95 91.78 0.01 93.16 0.02 96.33 0.00 97.10 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.73673160
93.83 0.17 93.85 0.55 90.53 0.23 91.92 0.14 93.27 0.11 96.33 0.00 97.10 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.362177509
93.97 0.14 93.88 0.04 90.87 0.34 91.96 0.04 93.66 0.39 96.33 0.00 97.10 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3587506865
94.09 0.13 93.88 0.00 91.13 0.25 91.96 0.00 93.69 0.03 96.33 0.00 97.57 0.47 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.3066798326
94.21 0.12 93.88 0.00 91.13 0.00 92.65 0.70 93.69 0.00 96.33 0.00 97.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.2440396528
94.31 0.10 94.07 0.19 91.26 0.13 92.83 0.17 93.80 0.11 96.33 0.00 97.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2776239630
94.40 0.09 94.07 0.00 91.26 0.00 93.37 0.54 93.80 0.00 96.33 0.00 97.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.225900897
94.48 0.08 94.23 0.15 91.37 0.11 93.49 0.12 93.92 0.12 96.33 0.00 97.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.214538391
94.56 0.08 94.29 0.06 91.41 0.05 93.64 0.15 93.96 0.03 96.50 0.17 97.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.3951681913
94.64 0.08 94.29 0.00 91.86 0.45 93.64 0.00 93.96 0.00 96.50 0.00 97.58 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.2143948956
94.70 0.06 94.39 0.11 91.88 0.01 93.77 0.13 93.96 0.00 96.50 0.00 97.67 0.09 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2430021509
94.75 0.06 94.40 0.01 92.03 0.16 93.77 0.00 94.13 0.18 96.50 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1065339125
94.80 0.05 94.43 0.03 92.09 0.05 93.94 0.17 94.17 0.04 96.50 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.1088687873
94.85 0.05 94.46 0.03 92.11 0.02 93.98 0.04 94.20 0.02 96.68 0.17 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2847301847
94.90 0.05 94.46 0.00 92.11 0.00 94.26 0.28 94.20 0.00 96.68 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1300934734
94.94 0.04 94.46 0.00 92.18 0.07 94.26 0.00 94.22 0.02 96.68 0.00 97.83 0.15 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.3498628309
94.98 0.04 94.47 0.01 92.20 0.01 94.26 0.00 94.24 0.02 96.85 0.17 97.84 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.930537250
95.02 0.04 94.54 0.07 92.20 0.00 94.41 0.15 94.25 0.01 96.85 0.00 97.84 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2589215811
95.05 0.04 94.55 0.01 92.21 0.01 94.42 0.01 94.26 0.01 97.03 0.17 97.85 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.2087213396
95.09 0.04 94.55 0.01 92.22 0.01 94.43 0.01 94.26 0.01 97.20 0.17 97.86 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.294458478
95.12 0.04 94.56 0.01 92.23 0.01 94.43 0.00 94.27 0.01 97.38 0.17 97.87 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.2529244289
95.16 0.03 94.56 0.01 92.29 0.06 94.50 0.07 94.34 0.06 97.38 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.536299676
95.19 0.03 94.56 0.00 92.49 0.20 94.50 0.00 94.34 0.00 97.38 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.3553875633
95.22 0.03 94.56 0.00 92.51 0.02 94.50 0.00 94.34 0.00 97.38 0.00 98.05 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.4290786662
95.25 0.03 94.60 0.04 92.62 0.11 94.54 0.04 94.34 0.00 97.38 0.00 98.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.469449612
95.28 0.03 94.60 0.00 92.62 0.01 94.54 0.00 94.34 0.00 97.38 0.00 98.23 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3445399662
95.31 0.03 94.60 0.00 92.62 0.00 94.54 0.00 94.34 0.00 97.55 0.17 98.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.3231944951
95.34 0.02 94.67 0.07 92.65 0.03 94.55 0.01 94.39 0.05 97.55 0.00 98.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.368769137
95.36 0.02 94.67 0.01 92.67 0.02 94.66 0.11 94.39 0.00 97.55 0.00 98.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4116367717
95.38 0.02 94.67 0.00 92.81 0.13 94.66 0.00 94.39 0.00 97.55 0.00 98.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.850926542
95.40 0.02 94.73 0.07 92.86 0.05 94.66 0.00 94.40 0.02 97.55 0.00 98.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.2087556322
95.43 0.02 94.80 0.07 92.90 0.05 94.66 0.01 94.42 0.02 97.55 0.00 98.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.4207271745
95.45 0.02 94.80 0.00 92.92 0.01 94.66 0.00 94.42 0.00 97.55 0.00 98.33 0.11 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3417224517
95.46 0.02 94.80 0.00 92.92 0.00 94.77 0.11 94.42 0.00 97.55 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4106877616
95.48 0.02 94.80 0.00 92.93 0.02 94.77 0.00 94.42 0.00 97.55 0.00 98.41 0.08 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.4259655035
95.50 0.02 94.80 0.00 92.99 0.05 94.77 0.00 94.43 0.02 97.55 0.00 98.44 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1522964566
95.51 0.02 94.80 0.00 93.08 0.09 94.77 0.00 94.43 0.00 97.55 0.00 98.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.751043096
95.53 0.01 94.80 0.00 93.08 0.00 94.86 0.08 94.43 0.00 97.55 0.00 98.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.350808023
95.54 0.01 94.80 0.00 93.09 0.01 94.86 0.00 94.43 0.00 97.55 0.00 98.51 0.07 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1578572798
95.55 0.01 94.81 0.01 93.13 0.05 94.86 0.00 94.45 0.02 97.55 0.00 98.51 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1410338605
95.56 0.01 94.81 0.00 93.13 0.00 94.86 0.00 94.45 0.00 97.55 0.00 98.58 0.07 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1657795010
95.57 0.01 94.81 0.00 93.14 0.01 94.92 0.06 94.45 0.00 97.55 0.00 98.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.676188063
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95.86 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.19 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1931255505
95.86 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.20 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3881733610
95.86 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.21 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4192879451
95.86 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.22 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345822358
95.86 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.24 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.1582951380
95.87 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.25 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.494040048
95.87 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.26 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155910228
95.87 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.27 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.2852868991
95.87 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.28 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.1666980136
95.87 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.30 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.963134353
95.88 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.31 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.307168690
95.88 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.32 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985921582
95.88 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.33 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2152688382
95.88 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.34 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.942319337
95.88 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.35 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413163569
95.89 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.37 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.2500837762
95.89 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.38 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.2646915431
95.89 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.39 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291448630
95.89 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.40 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.3575675962
95.89 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.41 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1414520283
95.89 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.42 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.4039283550
95.90 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.44 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.280291835
95.90 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.45 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596303276
95.90 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.46 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1873240930
95.90 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.47 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040882066
95.90 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.48 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.4130911163
95.91 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.49 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.706708407
95.91 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.51 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.3775321239
95.91 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.52 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329219984
95.91 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.53 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.1188327032
95.91 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.54 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.2337222329
95.92 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.55 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.399350777
95.92 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.57 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.3499186659
95.92 0.01 94.87 0.00 93.67 0.00 95.37 0.00 94.48 0.00 97.55 0.00 99.58 0.01 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1825985018
95.92 0.01 94.87 0.00 93.67 0.00 95.39 0.01 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1494472869
95.92 0.01 94.87 0.00 93.68 0.01 95.39 0.00 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.3770359170
95.93 0.01 94.87 0.00 93.69 0.01 95.39 0.00 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3890842001
95.93 0.01 94.87 0.00 93.70 0.01 95.39 0.00 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.867150720
95.93 0.01 94.87 0.00 93.71 0.01 95.39 0.00 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.621720535
95.93 0.01 94.87 0.00 93.72 0.01 95.39 0.00 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.3358605251
95.93 0.01 94.87 0.00 93.72 0.00 95.40 0.01 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.71171699
95.93 0.01 94.87 0.01 93.72 0.00 95.40 0.01 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.73883537
95.94 0.01 94.87 0.00 93.72 0.00 95.41 0.01 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2287099516
95.94 0.01 94.87 0.00 93.72 0.00 95.42 0.01 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.1357636141
95.94 0.01 94.88 0.01 93.72 0.00 95.42 0.01 94.48 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3386349629
95.94 0.01 94.88 0.00 93.72 0.00 95.42 0.00 94.49 0.01 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.175252837
95.94 0.01 94.88 0.00 93.72 0.00 95.42 0.00 94.50 0.01 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3424150807
95.94 0.01 94.88 0.00 93.73 0.01 95.42 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.872933886
95.94 0.01 94.88 0.00 93.73 0.01 95.42 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.833412074
95.95 0.01 94.88 0.00 93.74 0.01 95.42 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.552743414
95.95 0.01 94.88 0.00 93.74 0.00 95.43 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.156928861
95.95 0.01 94.88 0.00 93.75 0.01 95.43 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.3083130479
95.95 0.01 94.88 0.01 93.75 0.00 95.44 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.2286872673
95.95 0.01 94.88 0.00 93.75 0.00 95.44 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1489298942
95.95 0.01 94.88 0.00 93.75 0.00 95.45 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.2010839280
95.95 0.01 94.88 0.00 93.75 0.00 95.45 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4214143877
95.95 0.01 94.88 0.00 93.75 0.00 95.45 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2568099180
95.95 0.01 94.88 0.00 93.75 0.01 95.45 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3358359838
95.95 0.01 94.88 0.00 93.75 0.01 95.45 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3003492501
95.95 0.01 94.88 0.00 93.76 0.01 95.45 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3055989582
95.95 0.01 94.88 0.00 93.76 0.01 95.45 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.3814503736
95.95 0.01 94.88 0.00 93.76 0.01 95.45 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.971592339
95.96 0.01 94.88 0.00 93.77 0.01 95.45 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1255072963
95.96 0.01 94.88 0.00 93.77 0.01 95.45 0.00 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1534346725
95.96 0.01 94.88 0.00 93.77 0.00 95.46 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.687038870
95.96 0.01 94.88 0.00 93.77 0.00 95.46 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3475808552
95.96 0.01 94.88 0.00 93.77 0.00 95.46 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2656878244
95.96 0.01 94.88 0.00 93.77 0.00 95.46 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.904121343
95.96 0.01 94.88 0.00 93.77 0.00 95.47 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.587117121
95.96 0.01 94.88 0.00 93.77 0.00 95.47 0.01 94.50 0.00 97.55 0.00 99.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.214927269

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.619573669
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.4153465303
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.600029237
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1753478783
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.1070699748
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2035835033
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3104248982
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.2874485358
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.747763065
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.1369679641
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.4044909478
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3968355487
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/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2399246941
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/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2360491949



Total test records in report: 2919
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.233316766 Sep 02 02:08:13 AM UTC 24 Sep 02 02:10:28 AM UTC 24 2960364424 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.920403744 Sep 02 02:08:11 AM UTC 24 Sep 02 02:12:50 AM UTC 24 2923669352 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3221824895 Sep 02 02:09:06 AM UTC 24 Sep 02 02:13:02 AM UTC 24 2284646519 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.4207271745 Sep 02 02:08:44 AM UTC 24 Sep 02 02:13:32 AM UTC 24 3172154888 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.2612216385 Sep 02 02:07:16 AM UTC 24 Sep 02 02:13:37 AM UTC 24 3862404712 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.97235083 Sep 02 02:09:59 AM UTC 24 Sep 02 02:13:54 AM UTC 24 2782585772 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.2445511509 Sep 02 02:08:57 AM UTC 24 Sep 02 02:14:08 AM UTC 24 3534975068 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.536299676 Sep 02 02:09:40 AM UTC 24 Sep 02 02:14:29 AM UTC 24 3645137042 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.2286872673 Sep 02 02:09:57 AM UTC 24 Sep 02 02:14:34 AM UTC 24 2706479148 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.2637617509 Sep 02 02:10:08 AM UTC 24 Sep 02 02:15:13 AM UTC 24 3139242744 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.3430550908 Sep 02 02:09:08 AM UTC 24 Sep 02 02:15:24 AM UTC 24 3358987590 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.1088687873 Sep 02 02:09:18 AM UTC 24 Sep 02 02:15:29 AM UTC 24 3001913090 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.1856089137 Sep 02 02:09:45 AM UTC 24 Sep 02 02:15:31 AM UTC 24 2974754846 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.348309031 Sep 02 02:08:05 AM UTC 24 Sep 02 02:16:55 AM UTC 24 4629080156 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.512309144 Sep 02 02:07:44 AM UTC 24 Sep 02 02:17:06 AM UTC 24 4431149100 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.1994626472 Sep 02 02:07:19 AM UTC 24 Sep 02 02:17:38 AM UTC 24 3968924774 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.278686294 Sep 02 02:09:12 AM UTC 24 Sep 02 02:17:47 AM UTC 24 3756523696 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1246328969 Sep 02 02:09:45 AM UTC 24 Sep 02 02:18:18 AM UTC 24 3874812840 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.985465569 Sep 02 02:13:54 AM UTC 24 Sep 02 02:18:19 AM UTC 24 3175084846 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.1988090348 Sep 02 02:09:59 AM UTC 24 Sep 02 02:18:46 AM UTC 24 3758760905 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.4164579275 Sep 02 02:11:38 AM UTC 24 Sep 02 02:18:56 AM UTC 24 3354401208 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1956292940 Sep 02 02:10:02 AM UTC 24 Sep 02 02:18:56 AM UTC 24 3722258022 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.3083130479 Sep 02 02:09:18 AM UTC 24 Sep 02 02:19:09 AM UTC 24 4376538711 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3463962025 Sep 02 02:11:57 AM UTC 24 Sep 02 02:19:10 AM UTC 24 3175852424 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.848868299 Sep 02 02:13:54 AM UTC 24 Sep 02 02:19:16 AM UTC 24 2870491020 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.36116704 Sep 02 02:15:17 AM UTC 24 Sep 02 02:19:19 AM UTC 24 2281487626 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2354013547 Sep 02 02:16:31 AM UTC 24 Sep 02 02:19:19 AM UTC 24 2975462734 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1494472869 Sep 02 02:14:48 AM UTC 24 Sep 02 02:19:36 AM UTC 24 2689034627 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1467466800 Sep 02 02:16:30 AM UTC 24 Sep 02 02:19:37 AM UTC 24 3037550980 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.551952411 Sep 02 02:07:57 AM UTC 24 Sep 02 02:19:56 AM UTC 24 4709683596 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.1614828748 Sep 02 02:07:35 AM UTC 24 Sep 02 02:20:09 AM UTC 24 4581320824 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.414632124 Sep 02 02:10:03 AM UTC 24 Sep 02 02:20:55 AM UTC 24 4274275694 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1037794971 Sep 02 02:19:15 AM UTC 24 Sep 02 02:21:19 AM UTC 24 2049948743 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4106877616 Sep 02 02:16:28 AM UTC 24 Sep 02 02:21:26 AM UTC 24 3631724641 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2221613763 Sep 02 02:19:27 AM UTC 24 Sep 02 02:21:39 AM UTC 24 2855279582 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4116367717 Sep 02 02:09:55 AM UTC 24 Sep 02 02:21:46 AM UTC 24 4764903635 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.2650837196 Sep 02 02:10:08 AM UTC 24 Sep 02 02:21:53 AM UTC 24 4865587836 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2601463154 Sep 02 02:10:07 AM UTC 24 Sep 02 02:22:03 AM UTC 24 4163955600 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.3951681913 Sep 02 02:09:43 AM UTC 24 Sep 02 02:22:10 AM UTC 24 5580991304 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.2213450281 Sep 02 02:10:10 AM UTC 24 Sep 02 02:22:12 AM UTC 24 4473953008 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.68235035 Sep 02 02:09:47 AM UTC 24 Sep 02 02:22:26 AM UTC 24 4343043212 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1733073774 Sep 02 02:08:56 AM UTC 24 Sep 02 02:23:04 AM UTC 24 4746601992 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.1769622525 Sep 02 02:10:02 AM UTC 24 Sep 02 02:23:16 AM UTC 24 5551944414 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1255072963 Sep 02 02:09:36 AM UTC 24 Sep 02 02:23:49 AM UTC 24 5188220872 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.219952353 Sep 02 02:10:00 AM UTC 24 Sep 02 02:24:42 AM UTC 24 7150393483 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.2440396528 Sep 02 02:14:51 AM UTC 24 Sep 02 02:25:15 AM UTC 24 4290967760 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4207566892 Sep 02 02:14:16 AM UTC 24 Sep 02 02:25:59 AM UTC 24 5240376256 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.3872863697 Sep 02 02:19:50 AM UTC 24 Sep 02 02:27:09 AM UTC 24 3971850472 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.392907505 Sep 02 02:23:56 AM UTC 24 Sep 02 02:27:28 AM UTC 24 2639269204 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2129741990 Sep 02 02:12:03 AM UTC 24 Sep 02 02:27:41 AM UTC 24 5589830638 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.2339477942 Sep 02 02:25:17 AM UTC 24 Sep 02 02:29:32 AM UTC 24 2542374500 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2483505216 Sep 02 02:24:28 AM UTC 24 Sep 02 02:29:41 AM UTC 24 3355167800 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3080059745 Sep 02 02:11:36 AM UTC 24 Sep 02 02:29:55 AM UTC 24 5211703469 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4080122078 Sep 02 02:22:18 AM UTC 24 Sep 02 02:30:08 AM UTC 24 7769087222 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3065470122 Sep 02 02:24:13 AM UTC 24 Sep 02 02:30:29 AM UTC 24 3566810834 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3295681964 Sep 02 02:26:36 AM UTC 24 Sep 02 02:30:31 AM UTC 24 2803966520 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3832355138 Sep 02 02:23:40 AM UTC 24 Sep 02 02:31:00 AM UTC 24 3639613248 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.159366888 Sep 02 02:11:59 AM UTC 24 Sep 02 02:31:41 AM UTC 24 5700486120 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4214143877 Sep 02 02:24:46 AM UTC 24 Sep 02 02:32:15 AM UTC 24 6332691940 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3475808552 Sep 02 02:28:15 AM UTC 24 Sep 02 02:32:20 AM UTC 24 2763499993 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.2900398705 Sep 02 02:08:45 AM UTC 24 Sep 02 02:32:21 AM UTC 24 9199945688 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1390945862 Sep 02 02:23:38 AM UTC 24 Sep 02 02:32:40 AM UTC 24 5112332712 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.424232565 Sep 02 02:28:04 AM UTC 24 Sep 02 02:32:44 AM UTC 24 2569899062 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.523811036 Sep 02 02:27:26 AM UTC 24 Sep 02 02:33:02 AM UTC 24 2868527796 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3632032303 Sep 02 02:23:48 AM UTC 24 Sep 02 02:33:07 AM UTC 24 3859456744 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.2034607783 Sep 02 02:19:00 AM UTC 24 Sep 02 02:33:12 AM UTC 24 9315294120 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.4086273927 Sep 02 02:28:14 AM UTC 24 Sep 02 02:33:57 AM UTC 24 2726506612 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.787209280 Sep 02 02:14:06 AM UTC 24 Sep 02 02:34:03 AM UTC 24 6536527112 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3193249390 Sep 02 02:25:03 AM UTC 24 Sep 02 02:34:08 AM UTC 24 6650755052 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.2155827802 Sep 02 02:25:08 AM UTC 24 Sep 02 02:34:16 AM UTC 24 4058591950 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.1906072724 Sep 02 02:25:33 AM UTC 24 Sep 02 02:35:04 AM UTC 24 3819283000 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.2369589257 Sep 02 02:31:39 AM UTC 24 Sep 02 02:36:10 AM UTC 24 2728071240 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.2586357782 Sep 02 02:31:52 AM UTC 24 Sep 02 02:35:09 AM UTC 24 2443836670 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2228241372 Sep 02 02:24:59 AM UTC 24 Sep 02 02:35:13 AM UTC 24 6145113032 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1339185226 Sep 02 02:24:47 AM UTC 24 Sep 02 02:35:22 AM UTC 24 6766857000 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.578905821 Sep 02 02:23:02 AM UTC 24 Sep 02 02:35:23 AM UTC 24 6739626090 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.3404873942 Sep 02 02:16:21 AM UTC 24 Sep 02 02:35:54 AM UTC 24 11146589502 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1542443561 Sep 02 02:23:53 AM UTC 24 Sep 02 02:36:17 AM UTC 24 4923428284 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3156799134 Sep 02 02:14:46 AM UTC 24 Sep 02 02:36:17 AM UTC 24 7228227712 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1462183576 Sep 02 02:24:24 AM UTC 24 Sep 02 02:36:22 AM UTC 24 18696366572 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.2213414720 Sep 02 02:28:18 AM UTC 24 Sep 02 02:36:26 AM UTC 24 4648926936 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2110925434 Sep 02 02:25:18 AM UTC 24 Sep 02 02:36:41 AM UTC 24 4573600680 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1477234584 Sep 02 02:25:16 AM UTC 24 Sep 02 02:36:41 AM UTC 24 5681749400 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.870998969 Sep 02 02:30:30 AM UTC 24 Sep 02 02:36:42 AM UTC 24 3874897370 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2026587612 Sep 02 02:14:30 AM UTC 24 Sep 02 02:36:45 AM UTC 24 9765827788 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.3948479506 Sep 02 02:31:38 AM UTC 24 Sep 02 02:36:49 AM UTC 24 3092716455 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2847301847 Sep 02 02:23:18 AM UTC 24 Sep 02 02:39:01 AM UTC 24 6919371840 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.3603245217 Sep 02 02:35:25 AM UTC 24 Sep 02 02:39:16 AM UTC 24 2927042080 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2955609993 Sep 02 02:31:23 AM UTC 24 Sep 02 02:39:25 AM UTC 24 4011785056 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.501861247 Sep 02 02:36:15 AM UTC 24 Sep 02 02:41:11 AM UTC 24 2841613672 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.2039348267 Sep 02 02:24:46 AM UTC 24 Sep 02 02:41:13 AM UTC 24 5586431640 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.156928861 Sep 02 02:36:49 AM UTC 24 Sep 02 02:41:19 AM UTC 24 2936029280 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.480746319 Sep 02 02:34:30 AM UTC 24 Sep 02 02:41:41 AM UTC 24 4475077182 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2656878244 Sep 02 02:33:27 AM UTC 24 Sep 02 02:41:44 AM UTC 24 2766310656 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.2801200410 Sep 02 02:25:33 AM UTC 24 Sep 02 02:41:56 AM UTC 24 5410832560 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1534346725 Sep 02 02:25:51 AM UTC 24 Sep 02 02:41:59 AM UTC 24 4938184250 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2285937273 Sep 02 02:21:49 AM UTC 24 Sep 02 02:42:11 AM UTC 24 7869231816 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2055715072 Sep 02 02:24:45 AM UTC 24 Sep 02 02:42:22 AM UTC 24 8602235952 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1748527171 Sep 02 02:37:44 AM UTC 24 Sep 02 02:42:24 AM UTC 24 3020485946 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.2967866148 Sep 02 02:38:56 AM UTC 24 Sep 02 02:42:43 AM UTC 24 2989655644 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.3099505753 Sep 02 02:38:54 AM UTC 24 Sep 02 02:42:53 AM UTC 24 2570843824 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.3192024595 Sep 02 02:36:37 AM UTC 24 Sep 02 02:43:02 AM UTC 24 3500384284 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.1849167468 Sep 02 02:38:44 AM UTC 24 Sep 02 02:43:11 AM UTC 24 2856160519 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.2201007638 Sep 02 02:12:03 AM UTC 24 Sep 02 02:44:16 AM UTC 24 24779988132 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1986077563 Sep 02 02:09:52 AM UTC 24 Sep 02 02:44:16 AM UTC 24 8324108346 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.4274528044 Sep 02 02:39:02 AM UTC 24 Sep 02 02:44:17 AM UTC 24 3663552102 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2443170751 Sep 02 02:38:23 AM UTC 24 Sep 02 02:44:35 AM UTC 24 3054103757 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.462306979 Sep 02 02:32:18 AM UTC 24 Sep 02 02:44:59 AM UTC 24 3462704698 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.3913756321 Sep 02 02:40:04 AM UTC 24 Sep 02 02:45:39 AM UTC 24 2917373736 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1300934734 Sep 02 02:35:42 AM UTC 24 Sep 02 02:45:54 AM UTC 24 7609043608 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.2054723352 Sep 02 02:39:01 AM UTC 24 Sep 02 02:46:27 AM UTC 24 3497476296 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.895393267 Sep 02 02:37:56 AM UTC 24 Sep 02 02:46:55 AM UTC 24 10094210269 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.676188063 Sep 02 02:39:01 AM UTC 24 Sep 02 02:47:39 AM UTC 24 5483313753 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.913167806 Sep 02 02:35:30 AM UTC 24 Sep 02 02:48:08 AM UTC 24 3186061680 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3386349629 Sep 02 02:43:10 AM UTC 24 Sep 02 02:48:11 AM UTC 24 2451890760 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.621720535 Sep 02 02:21:35 AM UTC 24 Sep 02 02:49:56 AM UTC 24 10321309688 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3328932626 Sep 02 02:25:01 AM UTC 24 Sep 02 02:50:04 AM UTC 24 8884325267 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.3325349771 Sep 02 02:47:04 AM UTC 24 Sep 02 02:51:21 AM UTC 24 2889666782 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.779017937 Sep 02 02:44:23 AM UTC 24 Sep 02 02:51:33 AM UTC 24 4434537320 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4009189001 Sep 02 02:42:58 AM UTC 24 Sep 02 02:51:48 AM UTC 24 4698553208 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1597280224 Sep 02 02:31:36 AM UTC 24 Sep 02 02:52:07 AM UTC 24 10839564440 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.138952692 Sep 02 02:44:16 AM UTC 24 Sep 02 02:52:11 AM UTC 24 3940429480 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4013925183 Sep 02 02:38:42 AM UTC 24 Sep 02 02:52:26 AM UTC 24 5329027268 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.225900897 Sep 02 02:19:40 AM UTC 24 Sep 02 02:52:35 AM UTC 24 20343926479 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.987083143 Sep 02 02:23:50 AM UTC 24 Sep 02 02:52:45 AM UTC 24 12749822482 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3916692741 Sep 02 02:44:23 AM UTC 24 Sep 02 02:53:05 AM UTC 24 3559173860 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3806994803 Sep 02 02:35:28 AM UTC 24 Sep 02 02:53:22 AM UTC 24 6269238764 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2879169679 Sep 02 02:44:21 AM UTC 24 Sep 02 02:53:40 AM UTC 24 6022885205 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2718881124 Sep 02 02:38:59 AM UTC 24 Sep 02 02:53:50 AM UTC 24 9441704424 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.1357636141 Sep 02 02:38:51 AM UTC 24 Sep 02 02:53:53 AM UTC 24 8212896931 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.860242433 Sep 02 02:46:12 AM UTC 24 Sep 02 02:53:56 AM UTC 24 3270570480 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.214538391 Sep 02 02:23:24 AM UTC 24 Sep 02 02:54:24 AM UTC 24 24805731560 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2993475845 Sep 02 02:44:14 AM UTC 24 Sep 02 02:54:51 AM UTC 24 5264432844 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.628500471 Sep 02 02:31:05 AM UTC 24 Sep 02 02:54:51 AM UTC 24 7605607940 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1346122377 Sep 02 02:37:53 AM UTC 24 Sep 02 02:55:17 AM UTC 24 6700335624 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.4150694485 Sep 02 02:35:32 AM UTC 24 Sep 02 02:55:22 AM UTC 24 6671175128 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1691259870 Sep 02 02:44:14 AM UTC 24 Sep 02 02:55:36 AM UTC 24 4530279270 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2098142250 Sep 02 02:46:28 AM UTC 24 Sep 02 02:55:42 AM UTC 24 3413097736 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.368769137 Sep 02 02:40:03 AM UTC 24 Sep 02 02:56:33 AM UTC 24 6335744740 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2062338372 Sep 02 02:45:37 AM UTC 24 Sep 02 02:56:38 AM UTC 24 4484326296 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1788595289 Sep 02 02:45:35 AM UTC 24 Sep 02 02:56:39 AM UTC 24 3955943464 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.96567978 Sep 02 02:45:40 AM UTC 24 Sep 02 02:56:48 AM UTC 24 3908736932 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3533742244 Sep 02 02:44:24 AM UTC 24 Sep 02 02:57:06 AM UTC 24 5427783288 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3306565417 Sep 02 02:45:36 AM UTC 24 Sep 02 02:57:11 AM UTC 24 4868179968 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3837964890 Sep 02 02:44:00 AM UTC 24 Sep 02 02:57:12 AM UTC 24 5094280496 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2029046868 Sep 02 02:39:48 AM UTC 24 Sep 02 02:57:13 AM UTC 24 8670519808 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.285782659 Sep 02 02:36:48 AM UTC 24 Sep 02 02:57:18 AM UTC 24 6028894520 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3780553727 Sep 02 02:54:30 AM UTC 24 Sep 02 02:57:27 AM UTC 24 2191144390 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1506653153 Sep 02 02:50:45 AM UTC 24 Sep 02 02:57:37 AM UTC 24 7076208296 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.3377641126 Sep 02 02:54:33 AM UTC 24 Sep 02 02:57:40 AM UTC 24 2404868778 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3556987329 Sep 02 02:45:20 AM UTC 24 Sep 02 02:57:52 AM UTC 24 5169080330 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2571685916 Sep 02 02:47:33 AM UTC 24 Sep 02 02:59:29 AM UTC 24 4686929224 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4212182082 Sep 02 02:55:38 AM UTC 24 Sep 02 02:59:35 AM UTC 24 2729176296 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.276222376 Sep 02 02:53:30 AM UTC 24 Sep 02 02:59:37 AM UTC 24 4613188150 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3100637539 Sep 02 02:54:34 AM UTC 24 Sep 02 02:59:51 AM UTC 24 2783635700 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.1194638030 Sep 02 02:53:52 AM UTC 24 Sep 02 02:59:52 AM UTC 24 4269951014 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.2010839280 Sep 02 02:50:43 AM UTC 24 Sep 02 03:00:27 AM UTC 24 4304519516 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2766002175 Sep 02 02:36:59 AM UTC 24 Sep 02 03:00:30 AM UTC 24 7434345248 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4033209775 Sep 02 02:31:22 AM UTC 24 Sep 02 03:00:43 AM UTC 24 7289304512 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1333436412 Sep 02 02:53:42 AM UTC 24 Sep 02 03:00:59 AM UTC 24 6040849772 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4045575681 Sep 02 02:56:27 AM UTC 24 Sep 02 03:01:09 AM UTC 24 3227716419 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.1771454840 Sep 02 02:55:38 AM UTC 24 Sep 02 03:01:21 AM UTC 24 3135713921 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.1493771694 Sep 02 02:09:08 AM UTC 24 Sep 02 03:01:25 AM UTC 24 11827449924 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3890842001 Sep 02 02:52:09 AM UTC 24 Sep 02 03:01:34 AM UTC 24 4549887384 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1373914338 Sep 02 02:34:28 AM UTC 24 Sep 02 03:01:37 AM UTC 24 6831276504 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2287099516 Sep 02 02:53:30 AM UTC 24 Sep 02 03:01:45 AM UTC 24 4523535116 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.799455141 Sep 02 02:56:26 AM UTC 24 Sep 02 03:02:26 AM UTC 24 3623200340 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.1668673090 Sep 02 02:09:56 AM UTC 24 Sep 02 03:02:30 AM UTC 24 13802211010 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1554575793 Sep 02 02:53:10 AM UTC 24 Sep 02 03:02:33 AM UTC 24 6769589962 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2589215811 Sep 02 02:54:07 AM UTC 24 Sep 02 03:02:38 AM UTC 24 5425513171 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3424150807 Sep 02 02:53:51 AM UTC 24 Sep 02 03:03:06 AM UTC 24 5290135792 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3813784518 Sep 02 02:44:09 AM UTC 24 Sep 02 03:03:25 AM UTC 24 5681320620 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.3843337257 Sep 02 02:39:02 AM UTC 24 Sep 02 03:03:31 AM UTC 24 7173632568 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.867150720 Sep 02 02:53:26 AM UTC 24 Sep 02 03:03:46 AM UTC 24 6588590880 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.3426462056 Sep 02 02:34:25 AM UTC 24 Sep 02 03:04:15 AM UTC 24 7328679968 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.4279462811 Sep 02 02:48:47 AM UTC 24 Sep 02 03:04:29 AM UTC 24 7170882692 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3908846929 Sep 02 03:01:23 AM UTC 24 Sep 02 03:05:45 AM UTC 24 3227973042 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3955627135 Sep 02 03:01:41 AM UTC 24 Sep 02 03:06:09 AM UTC 24 2910457769 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.685815745 Sep 02 03:02:56 AM UTC 24 Sep 02 03:07:03 AM UTC 24 2935786214 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.1260883122 Sep 02 02:43:43 AM UTC 24 Sep 02 03:07:20 AM UTC 24 10165386900 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1213767631 Sep 02 03:03:58 AM UTC 24 Sep 02 03:07:47 AM UTC 24 2727200402 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.569812556 Sep 02 02:56:27 AM UTC 24 Sep 02 03:07:54 AM UTC 24 4891551000 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.511152478 Sep 02 02:31:22 AM UTC 24 Sep 02 03:08:05 AM UTC 24 8957671300 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.140525077 Sep 02 02:56:30 AM UTC 24 Sep 02 03:08:09 AM UTC 24 5082339977 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.1494976030 Sep 02 02:36:58 AM UTC 24 Sep 02 03:09:31 AM UTC 24 8959919368 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.793495153 Sep 02 02:48:01 AM UTC 24 Sep 02 03:10:01 AM UTC 24 13120539803 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.560600571 Sep 02 02:23:20 AM UTC 24 Sep 02 03:10:09 AM UTC 24 29038973075 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1842152037 Sep 02 03:00:06 AM UTC 24 Sep 02 03:10:34 AM UTC 24 6197144823 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.2104543686 Sep 02 03:01:19 AM UTC 24 Sep 02 03:10:54 AM UTC 24 4115260956 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.2002902684 Sep 02 03:03:15 AM UTC 24 Sep 02 03:11:23 AM UTC 24 10530349044 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.2216888224 Sep 02 02:48:30 AM UTC 24 Sep 02 03:13:21 AM UTC 24 13884859217 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.534243973 Sep 02 02:38:23 AM UTC 24 Sep 02 03:14:19 AM UTC 24 11341971450 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.363305400 Sep 02 02:59:29 AM UTC 24 Sep 02 03:17:45 AM UTC 24 7483555817 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2776239630 Sep 02 02:52:23 AM UTC 24 Sep 02 03:19:33 AM UTC 24 22888763800 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.175252837 Sep 02 02:52:27 AM UTC 24 Sep 02 03:19:59 AM UTC 24 24126637304 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3087535365 Sep 02 03:00:06 AM UTC 24 Sep 02 03:20:23 AM UTC 24 6883533659 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1662498 Sep 02 02:42:54 AM UTC 24 Sep 02 03:20:45 AM UTC 24 25103769714 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2094705307 Sep 02 03:02:12 AM UTC 24 Sep 02 03:21:06 AM UTC 24 5581692872 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3348908407 Sep 02 02:23:31 AM UTC 24 Sep 02 03:29:17 AM UTC 24 20343029949 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3098667704 Sep 02 03:02:22 AM UTC 24 Sep 02 03:30:02 AM UTC 24 5775777024 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.1280271562 Sep 02 03:30:39 AM UTC 24 Sep 02 03:33:41 AM UTC 24 3095389571 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.1558478207 Sep 02 02:59:28 AM UTC 24 Sep 02 03:34:11 AM UTC 24 23265267722 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.3712992851 Sep 02 03:34:19 AM UTC 24 Sep 02 03:41:11 AM UTC 24 5174733754 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.3138975942 Sep 02 02:10:00 AM UTC 24 Sep 02 03:42:25 AM UTC 24 18995185300 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.904121343 Sep 02 02:38:49 AM UTC 24 Sep 02 03:46:20 AM UTC 24 13228929138 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.350238497 Sep 02 02:25:28 AM UTC 24 Sep 02 03:48:55 AM UTC 24 19037131367 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.587117121 Sep 02 02:24:41 AM UTC 24 Sep 02 03:49:25 AM UTC 24 16661604880 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.864518524 Sep 02 03:43:02 AM UTC 24 Sep 02 03:50:12 AM UTC 24 2764878550 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.1874039397 Sep 02 03:50:02 AM UTC 24 Sep 02 03:53:13 AM UTC 24 2875116416 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3641992913 Sep 02 03:12:39 AM UTC 24 Sep 02 03:51:20 AM UTC 24 10512249155 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.2773462006 Sep 02 03:46:57 AM UTC 24 Sep 02 03:52:53 AM UTC 24 3256586164 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1127775380 Sep 02 02:11:59 AM UTC 24 Sep 02 03:53:36 AM UTC 24 42573477824 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2624960548 Sep 02 03:13:54 AM UTC 24 Sep 02 03:54:17 AM UTC 24 10751528146 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.1899687285 Sep 02 03:41:48 AM UTC 24 Sep 02 03:54:21 AM UTC 24 4332309608 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.3489600862 Sep 02 03:49:31 AM UTC 24 Sep 02 03:54:40 AM UTC 24 2974200366 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.2622513735 Sep 02 03:51:57 AM UTC 24 Sep 02 03:56:42 AM UTC 24 2900406002 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.4025833446 Sep 02 03:14:52 AM UTC 24 Sep 02 03:58:04 AM UTC 24 10773596655 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.3729706129 Sep 02 03:53:49 AM UTC 24 Sep 02 03:59:03 AM UTC 24 2673987112 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.2665645349 Sep 02 03:55:13 AM UTC 24 Sep 02 03:59:34 AM UTC 24 2931878046 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.2857958685 Sep 02 03:53:30 AM UTC 24 Sep 02 04:00:00 AM UTC 24 3247625552 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.1343783606 Sep 02 03:57:19 AM UTC 24 Sep 02 04:02:20 AM UTC 24 2762348640 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.3264008112 Sep 02 03:50:49 AM UTC 24 Sep 02 04:03:00 AM UTC 24 3310917976 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.3447386729 Sep 02 03:59:39 AM UTC 24 Sep 02 04:03:43 AM UTC 24 3378502220 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.3514120720 Sep 02 03:58:40 AM UTC 24 Sep 02 04:04:10 AM UTC 24 3328080338 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.71171699 Sep 02 03:02:30 AM UTC 24 Sep 02 04:04:13 AM UTC 24 20543952987 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2112256510 Sep 02 03:05:08 AM UTC 24 Sep 02 04:04:58 AM UTC 24 11121768728 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.4041769711 Sep 02 03:55:19 AM UTC 24 Sep 02 04:05:05 AM UTC 24 6413896920 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1025054173 Sep 02 03:11:47 AM UTC 24 Sep 02 04:05:57 AM UTC 24 11109607880 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.2039214562 Sep 02 03:55:15 AM UTC 24 Sep 02 04:06:02 AM UTC 24 5482404232 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3407492911 Sep 02 03:08:28 AM UTC 24 Sep 02 04:06:07 AM UTC 24 10615139682 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.3552669545 Sep 02 04:00:11 AM UTC 24 Sep 02 04:06:29 AM UTC 24 3103372098 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.1228660164 Sep 02 04:03:30 AM UTC 24 Sep 02 04:06:32 AM UTC 24 2736641140 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.2483112860 Sep 02 04:02:56 AM UTC 24 Sep 02 04:07:30 AM UTC 24 2643600428 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.825399400 Sep 02 04:00:36 AM UTC 24 Sep 02 04:07:47 AM UTC 24 2812386592 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.2229544064 Sep 02 04:04:21 AM UTC 24 Sep 02 04:08:35 AM UTC 24 2712439516 ps
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T442 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1675402559 Sep 02 03:11:15 AM UTC 24 Sep 02 04:11:57 AM UTC 24 11820210140 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.1485416045 Sep 02 04:07:25 AM UTC 24 Sep 02 04:12:30 AM UTC 24 3164905458 ps
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T19 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3587506865 Sep 02 04:07:29 AM UTC 24 Sep 02 04:14:40 AM UTC 24 3393333871 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.694834671 Sep 02 03:09:40 AM UTC 24 Sep 02 04:14:53 AM UTC 24 11576859432 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.2087556322 Sep 02 04:07:18 AM UTC 24 Sep 02 04:16:50 AM UTC 24 6733391486 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.827399175 Sep 02 04:05:52 AM UTC 24 Sep 02 04:16:51 AM UTC 24 4826526450 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.2087213396 Sep 02 04:05:51 AM UTC 24 Sep 02 04:18:01 AM UTC 24 4691075492 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.2315430389 Sep 02 03:54:12 AM UTC 24 Sep 02 04:18:54 AM UTC 24 6696204704 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.3088876290 Sep 02 03:20:10 AM UTC 24 Sep 02 04:19:28 AM UTC 24 31935363899 ps
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T116 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.3225677391 Sep 02 04:08:23 AM UTC 24 Sep 02 04:19:54 AM UTC 24 4370689886 ps
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