Summary for Variable cp_req_dly
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| big_delay |
500 |
1 |
|
|
T540 |
1 |
|
T541 |
1 |
|
T531 |
1 |
| small_delay |
643 |
1 |
|
|
T161 |
1 |
|
T269 |
1 |
|
T426 |
1 |
| zero |
657 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
Summary for Variable cp_rsp_dly
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| big_delay |
200 |
1 |
|
|
T531 |
1 |
|
T532 |
1 |
|
T473 |
1 |
| small_delay |
943 |
1 |
|
|
T161 |
1 |
|
T269 |
1 |
|
T426 |
1 |
| zero |
657 |
1 |
|
|
T94 |
1 |
|
T95 |
1 |
|
T96 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |