Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	500	1			T603	1		T750	2		T829	1
all_values[1]	470	1			T521	2		T522	1		T459	1
all_values[2]	498	1			T521	1		T522	2		T603	1
all_values[3]	496	1			T521	2		T522	1		T829	2
all_values[4]	493	1			T520	1		T522	3		T829	2
all_values[5]	538	1			T520	1		T521	1		T770	1
all_values[6]	510	1			T426	1		T521	2		T603	1
all_values[7]	515	1			T521	1		T603	1		T759	1
all_values[8]	511	1			T268	1		T426	1		T603	1
all_values[9]	521	1			T522	2		T603	1		T750	1
all_values[10]	513	1			T521	2		T829	1		T571	3
all_values[11]	484	1			T639	1		T521	2		T522	1
all_values[12]	472	1			T268	1		T521	4		T522	1
all_values[13]	513	1			T269	1		T520	1		T492	1
all_values[14]	533	1			T639	1		T521	1		T603	1
all_values[15]	486	1			T521	1		T522	2		T459	1
all_values[16]	483	1			T521	1		T522	1		T603	1
all_values[17]	509	1			T268	1		T520	1		T521	4
all_values[18]	498	1			T521	2		T829	5		T571	5
all_values[19]	524	1			T521	1		T522	1		T603	1
all_values[20]	540	1			T522	1		T751	6		T475	3
all_values[21]	494	1			T759	1		T571	6		T765	1
all_values[22]	504	1			T815	1		T492	1		T571	4
all_values[23]	485	1			T521	3		T603	1		T815	1
all_values[24]	517	1			T770	1		T603	1		T459	1
all_values[25]	508	1			T426	1		T816	1		T829	2
all_values[26]	549	1			T492	1		T750	1		T571	2
all_values[27]	533	1			T268	1		T521	1		T522	1
all_values[28]	477	1			T522	1		T603	1		T829	3
all_values[29]	473	1			T521	3		T492	1		T829	2
all_values[30]	519	1			T268	1		T521	3		T522	1
all_values[31]	510	1			T521	2		T492	1		T750	1
all_values[32]	539	1			T521	2		T492	1		T829	3
all_values[33]	486	1			T268	1		T521	1		T492	1
all_values[34]	523	1			T521	2		T459	1		T750	1
all_values[35]	515	1			T520	1		T522	1		T750	1
all_values[36]	493	1			T603	1		T459	1		T492	1
all_values[37]	505	1			T521	1		T522	2		T603	1
all_values[38]	538	1			T426	1		T522	1		T603	1
all_values[39]	479	1			T492	2		T750	2		T829	2
all_values[40]	503	1			T603	1		T750	2		T829	1
all_values[41]	503	1			T520	1		T521	2		T750	1
all_values[42]	552	1			T268	1		T521	3		T603	1
all_values[43]	497	1			T459	1		T759	1		T750	1
all_values[44]	500	1			T521	3		T603	1		T829	2
all_values[45]	484	1			T520	1		T521	2		T522	1
all_values[46]	528	1			T522	2		T750	2		T829	3
all_values[47]	462	1			T520	1		T521	1		T522	1
all_values[48]	496	1			T521	1		T603	1		T492	1
all_values[49]	494	1			T521	1		T770	1		T829	1