Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3622	1			T526	2		T518	1		T521	5
all_values[1]	3622	1			T526	1		T518	4		T510	3
all_values[2]	3583	1			T526	2		T510	5		T521	5
all_values[3]	3560	1			T526	3		T518	2		T521	8
all_values[4]	3613	1			T526	4		T518	3		T510	2
all_values[5]	3584	1			T526	3		T518	1		T521	6
all_values[6]	3573	1			T526	2		T518	3		T510	1
all_values[7]	3548	1			T526	1		T518	3		T510	3
all_values[8]	3556	1			T526	3		T518	1		T510	1
all_values[9]	3518	1			T526	2		T518	1		T510	3
all_values[10]	3575	1			T526	2		T518	2		T510	1
all_values[11]	3548	1			T526	1		T518	1		T510	4
all_values[12]	3650	1			T526	1		T518	2		T510	1
all_values[13]	3607	1			T526	4		T518	3		T510	2
all_values[14]	3576	1			T526	3		T510	3		T521	4
all_values[15]	3494	1			T526	2		T518	4		T510	2
all_values[16]	3564	1			T526	2		T518	2		T510	1
all_values[17]	3490	1			T526	1		T518	1		T510	2
all_values[18]	3556	1			T526	2		T518	2		T510	2
all_values[19]	3533	1			T526	1		T518	2		T510	1
all_values[20]	3447	1			T526	2		T518	1		T521	4
all_values[21]	3647	1			T526	4		T518	5		T510	1
all_values[22]	3551	1			T526	5		T510	1		T521	7
all_values[23]	3566	1			T526	3		T518	4		T510	3
all_values[24]	3576	1			T526	2		T518	2		T510	2
all_values[25]	3654	1			T526	3		T518	2		T510	3
all_values[26]	3685	1			T526	4		T518	3		T510	3
all_values[27]	3623	1			T526	2		T518	5		T510	2
all_values[28]	3598	1			T526	6		T518	2		T510	4
all_values[29]	3447	1			T526	1		T510	5		T521	5
all_values[30]	3614	1			T526	4		T510	2		T521	4
all_values[31]	3504	1			T526	1		T518	1		T510	2
all_values[32]	3513	1			T526	2		T518	1		T510	3
all_values[33]	3540	1			T526	2		T518	1		T510	1
all_values[34]	3558	1			T526	4		T518	3		T510	4
all_values[35]	3613	1			T526	4		T518	4		T510	4
all_values[36]	3662	1			T526	4		T518	2		T510	1
all_values[37]	3533	1			T526	1		T518	2		T510	3
all_values[38]	3500	1			T526	1		T510	1		T521	1
all_values[39]	3639	1			T526	3		T518	2		T510	2
all_values[40]	3653	1			T526	2		T510	4		T521	1
all_values[41]	3618	1			T526	3		T518	2		T510	2
all_values[42]	3662	1			T526	4		T518	6		T510	5
all_values[43]	3551	1			T526	2		T518	1		T510	3
all_values[44]	3673	1			T526	4		T518	3		T510	1
all_values[45]	3576	1			T526	2		T518	2		T510	1
all_values[46]	3569	1			T526	1		T518	3		T510	2
all_values[47]	3583	1			T526	1		T518	2		T510	1
all_values[48]	3593	1			T526	1		T518	1		T510	2
all_values[49]	3576	1			T526	1		T518	2		T510	4
all_values[50]	3629	1			T526	5		T518	2		T510	1
all_values[51]	3489	1			T526	8		T518	2		T510	2
all_values[52]	3564	1			T526	2		T518	2		T510	3
all_values[53]	3543	1			T526	2		T518	1		T510	1
all_values[54]	3602	1			T526	5		T518	3		T510	3
all_values[55]	3551	1			T526	3		T518	6		T510	3
all_values[56]	3482	1			T526	2		T518	1		T510	1
all_values[57]	3553	1			T526	1		T518	2		T510	1
all_values[58]	3659	1			T526	5		T518	2		T510	1
all_values[59]	3535	1			T526	4		T518	1		T510	1
all_values[60]	3566	1			T526	2		T518	2		T521	4
all_values[61]	3486	1			T526	5		T518	1		T510	1
all_values[62]	3596	1			T518	1		T510	2		T521	4
all_values[63]	3489	1			T526	2		T518	3		T510	1