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132
133 1/1 assign alert_test = {
Tests: T1 T2 T3
134 reg2hw.alert_test.q &
135 reg2hw.alert_test.qe
136 };
137
138 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
139 prim_alert_sender #(
140 .AsyncOn(AlertAsyncOn[i]),
141 .IsFatal(1'b1)
142 ) u_prim_alert_sender (
143 .clk_i,
144 .rst_ni,
145 .alert_test_i ( alert_test[i] ),
146 .alert_req_i ( alerts[0] ),
147 .alert_ack_o ( ),
148 .alert_state_o ( ),
149 .alert_rx_i ( alert_rx_i[i] ),
150 .alert_tx_o ( alert_tx_o[i] )
151 );
152 end
153
154 /////////////////////////////
155 // Pad attribute registers //
156 /////////////////////////////
157
158 prim_pad_wrapper_pkg::pad_attr_t [NDioPads-1:0] dio_pad_attr_q;
159 prim_pad_wrapper_pkg::pad_attr_t [NMioPads-1:0] mio_pad_attr_q;
160
161 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
162 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
163 1/1 dio_pad_attr_q <= '0;
Tests: T1 T2 T3
164 1/1 mio_pad_attr_q <= '0;
Tests: T1 T2 T3
165 end else begin
166 // dedicated pads
167 1/1 for (int kk = 0; kk < NDioPads; kk++) begin
Tests: T1 T2 T3
168 1/1 if (reg2hw.dio_pad_attr[kk].drive_strength.qe) begin
Tests: T1 T2 T3
169 1/1 dio_pad_attr_q[kk].drive_strength <= reg2hw.dio_pad_attr[kk].drive_strength.q;
Tests: T1 T2 T3
170 end
MISSING_ELSE
171 1/1 if (reg2hw.dio_pad_attr[kk].slew_rate.qe) begin
Tests: T1 T2 T3
172 1/1 dio_pad_attr_q[kk].slew_rate <= reg2hw.dio_pad_attr[kk].slew_rate.q;
Tests: T1 T2 T3
173 end
MISSING_ELSE
174 1/1 if (reg2hw.dio_pad_attr[kk].input_disable.qe) begin
Tests: T1 T2 T3
175 1/1 dio_pad_attr_q[kk].input_disable <= reg2hw.dio_pad_attr[kk].input_disable.q;
Tests: T1 T2 T3
176 end
MISSING_ELSE
177 1/1 if (reg2hw.dio_pad_attr[kk].od_en.qe) begin
Tests: T1 T2 T3
178 1/1 dio_pad_attr_q[kk].od_en <= reg2hw.dio_pad_attr[kk].od_en.q;
Tests: T1 T2 T3
179 end
MISSING_ELSE
180 1/1 if (reg2hw.dio_pad_attr[kk].schmitt_en.qe) begin
Tests: T1 T2 T3
181 1/1 dio_pad_attr_q[kk].schmitt_en <= reg2hw.dio_pad_attr[kk].schmitt_en.q;
Tests: T1 T2 T3
182 end
MISSING_ELSE
183 1/1 if (reg2hw.dio_pad_attr[kk].keeper_en.qe) begin
Tests: T1 T2 T3
184 1/1 dio_pad_attr_q[kk].keep_en <= reg2hw.dio_pad_attr[kk].keeper_en.q;
Tests: T1 T2 T3
185 end
MISSING_ELSE
186 1/1 if (reg2hw.dio_pad_attr[kk].pull_select.qe) begin
Tests: T1 T2 T3
187 1/1 dio_pad_attr_q[kk].pull_select <= reg2hw.dio_pad_attr[kk].pull_select.q;
Tests: T1 T2 T3
188 end
MISSING_ELSE
189 1/1 if (reg2hw.dio_pad_attr[kk].pull_en.qe) begin
Tests: T1 T2 T3
190 1/1 dio_pad_attr_q[kk].pull_en <= reg2hw.dio_pad_attr[kk].pull_en.q;
Tests: T1 T2 T3
191 end
MISSING_ELSE
192 1/1 if (reg2hw.dio_pad_attr[kk].virtual_od_en.qe) begin
Tests: T1 T2 T3
193 1/1 dio_pad_attr_q[kk].virt_od_en <= reg2hw.dio_pad_attr[kk].virtual_od_en.q;
Tests: T1 T2 T3
194 end
MISSING_ELSE
195 1/1 if (reg2hw.dio_pad_attr[kk].invert.qe) begin
Tests: T1 T2 T3
196 1/1 dio_pad_attr_q[kk].invert <= reg2hw.dio_pad_attr[kk].invert.q;
Tests: T1 T2 T3
197 end
MISSING_ELSE
198 end
199 // muxed pads
200 1/1 for (int kk = 0; kk < NMioPads; kk++) begin
Tests: T1 T2 T3
201 1/1 if (reg2hw.mio_pad_attr[kk].drive_strength.qe) begin
Tests: T1 T2 T3
202 1/1 mio_pad_attr_q[kk].drive_strength <= reg2hw.mio_pad_attr[kk].drive_strength.q;
Tests: T1 T2 T3
203 end
MISSING_ELSE
204 1/1 if (reg2hw.mio_pad_attr[kk].slew_rate.qe) begin
Tests: T1 T2 T3
205 1/1 mio_pad_attr_q[kk].slew_rate <= reg2hw.mio_pad_attr[kk].slew_rate.q;
Tests: T1 T2 T3
206 end
MISSING_ELSE
207 1/1 if (reg2hw.mio_pad_attr[kk].input_disable.qe) begin
Tests: T1 T2 T3
208 1/1 mio_pad_attr_q[kk].input_disable <= reg2hw.mio_pad_attr[kk].input_disable.q;
Tests: T1 T2 T3
209 end
MISSING_ELSE
210 1/1 if (reg2hw.mio_pad_attr[kk].od_en.qe) begin
Tests: T1 T2 T3
211 1/1 mio_pad_attr_q[kk].od_en <= reg2hw.mio_pad_attr[kk].od_en.q;
Tests: T1 T2 T3
212 end
MISSING_ELSE
213 1/1 if (reg2hw.mio_pad_attr[kk].schmitt_en.qe) begin
Tests: T1 T2 T3
214 1/1 mio_pad_attr_q[kk].schmitt_en <= reg2hw.mio_pad_attr[kk].schmitt_en.q;
Tests: T1 T2 T3
215 end
MISSING_ELSE
216 1/1 if (reg2hw.mio_pad_attr[kk].keeper_en.qe) begin
Tests: T1 T2 T3
217 1/1 mio_pad_attr_q[kk].keep_en <= reg2hw.mio_pad_attr[kk].keeper_en.q;
Tests: T1 T2 T3
218 end
MISSING_ELSE
219 1/1 if (reg2hw.mio_pad_attr[kk].pull_select.qe) begin
Tests: T1 T2 T3
220 1/1 mio_pad_attr_q[kk].pull_select <= reg2hw.mio_pad_attr[kk].pull_select.q;
Tests: T1 T2 T3
221 end
MISSING_ELSE
222 1/1 if (reg2hw.mio_pad_attr[kk].pull_en.qe) begin
Tests: T1 T2 T3
223 1/1 mio_pad_attr_q[kk].pull_en <= reg2hw.mio_pad_attr[kk].pull_en.q;
Tests: T1 T2 T3
224 end
MISSING_ELSE
225 1/1 if (reg2hw.mio_pad_attr[kk].virtual_od_en.qe) begin
Tests: T1 T2 T3
226 1/1 mio_pad_attr_q[kk].virt_od_en <= reg2hw.mio_pad_attr[kk].virtual_od_en.q;
Tests: T1 T2 T3
227 end
MISSING_ELSE
228 1/1 if (reg2hw.mio_pad_attr[kk].invert.qe) begin
Tests: T1 T2 T3
229 1/1 mio_pad_attr_q[kk].invert <= reg2hw.mio_pad_attr[kk].invert.q;
Tests: T1 T2 T3
230 end
MISSING_ELSE
231 end
232 end
233 end
234
235 ////////////////////////
236 // Connect attributes //
237 ////////////////////////
238
239 pad_attr_t [NDioPads-1:0] dio_attr;
240 for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_attr
241 pad_attr_t warl_mask;
242
243 prim_pad_attr #(
244 .PadType(TargetCfg.dio_pad_type[k])
245 ) u_prim_pad_attr (
246 .attr_warl_o(warl_mask)
247 );
248
249 16/16 assign dio_attr[k] = dio_pad_attr_q[k] & warl_mask;
Tests: T1 T2 T3 | T1 T2 T3 | T25 T10 T11 | T25 T10 T11 | T25 T10 T11 | T25 T10 T11 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T16 T45 T46 | T16 T45 T46 | T20 T21 T22 | T20 T21 T22 | T25 T43 T44 | T25 T43 T44
250 14/16 ==> assign hw2reg.dio_pad_attr[k].drive_strength.d = dio_attr[k].drive_strength;
Tests: T1 T2 T3 | T1 T2 T3 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
251 excluded assign hw2reg.dio_pad_attr[k].slew_rate.d = dio_attr[k].slew_rate;
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
252 16/16 assign hw2reg.dio_pad_attr[k].input_disable.d = dio_attr[k].input_disable;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
253 excluded assign hw2reg.dio_pad_attr[k].od_en.d = dio_attr[k].od_en;
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
254 excluded assign hw2reg.dio_pad_attr[k].schmitt_en.d = dio_attr[k].schmitt_en;
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
255 excluded assign hw2reg.dio_pad_attr[k].keeper_en.d = dio_attr[k].keep_en;
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
256 16/16 assign hw2reg.dio_pad_attr[k].pull_select.d = dio_attr[k].pull_select;
Tests: T20 T21 T22 | T20 T21 T22 | T25 T10 T11 | T25 T10 T11 | T25 T10 T11 | T25 T10 T11 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T25 T43 T44 | T25 T43 T44
257 16/16 assign hw2reg.dio_pad_attr[k].pull_en.d = dio_attr[k].pull_en;
Tests: T20 T21 T22 | T20 T21 T22 | T25 T10 T11 | T25 T10 T11 | T25 T10 T11 | T25 T10 T11 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T22 T47 | T20 T21 T22 | T20 T21 T22 | T25 T43 T44 | T25 T43 T44
258 14/16 ==> assign hw2reg.dio_pad_attr[k].virtual_od_en.d = dio_attr[k].virt_od_en;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T16 T45 T46 | T16 T45 T46 | T20 T21 T22 | T20 T21 T22
259 16/16 assign hw2reg.dio_pad_attr[k].invert.d = dio_attr[k].invert;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T22 T47 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
260 end
261
262 pad_attr_t [NMioPads-1:0] mio_attr;
263 for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_attr
264 pad_attr_t warl_mask;
265
266 prim_pad_attr #(
267 .PadType(TargetCfg.mio_pad_type[k])
268 ) u_prim_pad_attr (
269 .attr_warl_o(warl_mask)
270 );
271
272 47/47 assign mio_attr[k] = mio_pad_attr_q[k] & warl_mask;
Tests: T20 T21 T22 | T20 T21 T22 | T25 T43 T44 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T13 T48 T49 | T20 T21 T22 | T25 T43 T44 | T25 T10 T11 | T20 T21 T22 | T25 T10 T11 | T25 T12 T43 | T25 T12 T43 | T25 T12 T43 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T53 T54 T55 | T53 T54 T55 | T53 T54 T55 | T1 T2 T3 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
273 47/47 assign hw2reg.mio_pad_attr[k].drive_strength.d = mio_attr[k].drive_strength;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
274 excluded assign hw2reg.mio_pad_attr[k].slew_rate.d = mio_attr[k].slew_rate;
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
275 47/47 assign hw2reg.mio_pad_attr[k].input_disable.d = mio_attr[k].input_disable;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
276 excluded assign hw2reg.mio_pad_attr[k].od_en.d = mio_attr[k].od_en;
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
277 excluded assign hw2reg.mio_pad_attr[k].schmitt_en.d = mio_attr[k].schmitt_en;
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
278 excluded assign hw2reg.mio_pad_attr[k].keeper_en.d = mio_attr[k].keep_en;
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
279 47/47 assign hw2reg.mio_pad_attr[k].pull_select.d = mio_attr[k].pull_select;
Tests: T20 T21 T22 | T20 T21 T22 | T25 T43 T44 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T13 T48 T49 | T20 T21 T22 | T25 T43 T44 | T25 T10 T11 | T20 T21 T22 | T25 T10 T11 | T25 T12 T43 | T25 T12 T43 | T25 T12 T43 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T53 T54 T55 | T20 T21 T22 | T20 T21 T22 | T1 T2 T3 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
280 47/47 assign hw2reg.mio_pad_attr[k].pull_en.d = mio_attr[k].pull_en;
Tests: T20 T21 T22 | T20 T21 T22 | T25 T43 T44 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T13 T48 T49 | T20 T21 T22 | T25 T43 T44 | T25 T10 T11 | T20 T21 T22 | T25 T10 T11 | T25 T12 T43 | T25 T12 T43 | T25 T12 T43 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T53 T54 T55 | T53 T54 T55 | T53 T54 T55 | T1 T2 T3 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
281 47/47 assign hw2reg.mio_pad_attr[k].virtual_od_en.d = mio_attr[k].virt_od_en;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
282 47/47 assign hw2reg.mio_pad_attr[k].invert.d = mio_attr[k].invert;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
283 end
284
285
286 //////////////////////////
287 // Strap Sampling Logic //
288 //////////////////////////
289
290 logic strap_en;
291 if (SecVolatileRawUnlockEn) begin : gen_strap_override
292 logic strap_en_override_d, strap_en_override_q;
293 prim_flop_2sync #(
294 .Width(1),
295 .ResetValue(0)
296 ) u_prim_flop_2sync (
297 .clk_i,
298 .rst_ni,
299 .d_i(strap_en_override_i),
300 .q_o(strap_en_override_d)
301 );
302
303 always_ff @(posedge clk_i or negedge rst_ni) begin : p_strap_override_reg
304 if(!rst_ni) begin
305 strap_en_override_q <= 1'b0;
306 end else begin
307 strap_en_override_q <= strap_en_override_d;
308 end
309 end
310
311 // Detect a change from 0 -> 1 on the override signal (it will stay at 1 afterwards).
312 assign strap_en = strap_en_i || (strap_en_override_d && !strap_en_override_q);
313
314 // The strap sampling override shall be set to high exactly once.
315 `ASSUME(LcCtrlStrapSampleOverrideOnce_A,
316 $rose(strap_en_override_i) |-> always strap_en_override_i)
317
318 end else begin : gen_no_strap_override
319 logic unused_strap_en_override;
320 unreachable assign unused_strap_en_override = strap_en_override_i;
321 1/1 assign strap_en = strap_en_i;
Tests: T1 T2 T3
322 end
323
324 // Local versions of the input signals
325 logic [NMioPads-1:0] mio_out, mio_oe, mio_in;
326 logic [NDioPads-1:0] dio_out, dio_oe, dio_in;
327
328 // This module contains the strap sampling and JTAG mux.
329 // Affected inputs are intercepted/tapped before they go to the pinmux
330 // matrix. Likewise, affected outputs are intercepted/tapped after the
331 // retention registers.
332 pinmux_strap_sampling #(
333 .TargetCfg (TargetCfg)
334 ) u_pinmux_strap_sampling (
335 .clk_i,
336 // Inside the pinmux, the strap sampling module is the only module using SYS_RST. The reason for
337 // that is that SYS_RST reset will not be asserted during a NDM reset from the RV_DM and hence
338 // it retains some of the TAP selection state during an active debug session where NDM reset
339 // is triggered. To that end, the strap sampling module latches the lc_hw_debug_en_i signal
340 // whenever strap_en_i is asserted. Note that this does not affect the DFT TAP selection, since
341 // we always consume the live lc_dft_en_i signal.
342 .rst_ni (rst_sys_ni),
343 .scanmode_i,
344 // To padring side
345 .out_padring_o ( {dio_out_o, mio_out_o} ),
346 .oe_padring_o ( {dio_oe_o , mio_oe_o } ),
347 .in_padring_i ( {dio_in_i , mio_in_i } ),
348 .attr_padring_o ( {dio_attr_o, mio_attr_o} ),
349 // To core side
350 .out_core_i ( {dio_out, mio_out} ),
351 .oe_core_i ( {dio_oe, mio_oe} ),
352 .in_core_o ( {dio_in, mio_in} ),
353 .attr_core_i ( {dio_attr, mio_attr} ),
354 // Strap and JTAG signals
355 .strap_en_i ( strap_en ),
356 .lc_dft_en_i,
357 .lc_hw_debug_en_i,
358 .lc_escalate_en_i,
359 .lc_check_byp_en_i,
360 // This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG
361 // signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle.
362 .pinmux_hw_debug_en_o,
363 .dft_strap_test_o,
364 .dft_hold_tap_sel_i,
365 .lc_jtag_o,
366 .lc_jtag_i,
367 .rv_jtag_o,
368 .rv_jtag_i,
369 .dft_jtag_o,
370 .dft_jtag_i
371 );
372
373 ///////////////////////////////////////
374 // USB wake detect module connection //
375 ///////////////////////////////////////
376
377 // Dedicated Peripheral side
378 usbdev_aon_wake u_usbdev_aon_wake (
379 .clk_aon_i,
380 .rst_aon_ni,
381
382 // input signals for resume detection
383 .usb_dp_i(dio_to_periph_o[TargetCfg.usb_dp_idx]),
384 .usb_dn_i(dio_to_periph_o[TargetCfg.usb_dn_idx]),
385 .usb_sense_i(mio_to_periph_o[TargetCfg.usb_sense_idx]),
386 .usbdev_dppullup_en_i(usbdev_dppullup_en_i),
387 .usbdev_dnpullup_en_i(usbdev_dnpullup_en_i),
388
389 // output signals for pullup connectivity
390 .usb_dppullup_en_o(usb_dppullup_en_o),
391 .usb_dnpullup_en_o(usb_dnpullup_en_o),
392
393 // tie this to something from usbdev to indicate its out of reset
394 .suspend_req_aon_i(usbdev_suspend_req_i),
395 .wake_ack_aon_i(usbdev_wake_ack_i),
396
397 // wake/powerup request
398 .wake_req_aon_o(usb_wkup_req_o),
399 .bus_not_idle_aon_o(usbdev_bus_not_idle_o),
400 .bus_reset_aon_o(usbdev_bus_reset_o),
401 .sense_lost_aon_o(usbdev_sense_lost_o),
402 .wake_detect_active_aon_o(usbdev_wake_detect_active_o)
403 );
404
405 /////////////////////////
406 // Retention Registers //
407 /////////////////////////
408
409 logic sleep_en_q, sleep_trig;
410
411 logic [NMioPads-1:0] mio_sleep_trig;
412 logic [NMioPads-1:0] mio_out_retreg_d, mio_oe_retreg_d;
413 logic [NMioPads-1:0] mio_out_retreg_q, mio_oe_retreg_q;
414
415 logic [NDioPads-1:0] dio_sleep_trig;
416 logic [NDioPads-1:0] dio_out_retreg_d, dio_oe_retreg_d;
417 logic [NDioPads-1:0] dio_out_retreg_q, dio_oe_retreg_q;
418
419 // Sleep entry trigger
420 1/1 assign sleep_trig = sleep_en_i & ~sleep_en_q;
Tests: T1 T2 T3
421
422 always_ff @(posedge clk_i or negedge rst_ni) begin : p_sleep
423 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
424 1/1 sleep_en_q <= 1'b0;
Tests: T1 T2 T3
425 1/1 mio_out_retreg_q <= '0;
Tests: T1 T2 T3
426 1/1 mio_oe_retreg_q <= '0;
Tests: T1 T2 T3
427 1/1 dio_out_retreg_q <= '0;
Tests: T1 T2 T3
428 1/1 dio_oe_retreg_q <= '0;
Tests: T1 T2 T3
429 end else begin
430 1/1 sleep_en_q <= sleep_en_i;
Tests: T1 T2 T3
431
432 // MIOs
433 1/1 for (int k = 0; k < NMioPads; k++) begin
Tests: T1 T2 T3
434 1/1 if (mio_sleep_trig[k]) begin
Tests: T1 T2 T3
435 1/1 mio_out_retreg_q[k] <= mio_out_retreg_d[k];
Tests: T3 T5 T6
436 1/1 mio_oe_retreg_q[k] <= mio_oe_retreg_d[k];
Tests: T3 T5 T6
437 end
MISSING_ELSE
438 end
439
440 // DIOs
441 1/1 for (int k = 0; k < NDioPads; k++) begin
Tests: T1 T2 T3
442 1/1 if (dio_sleep_trig[k]) begin
Tests: T1 T2 T3
443 1/1 dio_out_retreg_q[k] <= dio_out_retreg_d[k];
Tests: T3 T6 T19
444 1/1 dio_oe_retreg_q[k] <= dio_oe_retreg_d[k];
Tests: T3 T6 T19
445 end
MISSING_ELSE
446 end
447 end
448 end
449
450 /////////////////////
451 // MIO Input Muxes //
452 /////////////////////
453
454 localparam int AlignedMuxSize = (NMioPads + 2 > NDioPads) ? 2**$clog2(NMioPads + 2) :
455 2**$clog2(NDioPads);
456
457 // stack input and default signals for convenient indexing below possible defaults:
458 // constant 0 or 1. make sure mux is aligned to a power of 2 to avoid Xes.
459 logic [AlignedMuxSize-1:0] mio_mux;
460 1/1 assign mio_mux = AlignedMuxSize'({mio_in, 1'b1, 1'b0});
Tests: T1 T2 T3
461
462 for (genvar k = 0; k < NMioPeriphIn; k++) begin : gen_mio_periph_in
463 // index using configured insel
464 57/57 assign mio_to_periph_o[k] = mio_mux[reg2hw.mio_periph_insel[k].q];
Tests: T6 T26 T38 | T5 T26 T38 | T5 T26 T38 | T5 T26 T38 | T5 T26 T38 | T5 T26 T38 | T5 T26 T38 | T5 T26 T38 | T5 T26 T38 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T26 T38 T39 | T57 T58 T12 | T57 T58 T12 | T59 T12 T60 | T59 T12 T60 | T61 T12 T62 | T61 T12 T62 | T25 T12 T43 | T25 T12 T43 | T25 T12 T43 | T25 T10 T11 | T1 T2 T3 | T1 T2 T3 | T63 T64 T12 | T24 T29 T12 | T13 T48 T65 | T65 T20 T21 | T65 T20 T21 | T65 T20 T21 | T27 T16 T66 | T27 T14 T67 | T27 T14 T66 | T27 T14 T66 | T27 T14 T16 | T27 T16 T66 | T31 T7 T8
465 end
466
467 //////////////////////
468 // MIO Output Muxes //
469 //////////////////////
470
471 // stack output data/enable and default signals for convenient indexing below
472 // possible defaults: 0, 1 or 2 (high-Z). make sure mux is aligned to a power of 2 to avoid Xes.
473 logic [2**$clog2(NMioPeriphOut+3)-1:0] periph_data_mux, periph_oe_mux;
474 1/1 assign periph_data_mux = $bits(periph_data_mux)'({periph_to_mio_i, 1'b0, 1'b1, 1'b0});
Tests: T5 T25 T28
475 1/1 assign periph_oe_mux = $bits(periph_oe_mux)'({periph_to_mio_oe_i, 1'b0, 1'b1, 1'b1});
Tests: T1 T2 T4
476
477 for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_out
478 // Check individual sleep enable status bits
479 47/47 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ?
Tests: T3 T5 T26 | T3 T5 T24 | T3 T5 T26 | T3 T5 T26 | T3 T5 T26 | T3 T5 T26 | T3 T5 T26 | T3 T5 T6 | T3 T26 T57 | T3 T25 T10 | T3 T25 T10 | T3 T10 T11 | T3 T25 T10 | T3 T25 T12 | T1 T2 T3 | T3 T25 T26 | T3 T26 T14 | T3 T26 T12 | T3 T28 T26 | T3 T28 T26 | T3 T28 T26 | T3 T28 T26 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T1 T2 T3 | T3 T19 T36 | T3 T19 T36 | T3 T14 T37 | T3 T19 T36 | T3 T26 T14 | T3 T26 T32 | T3 T26 T32 | T3 T26 T32 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T38 | T3 T26 T14 | T3 T26 T14 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T38 | T3 T26 T12
480 mio_out_retreg_q[k] :
481 periph_data_mux[reg2hw.mio_outsel[k].q];
482
483 47/47 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ?
Tests: T3 T5 T26 | T3 T5 T24 | T3 T5 T26 | T3 T5 T26 | T3 T5 T26 | T3 T5 T26 | T3 T5 T26 | T3 T5 T6 | T3 T26 T57 | T3 T25 T10 | T3 T25 T10 | T3 T10 T11 | T3 T25 T10 | T3 T25 T12 | T1 T2 T3 | T3 T25 T26 | T3 T26 T14 | T3 T26 T12 | T3 T28 T26 | T3 T28 T26 | T3 T28 T26 | T3 T28 T26 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T1 T2 T3 | T3 T19 T36 | T3 T19 T36 | T3 T14 T37 | T3 T19 T36 | T3 T26 T14 | T3 T26 T32 | T3 T26 T32 | T3 T26 T32 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T38 | T3 T26 T14 | T3 T26 T14 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T38 | T3 T26 T12
484 mio_oe_retreg_q[k] :
485 periph_oe_mux[reg2hw.mio_outsel[k].q];
486
487 // latch state when going to sleep
488 // 0: drive low
489 // 1: drive high
490 // 2: high-z
491 // 3: previous value
492 47/47 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 :
Tests: T5 T26 T38 | T3 T5 T24 | T3 T5 T26 | T3 T5 T26 | T5 T26 T38 | T5 T26 T63 | T3 T5 T26 | T3 T5 T6 | T26 T38 T39 | T25 T10 T11 | T3 T25 T12 | T12 T19 T68 | T25 T19 T43 | T3 T12 T36 | T1 T2 T3 | T3 T26 T12 | T3 T26 T14 | T26 T12 T38 | T3 T26 T14 | T3 T26 T32 | T3 T28 T26 | T28 T26 T32 | T3 T36 T20 | T20 T21 T22 | T36 T20 T21 | T3 T19 T36 | T1 T2 T3 | T36 T20 T21 | T3 T36 T20 | T14 T37 T19 | T3 T20 T21 | T3 T26 T14 | T26 T32 T69 | T3 T26 T32 | T3 T26 T32 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T38 | T3 T26 T14 | T26 T14 T37 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T38 | T26 T12 T38
493 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 :
494 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k];
495
496 47/47 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 :
Tests: T5 T26 T38 | T3 T5 T24 | T3 T5 T26 | T3 T5 T26 | T5 T26 T38 | T5 T26 T63 | T3 T5 T26 | T3 T5 T6 | T26 T57 T12 | T25 T12 T43 | T3 T25 T12 | T12 T19 T68 | T25 T12 T19 | T3 T12 T36 | T1 T2 T3 | T3 T26 T12 | T3 T26 T14 | T26 T12 T38 | T3 T28 T26 | T3 T28 T26 | T3 T28 T26 | T28 T26 T61 | T3 T36 T20 | T20 T21 T22 | T36 T20 T21 | T3 T19 T36 | T1 T2 T3 | T36 T20 T21 | T3 T36 T20 | T14 T37 T19 | T3 T20 T21 | T3 T26 T14 | T26 T32 T69 | T3 T26 T32 | T3 T26 T32 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T38 | T3 T26 T14 | T26 T14 T37 | T3 T26 T12 | T3 T26 T12 | T3 T26 T12 | T3 T26 T38 | T26 T12 T38
497 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 :
498 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k];
499
500 // Activate sleep behavior only if it has been enabled
501 47/47 assign mio_sleep_trig[k] = reg2hw.mio_pad_sleep_en[k].q & sleep_trig;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
502 assign hw2reg.mio_pad_sleep_status[k].d = 1'b1;
503 47/47 assign hw2reg.mio_pad_sleep_status[k].de = mio_sleep_trig[k];
Tests: T3 T5 T70 | T3 T5 T70 | T3 T5 T70 | T3 T5 T70 | T3 T5 T70 | T3 T5 T70 | T3 T5 T70 | T3 T5 T6 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36
504 end
505
506 /////////////////////
507 // DIO connections //
508 /////////////////////
509
510 // Inputs are just fed through
511 1/1 assign dio_to_periph_o = dio_in;
Tests: T3 T4 T31
512
513 for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_out
514 // Check individual sleep enable status bits
515 16/16 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ?
Tests: T3 T7 T8 | T3 T7 T8 | T3 T10 T11 | T3 T10 T11 | T3 T10 T11 | T3 T10 T11 | T3 T6 T10 | T3 T6 T13 | T3 T6 T10 | T3 T6 T10 | T3 T14 T15 | T3 T14 T16 | T3 T19 T36 | T3 T19 T36 | T3 T10 T11 | T3 T10 T11
516 dio_out_retreg_q[k] :
517 periph_to_dio_i[k];
518
519 16/16 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ?
Tests: T3 T8 T17 | T3 T8 T17 | T3 T10 T11 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T6 T10 | T3 T6 T13 | T3 T6 T10 | T3 T6 T10 | T3 T4 T19 | T3 T4 T19 | T3 T19 T36 | T3 T19 T36 | T3 T10 T11 | T3 T10 T11
520 dio_oe_retreg_q[k] :
521 periph_to_dio_oe_i[k];
522
523 // latch state when going to sleep
524 // 0: drive low
525 // 1: drive high
526 // 2: high-z
527 // 3: previous value
528 14/16 ==> assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 :
Tests: T3 T7 T8 | T7 T8 T9 | T3 T10 T11 | T3 T10 T11 | T3 T10 T11 | T3 T10 T11 | T3 T6 T10 | T3 T6 T13 | T3 T6 T10 | T6 T10 T11 | T3 T14 T15 | T14 T16 T15 | T3 T10 T11 | T3 T10 T11
529 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 :
530 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k];
531
532 16/16 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 :
Tests: T3 T8 T17 | T8 T17 T18 | T3 T10 T11 | T3 T19 T20 | T3 T36 T20 | T3 T19 T20 | T3 T6 T10 | T3 T6 T13 | T3 T6 T10 | T6 T10 T11 | T3 T4 T19 | T3 T4 T19 | T20 T21 T22 | T20 T21 T22 | T3 T10 T11 | T3 T10 T11
533 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 :
534 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k];
535
536 // Activate sleep behavior only if it has been enabled
537 16/16 assign dio_sleep_trig[k] = reg2hw.dio_pad_sleep_en[k].q & sleep_trig;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
538 assign hw2reg.dio_pad_sleep_status[k].d = 1'b1;
539 16/16 assign hw2reg.dio_pad_sleep_status[k].de = dio_sleep_trig[k];
Tests: T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T6 T19 | T3 T6 T19 | T3 T6 T19 | T3 T6 T19 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36 | T3 T19 T36
540 end
541
542 //////////////////////
543 // Wakeup detectors //
544 //////////////////////
545
546 // Wakeup detectors should not be connected to the scan clock, so filter
547 // those inputs.
548 logic [NDioPads-1:0] dio_wkup_no_scan;
549 for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_wkup_filter
550 if (TargetCfg.dio_scan_role[k] == ScanClock) begin : gen_dio_scan
551 always_comb begin
552 1/1 dio_wkup_no_scan[k] = dio_in_i[k];
Tests: T3 T6 T13
553 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin
Tests: T3 T6 T13
554 0/1 ==> dio_wkup_no_scan[k] = 1'b0;
555 end
MISSING_ELSE
556 end
557 end else begin : gen_no_dio_scan
558 15/15 assign dio_wkup_no_scan[k] = dio_in_i[k];
Tests: T31 T7 T8 | T3 T7 T8 | T3 T25 T10 | T3 T25 T10 | T3 T25 T10 | T3 T25 T10 | T3 T4 T6 | T3 T4 T6 | T3 T4 T6 | T3 T4 T6 | T3 T4 T27 | T3 T4 T27 | T3 T4 T6 | T3 T25 T10 | T3 T6 T25
559 end
560 end
561
562 logic [NMioPads-1:0] mio_wkup_no_scan;
563 for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_wkup_filter
564 if (TargetCfg.mio_scan_role[k] == ScanClock) begin : gen_mio_scan
565 always_comb begin
566 mio_wkup_no_scan[k] = mio_in_i[k];
567 if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin
568 mio_wkup_no_scan[k] = 1'b0;
569 end
570 end
571 end else begin : gen_no_mio_scan
572 47/47 assign mio_wkup_no_scan[k] = mio_in_i[k];
Tests: T3 T5 T24 | T3 T5 T24 | T3 T5 T25 | T3 T5 T26 | T3 T5 T26 | T3 T5 T26 | T3 T5 T26 | T3 T5 T6 | T3 T5 T6 | T3 T25 T33 | T3 T4 T25 | T3 T6 T33 | T3 T25 T10 | T3 T6 T25 | T1 T2 T3 | T3 T25 T26 | T3 T26 T14 | T3 T26 T27 | T3 T28 T26 | T3 T28 T26 | T3 T28 T26 | T3 T28 T26 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T3 T29 T30 | T3 T31 T7 | T1 T2 T3 | T3 T26 T27 | T3 T26 T32 | T3 T26 T32 | T3 T26 T32 | T3 T26 T30 | T3 T26 T30 | T3 T26 T30 | T3 T26 T30 | T3 T26 T30 | T1 T2 T3 | T3 T26 T14 | T1 T2 T3 | T3 T26 T33 | T3 T26 T33 | T3 T26 T33 | T3 T26 T27
573 end
574 end
575
576 // Wakeup detector taps are not affected by JTAG/strap
577 // selection mux. I.e., we always sample the unmuxed inputs
578 // that come directly from the pads.
579 logic [AlignedMuxSize-1:0] dio_wkup_mux;
580 logic [AlignedMuxSize-1:0] mio_wkup_mux;
581 1/1 assign dio_wkup_mux = AlignedMuxSize'(dio_wkup_no_scan);
Tests: T3 T4 T31
582 // The two constants that are concatenated here make sure tha the selection
583 // indices used to index this array are the same as the ones used to index
584 // the mio_mux array above, where positions 0 and 1 select constant 0 and
585 // 1, respectively.
586 1/1 assign mio_wkup_mux = AlignedMuxSize'({mio_wkup_no_scan, 1'b1, 1'b0});
Tests: T1 T2 T3
587
588 logic [NWkupDetect-1:0] aon_wkup_req;
589 for (genvar k = 0; k < NWkupDetect; k++) begin : gen_wkup_detect
590 logic pin_value;
591 8/8 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ?
Tests: T5 T31 T6 | T31 T7 T8 | T31 T7 T8 | T31 T7 T8 | T31 T7 T8 | T31 T7 T8 | T31 T7 T8 | T4 T31 T7
592 dio_wkup_mux[reg2hw.wkup_detector_padsel[k]] :
593 mio_wkup_mux[reg2hw.wkup_detector_padsel[k]];
594
595 // This module runs on the AON clock entirely
596 pinmux_wkup u_pinmux_wkup (
597 .clk_i (clk_aon_i ),
598 .rst_ni (rst_aon_ni ),
599 // config signals have already been synced to the AON domain inside the CSR node.
600 .wkup_en_i ( reg2hw.wkup_detector_en[k].q ),
601 .filter_en_i ( reg2hw.wkup_detector[k].filter.q ),
602 .wkup_mode_i ( wkup_mode_e'(reg2hw.wkup_detector[k].mode.q) ),
603 .wkup_cnt_th_i ( reg2hw.wkup_detector_cnt_th[k].q ),
604 .pin_value_i ( pin_value ),
605 // wakeup request pulse on clk_aon, will be synced back to the bus domain insie the CSR node.
606 .aon_wkup_pulse_o ( hw2reg.wkup_cause[k].de )
607 );
608
609 assign hw2reg.wkup_cause[k].d = 1'b1;
610
611 // This is the latched wakeup request, hence this request signal is level encoded.
612 4/8 ==> assign aon_wkup_req[k] = reg2hw.wkup_cause[k].q;
Tests: T5 T6 T70 | T23 T71 | T72 T73 T74 | T4
613 end
614
615 // OR' together all wakeup requests
616 1/1 assign pin_wkup_req_o = |aon_wkup_req;
Tests: T4 T5 T6