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 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T75,T219,T282
1	0	1	Covered	T41,T80,T82
1	1	0	Covered	T415,T528,T543
1	1	1	Covered	T41,T80,T82

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T41,T80,T82
1	0	1	Covered	T41,T80,T82
1	1	0	Covered	T270,T524,T419
1	1	1	Covered	T282,T69,T439

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T41,T80,T82
1	0	1	Covered	T80,T115,T299
1	1	0	Covered	T94,T419,T451
1	1	1	Covered	T168,T526,T524

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T168,T441,T524
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T168,T441,T526
1	1	0	Covered	T606
1	1	1	Covered	T3,T4,T5

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T168,T526,T419
1	1	0	Covered	T571
1	1	1	Covered	T2,T3,T4