Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T130 T131 T324 | T130 T131 T324 | T130 T131 T324 | T130 T131 T324 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T130 T131 T324 | T132 T324 T119 | T132 T324 T119 | T132 T324 T119 | T132 T324 T119 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T132 T324 T119 | T63 T324 T64 | T63 T324 T64 | T63 T324 T64 | T63 T324 T64 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T63 T324 T64 | T24 T29 T324 | T24 T29 T324 | T24 T29 T324 | T24 T29 T324 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T24 T29 T324 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T10 T127 T221 | T127 T186 T187 | T127 T186 T187 | T127 T186 T187 | T127 T186 T187 | T13 T127 T48 | T127 T186 T187 | T127 T186 T187 | T57 T327 T137 | T57 T327 T137 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T57 T58 T327 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T59 T327 T60 | T59 T327 T60 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T59 T327 T60 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T61 T327 T62 | T61 T327 T62 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T61 T327 T62 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T127 T186 T187 | T28 T127 T134 | T127 T186 T187 | T127 T186 T187 | T127 T186 T187 | T41 T82 T232 | T188 T330 T189 | T80 T327 T331 | T189 T327 T105 | T127 T186 T187 | T127 T186 T187 | T127 T186 T187 | T127 T186 T187 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T4 T5 T6 | T66 T324 T230 | T138 T327 T139 | T332 T255 T333 | T254 T255 T189 | T176 T127 T33 | T127 T186 T187 | T122 T145 T334 | T122 T145 T334 | T145 T334 T327 | T145 T334 T327 | T122 T145 T334 | T327 T328 T329 | T280 T335 T327 | T327 T328 T329 | T327 T328 T329 | T127 T186 T187 | T127 T186 T187 | T127 T186 T187 | T160 T127 T180 | T127 T186 T187 | T327 T328 T329 | T336 T327 T337 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T336 T327 T337 | T327 T328 T329 | T336 T327 T337 | T327 T328 T329
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T271 T33 T272 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T13 T26 T10 | T13 T271 T127 | T13 T271 T127 | T13 T10 T11 | T13 T10 T11 | T13 T271 T127 | T271 T127 T324 | T271 T127 T324 | T57 T271 T127 | T57 T271 T127 | T271 T127 T324 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T271 T127 T324 | T57 T58 T271 | T58 T271 T127 | T271 T127 T324 | T58 T271 T127 | T58 T271 T127 | T58 T271 T127 | T59 T271 T127 | T59 T271 T127 | T271 T127 T324 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T271 T127 T324 | T59 T271 T127 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T61 T271 T127 | T61 T271 T127 | T271 T127 T324 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T271 T127 T324 | T61 T271 T127 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T28 T271 T127 | T28 T271 T127 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T41 T80 T82 | T41 T80 T82 | T41 T80 T82 | T41 T80 T82 | T10 T11 T271 | T10 T11 T271 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T4 T5 T6 | T66 T271 T127 | T138 T271 T127 | T41 T80 T82 | T41 T254 T80 | T176 T271 T127 | T271 T127 T324 | T122 T145 T334 | T122 T145 T334 | T122 T145 T334 | T122 T145 T334 | T122 T145 T334 | T271 T127 T324 | T280 T335 T271 | T280 T335 T271 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T160 T271 T127 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T4 T5 T6 | T28 T41 T24 | T24 T26 T29 | T28 T41 T13 | T4 T5 T6 | T24 T29 T63 | T24 T26 T29 | T13 T26 T10 | T28 T41 T59 | T4 T5 T6 | T122 T145 T334 | T130 T132 T131 | T24 T29 T63 | T24 T26 T29 | T26 T271 T127 | T13 T26 T10 | T57 T58 T59 | T59 T61 T271 | T28 T41 T82 | T41 T80 T82 | T4 T5 T6 | T122 T145 T334 | T271 T127 T324 | T130 T131 T271 | T130 T132 T131 | T63 T132 T271 | T24 T29 T63 | T24 T26 T29 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T10 T271 | T13 T10 T57 | T57 T58 T271 | T59 T271 T127 | T59 T271 T127 | T61 T271 T127 | T61 T271 T127 | T28 T41 T82 | T41 T10 T80 | T271 T127 T324 | T271 T127 T324 | T4 T5 T6 | T122 T145 T334 | T160 T271 T127 | T271 T127 T324 | T130 T131 T271 | T130 T131 T271 | T130 T132 T131 | T132 T271 T127 | T63 T132 T271 | T63 T271 T127 | T63 T271 T127 | T24 T29 T271 | T24 T29 T271 | T24 T26 T29 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T13 T26 T10 | T13 T10 T11 | T57 T271 T127 | T57 T271 T127 | T57 T58 T271 | T58 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T28 T271 T127 | T41 T82 T232 | T41 T80 T82 | T10 T11 T271 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T4 T5 T6 | T41 T254 T80 | T122 T145 T334 | T122 T145 T334 | T271 T127 T324 | T160 T271 T127 | T271 T127 T324 | T271 T127 T324 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T63 T132 T271 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T26 T29 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T13 T26 T10 | T13 T271 T127 | T13 T10 T11 | T13 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T58 T271 | T58 T271 T127 | T58 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T271 T127 T324 | T271 T127 T324 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T271 T127 T324 | T271 T127 T324 | T28 T271 T127 | T271 T127 T324 | T41 T80 T82 | T41 T80 T82 | T41 T10 T80 | T10 T11 T271 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T4 T5 T6 | T66 T138 T271 | T41 T254 T80 | T176 T271 T127 | T122 T145 T334 | T122 T145 T334 | T122 T145 T334 | T280 T335 T271 | T271 T127 T324 | T271 T127 T324 | T160 T271 T127 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T4 T5 T6 | T28 T41 T24 | T4 T5 T6 | T24 T26 T29 | T28 T41 T13 | T4 T5 T6 | T24 T29 T63 | T24 T26 T29 | T13 T26 T10 | T28 T41 T59 | T4 T5 T6 | T122 T145 T334 | T130 T132 T131 | T24 T29 T63 | T24 T26 T29 | T26 T327 T39 | T13 T26 T10 | T57 T58 T59 | T59 T61 T327 | T28 T41 T82 | T80 T188 T330 | T4 T5 T6 | T122 T145 T334 | T336 T327 T337 | T130 T131 T324 | T130 T132 T131 | T63 T132 T324 | T24 T29 T63 | T24 T26 T29 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T10 T127 | T13 T57 T127 | T57 T58 T327 | T59 T327 T60 | T59 T327 T60 | T61 T327 T62 | T61 T327 T62 | T28 T41 T82 | T80 T188 T330 | T324 T325 T326 | T324 T325 T326 | T4 T5 T6 | T122 T145 T334 | T160 T127 T336 | T336 T327 T337 | T336 T327 T337 | T130 T131 T324 | T130 T131 T324 | T130 T132 T131 | T132 T324 T119 | T63 T132 T324 | T63 T324 T64 | T63 T324 T64 | T24 T29 T324 | T324 T325 T326 | T24 T26 T29 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T10 T127 | T13 T127 T48 | T57 T127 T327 | T327 T328 T329 | T57 T58 T327 | T327 T328 T329 | T59 T327 T60 | T327 T328 T329 | T59 T327 T60 | T61 T327 T62 | T61 T327 T62 | T327 T328 T329 | T61 T327 T62 | T28 T127 T327 | T41 T82 T232 | T80 T188 T330 | T127 T324 T186 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T4 T5 T6 | T254 T332 T255 | T122 T145 T334 | T122 T145 T334 | T127 T327 T186 | T160 T127 T336 | T327 T328 T329 | T336 T327 T337 | T336 T327 T337 | T130 T131 T324 | T130 T131 T324 | T130 T131 T324 | T324 T325 T326 | T130 T131 T324 | T132 T324 T119 | T132 T324 T119 | T324 T325 T326 | T324 T325 T326 | T63 T132 T324 | T63 T324 T64 | T63 T324 T64 | T324 T325 T326 | T63 T324 T64 | T24 T29 T324 | T24 T29 T324 | T324 T325 T326 | T324 T325 T326 | T24 T26 T29 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T10 T127 | T127 T186 T187 | T127 T186 T187 | T13 T127 T48 | T57 T127 T327 | T57 T327 T137 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T57 T58 T327 | T327 T328 T329 | T327 T328 T329 | T59 T327 T60 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T59 T327 T60 | T327 T328 T329 | T327 T328 T329 | T61 T327 T62 | T61 T327 T62 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T61 T327 T62 | T327 T328 T329 | T327 T328 T329 | T28 T127 T134 | T127 T186 T187 | T41 T82 T232 | T80 T188 T330 | T189 T127 T327 | T127 T186 T187 | T127 T324 T186 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T4 T5 T6 | T66 T138 T324 | T254 T332 T255 | T176 T127 T33 | T122 T145 T334 | T145 T334 T327 | T122 T145 T334 | T280 T335 T327 | T127 T327 T186 | T127 T186 T187 | T160 T127 T180 | T336 T327 T337 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T336 T327 T337 | T336 T327 T337
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T4 T5 T6 | T28 T41 T24 | T4 T5 T6 | T24 T26 T29 | T28 T41 T13 | T4 T5 T6 | T24 T29 T63 | T24 T26 T29 | T13 T26 T10 | T28 T41 T59 | T4 T5 T6 | T122 T145 T334 | T130 T132 T131 | T24 T29 T63 | T24 T26 T29 | T26 T327 T39 | T13 T26 T10 | T57 T58 T59 | T59 T61 T327 | T28 T41 T82 | T80 T189 T127 | T4 T5 T6 | T122 T145 T334 | T336 T327 T337 | T130 T131 T324 | T130 T132 T131 | T63 T132 T324 | T24 T29 T63 | T24 T26 T29 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T10 T127 | T13 T57 T127 | T57 T58 T327 | T59 T327 T60 | T59 T327 T60 | T61 T327 T62 | T61 T327 T62 | T28 T41 T82 | T80 T189 T127 | T324 T325 T326 | T324 T325 T326 | T4 T5 T6 | T122 T145 T334 | T160 T127 T336 | T336 T327 T337 | T327 T328 T329 | T130 T131 T324 | T324 T325 T326 | T130 T132 T131 | T132 T324 T119 | T63 T132 T324 | T63 T324 T64 | T63 T324 T64 | T24 T29 T324 | T324 T325 T326 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T10 T127 T221 | T13 T127 T48 | T57 T327 T137 | T327 T328 T329 | T57 T58 T327 | T327 T328 T329 | T59 T327 T60 | T327 T328 T329 | T59 T327 T60 | T61 T327 T62 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T28 T127 T327 | T41 T82 T232 | T80 T189 T127 | T127 T324 T186 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T4 T5 T6 | T254 T255 T176 | T122 T145 T334 | T280 T335 T327 | T127 T186 T187 | T127 T336 T327 | T327 T328 T329 | T336 T327 T337 | T327 T328 T329 | T130 T131 T324 | T130 T131 T324 | T324 T325 T326 | T324 T325 T326 | T130 T131 T324 | T132 T324 T119 | T132 T324 T119 | T324 T325 T326 | T324 T325 T326 | T63 T324 T64 | T63 T324 T64 | T324 T325 T326 | T324 T325 T326 | T63 T324 T64 | T24 T29 T324 | T24 T29 T324 | T324 T325 T326 | T324 T325 T326 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T26 T327 T39 | T10 T127 T221 | T127 T186 T187 | T127 T186 T187 | T127 T186 T187 | T57 T327 T137 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T59 T327 T60 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T59 T327 T60 | T327 T328 T329 | T327 T328 T329 | T61 T327 T62 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T28 T127 T134 | T127 T186 T187 | T41 T82 T232 | T80 T327 T331 | T127 T186 T187 | T127 T186 T187 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T324 T325 T326 | T4 T5 T6 | T138 T327 T139 | T254 T255 T189 | T127 T186 T187 | T122 T145 T334 | T145 T334 T327 | T327 T328 T329 | T327 T328 T329 | T127 T186 T187 | T127 T186 T187 | T127 T186 T187 | T336 T327 T337 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329 | T327 T328 T329
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T4 T5 T6 | T28 T41 T24 | T4 T5 T6 | T24 T26 T29 | T28 T41 T13 | T4 T5 T6 | T24 T29 T63 | T24 T26 T29 | T13 T26 T10 | T28 T41 T59 | T4 T5 T6 | T122 T145 T334 | T130 T132 T131 | T24 T29 T63 | T24 T26 T29 | T26 T271 T127 | T13 T26 T10 | T57 T58 T59 | T59 T61 T271 | T28 T41 T82 | T41 T80 T82 | T4 T5 T6 | T122 T145 T334 | T271 T127 T324 | T130 T131 T271 | T130 T132 T131 | T63 T132 T271 | T24 T29 T63 | T24 T26 T29 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T10 T271 | T13 T10 T57 | T57 T58 T271 | T59 T271 T127 | T59 T271 T127 | T61 T271 T127 | T61 T271 T127 | T28 T41 T82 | T41 T10 T80 | T271 T127 T324 | T271 T127 T324 | T4 T5 T6 | T122 T145 T334 | T160 T271 T127 | T271 T127 T324 | T271 T127 T324 | T130 T131 T271 | T130 T131 T271 | T130 T132 T131 | T132 T271 T127 | T63 T132 T271 | T63 T271 T127 | T63 T271 T127 | T24 T29 T271 | T24 T29 T271 | T24 T26 T29 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T13 T26 T10 | T13 T10 T11 | T57 T271 T127 | T57 T271 T127 | T57 T58 T271 | T58 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T28 T271 T127 | T41 T82 T232 | T41 T80 T82 | T10 T11 T271 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T4 T5 T6 | T41 T254 T80 | T122 T145 T334 | T122 T145 T334 | T271 T127 T324 | T160 T271 T127 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T130 T131 T271 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T132 T271 T127 | T63 T132 T271 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T63 T271 T127 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T29 T271 | T24 T26 T29 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T26 T271 T127 | T13 T26 T10 | T13 T271 T127 | T13 T10 T11 | T13 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T271 T127 | T57 T58 T271 | T58 T271 T127 | T58 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T59 T271 T127 | T271 T127 T324 | T271 T127 T324 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T61 T271 T127 | T271 T127 T324 | T271 T127 T324 | T28 T271 T127 | T271 T127 T324 | T41 T80 T82 | T41 T80 T82 | T41 T10 T80 | T10 T11 T271 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T4 T5 T6 | T66 T138 T271 | T41 T254 T80 | T176 T271 T127 | T122 T145 T334 | T122 T145 T334 | T122 T145 T334 | T280 T335 T271 | T271 T127 T324 | T271 T127 T324 | T160 T271 T127 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324 | T271 T127 T324
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T4 T5 T6
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T4 T5 T6
101 1/1 assign max_value_o = max_tree[0];
Tests: T4 T5 T6
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);