Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135496	1			T92	38		T93	10		T94	12
values[2]	9801	1			T268	3		T433	174		T438	1
values[3]	3377	1			T433	104		T414	9		T597	54
values[4]	1872	1			T433	51		T414	10		T597	5
values[5]	1194	1			T433	17		T414	8		T595	3
values[6]	884	1			T433	3		T414	8		T595	2
values[7]	640	1			T433	2		T414	2		T595	2
values[8]	503	1			T414	4		T503	10		T609	10
values[9]	385	1			T414	13		T503	11		T609	4
values[10]	364	1			T414	13		T503	3		T609	9
values[11]	315	1			T414	4		T609	15		T622	3
values[12]	280	1			T414	2		T609	3		T622	8
values[13]	291	1			T414	7		T609	3		T622	6
values[14]	229	1			T414	3		T609	6		T622	13
values[15]	291	1			T414	11		T609	15		T622	23
values[16]	292	1			T414	7		T609	6		T622	10
values[17]	213	1			T414	5		T609	6		T622	5
values[18]	242	1			T414	6		T609	17		T622	5
values[19]	240	1			T414	11		T609	5		T622	8
values[20]	209	1			T414	3		T609	4		T622	9
values[21]	238	1			T414	6		T609	6		T622	11
values[22]	184	1			T414	4		T609	5		T622	4
values[23]	234	1			T414	3		T609	7		T622	7
values[24]	247	1			T414	5		T609	3		T622	9
values[25]	262	1			T414	8		T609	7		T622	11
values[26]	219	1			T414	3		T609	7		T622	11
values[27]	294	1			T414	3		T609	16		T622	5
values[28]	190	1			T414	8		T609	6		T622	3
values[29]	265	1			T414	10		T609	8		T622	5
values[30]	188	1			T414	14		T609	3		T622	2
values[31]	243	1			T414	7		T609	23		T622	7
values[32]	212	1			T414	3		T609	5		T622	9
values[33]	229	1			T414	4		T609	7		T622	8
values[34]	241	1			T414	4		T609	8		T622	6
values[35]	206	1			T414	15		T609	6		T622	6
values[36]	253	1			T414	24		T609	4		T622	7
values[37]	200	1			T414	6		T609	4		T622	6
values[38]	232	1			T414	4		T609	7		T622	5
values[39]	198	1			T414	8		T609	6		T622	6
values[40]	212	1			T414	15		T609	8		T622	3
values[41]	239	1			T414	4		T609	5		T622	8
values[42]	227	1			T414	13		T609	11		T622	14
values[43]	170	1			T414	5		T609	5		T622	4
values[44]	206	1			T414	3		T609	5		T622	9
values[45]	184	1			T414	11		T609	4		T622	7
values[46]	202	1			T414	7		T609	5		T622	9
values[47]	222	1			T414	14		T609	18		T622	39
values[48]	192	1			T414	16		T609	3		T622	9
values[49]	176	1			T414	8		T609	3		T622	3
values[50]	196	1			T414	4		T609	3		T622	11
values[51]	220	1			T414	4		T609	28		T622	7
values[52]	193	1			T414	15		T609	5		T622	8
values[53]	183	1			T414	8		T622	10		T797	4
values[54]	183	1			T414	4		T622	6		T797	7
values[55]	171	1			T414	4		T622	4		T797	5
values[56]	171	1			T414	5		T622	6		T797	4
values[57]	184	1			T414	10		T622	5		T797	3
values[58]	155	1			T414	3		T622	3		T797	4
values[59]	145	1			T414	15		T622	5		T797	5
values[60]	123	1			T414	10		T622	3		T797	5
values[61]	142	1			T414	25		T622	5		T797	5
values[62]	138	1			T414	16		T622	7		T797	3
values[63]	112	1			T414	4		T622	7		T797	2
values[64]	111	1			T414	3		T622	9		T797	6
values[65]	107	1			T414	9		T622	9		T797	6
values[66]	110	1			T622	7		T797	4		T471	9
values[67]	79	1			T622	6		T471	3		T456	4
values[68]	71	1			T622	8		T471	5		T456	5
values[69]	94	1			T622	5		T471	17		T456	10
values[70]	74	1			T622	7		T471	7		T456	5
values[71]	89	1			T622	9		T456	7		T494	1
values[72]	76	1			T622	5		T456	11		T494	1
values[73]	66	1			T622	10		T456	3		T494	1
values[74]	77	1			T622	11		T456	4		T494	1
values[75]	64	1			T456	9		T494	1		T807	1
values[76]	53	1			T456	7		T494	1		T807	1
values[77]	58	1			T456	3		T494	1		T807	1
values[78]	60	1			T456	4		T494	1		T807	2
values[79]	87	1			T456	9		T494	1		T807	1
values[80]	70	1			T456	9		T494	1		T807	1
values[81]	66	1			T456	3		T494	1		T807	1
values[82]	50	1			T456	5		T494	1		T807	1
values[83]	45	1			T456	2		T494	1		T807	1
values[84]	49	1			T456	1		T494	1		T807	1
values[85]	42	1			T494	1		T807	1		T842	1
values[86]	61	1			T494	1		T807	1		T842	1
values[87]	66	1			T494	1		T807	1		T842	1
values[88]	45	1			T494	1		T807	1		T842	1
values[89]	53	1			T494	1		T807	1		T842	1
values[90]	69	1			T494	1		T807	1		T842	1
values[91]	55	1			T494	1		T807	1		T842	1
values[92]	72	1			T494	1		T807	2		T842	1
values[93]	77	1			T494	1		T807	2		T842	1
values[94]	70	1			T494	1		T807	1		T842	1
values[95]	50	1			T494	1		T807	4		T842	1
values[96]	51	1			T494	1		T807	4		T842	1
values[97]	61	1			T494	1		T807	6		T842	1
values[98]	54	1			T494	1		T807	1		T842	1
values[99]	50	1			T494	1		T807	1		T842	1
values[100]	58	1			T494	1		T807	4		T842	1
values[101]	69	1			T494	1		T807	5		T842	1
values[102]	79	1			T494	1		T807	10		T842	1
values[103]	76	1			T494	1		T807	2		T842	1
values[104]	58	1			T494	1		T807	2		T842	1
values[105]	59	1			T494	1		T807	1		T842	1
values[106]	73	1			T494	1		T807	6		T842	1
values[107]	56	1			T494	1		T807	1		T842	1
values[108]	68	1			T494	1		T807	2		T842	1
values[109]	51	1			T494	1		T807	1		T842	1
values[110]	52	1			T494	1		T807	1		T842	1
values[111]	56	1			T494	1		T807	3		T842	1
values[112]	43	1			T494	1		T807	1		T842	1
values[113]	50	1			T494	1		T807	2		T842	1
values[114]	55	1			T494	5		T807	1		T842	1
values[115]	56	1			T494	1		T807	4		T842	4
values[116]	44	1			T494	1		T807	2		T842	1
values[117]	51	1			T494	3		T807	2		T842	2
values[118]	62	1			T494	4		T807	5		T842	1
values[119]	36	1			T494	1		T807	1		T842	2
values[120]	30	1			T494	1		T807	1		T842	3
values[121]	47	1			T494	1		T807	3		T842	7
values[122]	40	1			T494	1		T807	4		T842	1
values[123]	32	1			T494	2		T807	1		T842	1
values[124]	50	1			T494	6		T807	1		T842	2
values[125]	44	1			T494	1		T807	1		T842	1
values[126]	53	1			T494	4		T807	1		T842	1
values[127]	652	1			T494	27		T807	35		T842	41
values[128]	6324	1			T494	259		T807	301		T842	364