Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.45 93.66 95.48 94.43 97.53 99.54


Total tests in report: 2931
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.03 40.03 45.16 45.16 46.68 46.68 27.53 27.53 63.14 63.14 57.52 57.52 0.14 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.28314135
47.75 7.72 49.36 4.20 56.04 9.35 27.75 0.22 69.60 6.46 82.69 25.17 1.07 0.93 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.855993093
53.07 5.32 60.58 11.22 63.67 7.63 30.83 3.08 79.60 10.00 82.69 0.00 1.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.734591500
57.41 4.33 70.20 9.62 64.87 1.21 38.54 7.72 79.79 0.19 82.69 0.00 8.34 7.27 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.315932432
61.54 4.13 70.20 0.00 64.87 0.00 38.54 0.00 79.79 0.00 82.69 0.00 33.15 24.80 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.669001299
65.15 3.61 76.50 6.30 68.69 3.81 46.08 7.53 81.97 2.18 84.27 1.57 33.39 0.25 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2530987797
68.14 2.99 81.43 4.93 72.34 3.65 49.56 3.48 83.64 1.67 88.46 4.20 33.39 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3472176484
70.84 2.70 81.53 0.10 75.08 2.74 49.56 0.00 83.79 0.15 88.46 0.00 46.60 13.21 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.2493249983
73.11 2.28 82.94 1.41 77.67 2.59 55.00 5.44 85.58 1.79 88.64 0.17 48.85 2.26 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.378589710
75.27 2.15 82.94 0.00 77.67 0.00 67.91 12.92 85.58 0.00 88.64 0.00 48.85 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3020989629
77.17 1.90 82.94 0.00 77.67 0.00 67.91 0.00 85.58 0.00 88.64 0.00 60.26 11.41 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3399451232
78.73 1.56 82.94 0.00 77.68 0.01 67.91 0.00 85.58 0.00 88.64 0.00 69.63 9.36 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.969625553
80.11 1.38 83.07 0.13 77.78 0.10 75.64 7.72 85.76 0.18 88.81 0.17 69.63 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.964619104
81.44 1.32 85.42 2.35 79.70 1.92 76.62 0.98 88.45 2.69 88.81 0.00 69.63 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3846287114
82.71 1.27 85.42 0.00 79.70 0.00 76.62 0.00 88.45 0.00 88.81 0.00 77.25 7.63 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1288717716
83.90 1.19 87.06 1.64 80.79 1.09 77.88 1.26 89.50 1.05 90.91 2.10 77.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.4111240438
84.93 1.03 88.65 1.59 81.71 0.92 79.85 1.98 90.17 0.67 91.96 1.05 77.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.1533306715
85.80 0.86 89.42 0.77 81.95 0.24 79.86 0.01 90.48 0.31 95.80 3.85 77.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1424478958
86.60 0.80 89.42 0.00 81.95 0.00 79.86 0.00 90.48 0.00 95.80 0.00 82.08 4.83 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4162341115
87.24 0.64 89.54 0.11 82.00 0.05 83.54 3.67 90.51 0.02 95.80 0.00 82.08 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.3688169067
87.81 0.57 90.28 0.74 83.85 1.85 83.85 0.31 91.00 0.49 95.80 0.00 82.11 0.02 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.3668077134
88.36 0.55 90.28 0.01 83.93 0.08 84.57 0.72 91.03 0.03 95.80 0.00 84.55 2.44 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.3530112270
88.91 0.55 90.28 0.00 83.93 0.00 84.57 0.00 91.03 0.00 95.80 0.00 87.83 3.28 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3347176087
89.41 0.50 90.29 0.01 86.50 2.57 84.57 0.00 91.03 0.00 95.80 0.00 88.24 0.41 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.2758257440
89.89 0.48 91.20 0.91 87.39 0.89 84.94 0.37 91.75 0.71 95.80 0.00 88.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3462323552
90.30 0.41 91.57 0.37 87.85 0.47 86.35 1.40 91.96 0.21 95.80 0.00 88.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.3817883691
90.70 0.40 91.57 0.00 87.86 0.01 86.35 0.00 91.96 0.00 95.80 0.00 90.66 2.42 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.352606025
91.08 0.38 91.57 0.00 87.90 0.04 86.35 0.00 91.98 0.02 95.80 0.00 92.87 2.21 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.813921597
91.42 0.34 92.28 0.70 88.18 0.28 87.02 0.67 92.14 0.16 95.98 0.17 92.92 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3246255013
91.72 0.30 92.83 0.56 88.68 0.49 87.28 0.26 92.62 0.49 95.98 0.00 92.92 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.865997936
92.01 0.29 92.83 0.00 88.68 0.00 89.05 1.77 92.62 0.00 95.98 0.00 92.92 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3497120571
92.25 0.23 92.83 0.00 88.74 0.07 89.05 0.00 92.62 0.00 95.98 0.00 94.25 1.34 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.1936467664
92.48 0.23 93.38 0.55 88.95 0.20 89.50 0.45 92.81 0.19 95.98 0.00 94.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2945445753
92.70 0.22 93.38 0.00 88.97 0.02 89.50 0.00 92.81 0.00 95.98 0.00 95.58 1.33 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.373252762
92.93 0.22 93.38 0.00 88.97 0.00 90.84 1.34 92.81 0.00 95.98 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.4244168372
93.08 0.16 93.38 0.00 89.03 0.06 90.84 0.00 92.81 0.00 95.98 0.00 96.45 0.87 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1800019937
93.23 0.15 93.49 0.11 89.80 0.76 90.86 0.01 92.81 0.00 95.98 0.00 96.45 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2374532501
93.37 0.14 93.54 0.06 90.16 0.36 90.88 0.02 93.21 0.40 95.98 0.00 96.45 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2168858450
93.50 0.13 93.83 0.29 90.27 0.11 91.26 0.38 93.24 0.03 95.98 0.00 96.45 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1204345038
93.64 0.13 93.83 0.00 90.27 0.01 92.05 0.79 93.24 0.00 95.98 0.00 96.45 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4194893922
93.76 0.12 93.98 0.15 90.44 0.17 92.18 0.13 93.51 0.27 95.98 0.00 96.45 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.1603618998
93.87 0.12 93.99 0.01 90.47 0.02 92.19 0.01 93.52 0.01 95.98 0.00 97.11 0.66 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3960596190
93.98 0.11 94.01 0.02 90.65 0.18 92.23 0.05 93.57 0.05 96.33 0.35 97.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3428786885
94.07 0.09 94.01 0.00 90.65 0.00 92.79 0.56 93.57 0.00 96.33 0.00 97.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1926892654
94.16 0.09 94.01 0.00 91.17 0.53 92.79 0.00 93.57 0.00 96.33 0.00 97.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.3310049566
94.25 0.08 94.13 0.12 91.27 0.10 92.99 0.21 93.65 0.08 96.33 0.00 97.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3047001165
94.33 0.08 94.28 0.15 91.39 0.12 93.09 0.10 93.77 0.12 96.33 0.00 97.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2510332167
94.40 0.07 94.28 0.00 91.49 0.10 93.09 0.00 93.78 0.02 96.33 0.00 97.44 0.33 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1840039775
94.47 0.07 94.31 0.03 91.51 0.02 93.26 0.16 93.82 0.03 96.50 0.17 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2435237934
94.54 0.07 94.33 0.01 91.58 0.07 93.49 0.24 93.90 0.08 96.50 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1372352783
94.60 0.06 94.33 0.01 91.83 0.25 93.52 0.02 93.91 0.02 96.50 0.00 97.53 0.09 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2289798422
94.67 0.06 94.33 0.01 92.00 0.17 93.53 0.01 94.11 0.19 96.50 0.00 97.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1153690186
94.73 0.06 94.34 0.01 92.05 0.05 93.62 0.09 94.13 0.02 96.68 0.17 97.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.678488786
94.78 0.05 94.34 0.00 92.05 0.00 93.95 0.33 94.13 0.00 96.68 0.00 97.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1362826227
94.82 0.04 94.34 0.00 92.08 0.02 93.95 0.00 94.13 0.00 96.68 0.00 97.77 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.748327511
94.86 0.04 94.34 0.00 92.08 0.01 94.01 0.06 94.13 0.00 96.85 0.17 97.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1169875682
94.90 0.04 94.35 0.01 92.09 0.01 94.01 0.00 94.15 0.02 97.03 0.17 97.78 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.695789468
94.94 0.04 94.35 0.00 92.12 0.03 94.20 0.19 94.15 0.00 97.03 0.00 97.78 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.3806813832
94.98 0.04 94.38 0.03 92.22 0.10 94.30 0.10 94.15 0.00 97.03 0.00 97.78 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2271298776
95.01 0.04 94.38 0.01 92.23 0.01 94.31 0.01 94.16 0.01 97.20 0.17 97.79 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3760112941
95.05 0.04 94.39 0.01 92.24 0.01 94.31 0.01 94.17 0.01 97.38 0.17 97.80 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.1082096381
95.08 0.04 94.39 0.01 92.26 0.01 94.31 0.00 94.17 0.01 97.55 0.17 97.81 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2589803662
95.12 0.03 94.39 0.00 92.36 0.10 94.31 0.00 94.22 0.05 97.55 0.00 97.86 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2436971008
95.15 0.03 94.39 0.00 92.37 0.01 94.31 0.00 94.22 0.00 97.55 0.00 98.04 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.4253134135
95.18 0.03 94.47 0.07 92.37 0.00 94.42 0.11 94.23 0.01 97.55 0.00 98.04 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2170962987
95.21 0.03 94.54 0.07 92.40 0.03 94.44 0.02 94.28 0.05 97.55 0.00 98.04 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.915038103
95.24 0.03 94.60 0.07 92.45 0.05 94.47 0.03 94.30 0.02 97.55 0.00 98.04 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.3003274841
95.26 0.03 94.60 0.00 92.47 0.02 94.48 0.01 94.30 0.00 97.55 0.00 98.18 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.787379769
95.29 0.03 94.60 0.00 92.47 0.00 94.48 0.00 94.30 0.00 97.55 0.00 98.34 0.16 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1365369033
95.32 0.03 94.67 0.07 92.52 0.05 94.48 0.00 94.33 0.03 97.55 0.00 98.34 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.4116731108
95.34 0.02 94.69 0.01 92.56 0.03 94.56 0.08 94.34 0.02 97.55 0.00 98.34 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.839548582
95.36 0.02 94.69 0.00 92.68 0.12 94.56 0.00 94.34 0.00 97.55 0.00 98.36 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1752627630
95.38 0.02 94.75 0.07 92.72 0.05 94.56 0.00 94.36 0.02 97.55 0.00 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.1919596689
95.40 0.02 94.75 0.00 92.85 0.13 94.56 0.00 94.36 0.00 97.55 0.00 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.4190767595
95.43 0.02 94.75 0.00 92.85 0.00 94.68 0.12 94.36 0.00 97.55 0.00 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.3979649516
95.44 0.02 94.75 0.00 92.86 0.01 94.68 0.00 94.36 0.00 97.55 0.00 98.46 0.11 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3996314033
95.46 0.02 94.75 0.01 92.88 0.02 94.77 0.09 94.36 0.00 97.55 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4265195440
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95.82 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.12 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.3600219617
95.82 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.13 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878317771
95.82 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.14 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.329808474
95.82 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.15 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1001048728
95.83 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.17 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2019089695
95.83 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.18 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3927467221
95.83 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.19 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.3241440931
95.83 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.20 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1588337604
95.83 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.21 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402426781
95.83 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.22 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.295771429
95.84 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.24 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1935030599
95.84 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.25 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.307215806
95.84 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.26 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.2090142256
95.84 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.27 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2951646949
95.84 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.28 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.2980768880
95.85 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.30 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1490267236
95.85 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.31 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.1911952445
95.85 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.32 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3899271256
95.85 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.33 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933513903
95.85 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.34 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3682266848
95.86 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.35 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.4133658800
95.86 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.37 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.2552115061
95.86 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.38 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1118519700
95.86 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.39 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1935044186
95.86 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.40 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.858243029
95.87 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.41 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1710954873
95.87 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.42 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.394039205
95.87 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.44 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.1073986243
95.87 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.45 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1548377098
95.87 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.46 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3217809503
95.88 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.47 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2541465034
95.88 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.48 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.872135000
95.88 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.49 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2764498965
95.88 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.51 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.4103703881
95.88 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.52 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2308303498
95.89 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.53 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.1875132841
95.89 0.01 94.87 0.00 93.57 0.00 95.39 0.00 94.41 0.00 97.55 0.00 99.54 0.01 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.2783016662
95.89 0.01 94.87 0.00 93.58 0.01 95.39 0.00 94.41 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.1439965248
95.89 0.01 94.87 0.00 93.59 0.01 95.39 0.00 94.41 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2051197514
95.89 0.01 94.87 0.01 93.59 0.00 95.40 0.01 94.41 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.347595985
95.89 0.01 94.87 0.00 93.59 0.00 95.41 0.01 94.41 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.379590336
95.90 0.01 94.87 0.00 93.59 0.00 95.41 0.01 94.41 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2414217129
95.90 0.01 94.87 0.00 93.59 0.00 95.42 0.01 94.41 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.4043659183
95.90 0.01 94.87 0.00 93.59 0.00 95.42 0.00 94.42 0.01 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.59304802
95.90 0.01 94.87 0.00 93.59 0.00 95.42 0.00 94.43 0.01 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.2670999556
95.90 0.01 94.87 0.00 93.60 0.01 95.42 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.435032938
95.90 0.01 94.87 0.00 93.60 0.01 95.42 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.520397038
95.90 0.01 94.87 0.00 93.61 0.01 95.42 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.1629295310
95.91 0.01 94.87 0.00 93.62 0.01 95.42 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.195206721
95.91 0.01 94.87 0.00 93.63 0.01 95.42 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4134365247
95.91 0.01 94.87 0.00 93.63 0.00 95.43 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1115809558
95.91 0.01 94.87 0.00 93.63 0.00 95.44 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3475466010
95.91 0.01 94.87 0.00 93.63 0.00 95.45 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2106728307
95.91 0.01 94.87 0.01 93.63 0.01 95.45 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1167082974
95.91 0.01 94.87 0.00 93.63 0.00 95.45 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.905477403
95.91 0.01 94.87 0.00 93.63 0.00 95.45 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.861097106
95.91 0.01 94.87 0.00 93.63 0.00 95.46 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1721138731
95.91 0.01 94.87 0.00 93.63 0.00 95.46 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1522989354
95.91 0.01 94.87 0.00 93.63 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.633985501
95.92 0.01 94.87 0.00 93.64 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.301951560
95.92 0.01 94.87 0.00 93.64 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3959483762
95.92 0.01 94.87 0.00 93.64 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.911259610
95.92 0.01 94.87 0.00 93.65 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.475208147
95.92 0.01 94.87 0.00 93.65 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1598665814
95.92 0.01 94.87 0.00 93.65 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.765111418
95.92 0.01 94.87 0.00 93.66 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1889640534
95.92 0.01 94.87 0.00 93.66 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.2369602708
95.92 0.01 94.87 0.00 93.66 0.01 95.46 0.00 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.3561752100
95.92 0.01 94.87 0.00 93.66 0.00 95.47 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1189574748
95.92 0.01 94.87 0.00 93.66 0.00 95.47 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2834452714
95.92 0.01 94.87 0.00 93.66 0.00 95.47 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.512421205
95.92 0.01 94.87 0.00 93.66 0.00 95.47 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4106333473
95.92 0.01 94.87 0.00 93.66 0.00 95.48 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.463992406
95.92 0.01 94.87 0.00 93.66 0.00 95.48 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3778125158
95.92 0.01 94.87 0.00 93.66 0.00 95.48 0.01 94.43 0.00 97.55 0.00 99.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3026284759

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1659281967
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.936463139
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2076179869
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/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.707863192



Total test records in report: 2931
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.1900233408 Sep 04 07:32:42 PM UTC 24 Sep 04 07:34:32 PM UTC 24 2822605166 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.1280370758 Sep 04 07:34:47 PM UTC 24 Sep 04 07:37:24 PM UTC 24 2594047080 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.2726587725 Sep 04 07:35:57 PM UTC 24 Sep 04 07:38:34 PM UTC 24 2354649800 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.2677812549 Sep 04 07:34:55 PM UTC 24 Sep 04 07:38:39 PM UTC 24 2644349216 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.884849816 Sep 04 07:34:32 PM UTC 24 Sep 04 07:38:45 PM UTC 24 2648572180 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.3743300185 Sep 04 07:35:08 PM UTC 24 Sep 04 07:39:08 PM UTC 24 2715313576 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.28314135 Sep 04 07:34:32 PM UTC 24 Sep 04 07:39:18 PM UTC 24 3089331374 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.4261597626 Sep 04 07:35:30 PM UTC 24 Sep 04 07:39:21 PM UTC 24 3284041992 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2086005072 Sep 04 07:35:45 PM UTC 24 Sep 04 07:39:39 PM UTC 24 2598699020 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.4017141961 Sep 04 07:35:26 PM UTC 24 Sep 04 07:40:15 PM UTC 24 3834356762 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.4111240438 Sep 04 07:35:07 PM UTC 24 Sep 04 07:40:23 PM UTC 24 4411635220 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2530987797 Sep 04 07:32:57 PM UTC 24 Sep 04 07:40:58 PM UTC 24 3949874070 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.2728760473 Sep 04 07:33:48 PM UTC 24 Sep 04 07:41:03 PM UTC 24 3654846750 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1372352783 Sep 04 07:36:07 PM UTC 24 Sep 04 07:41:51 PM UTC 24 3169061912 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.2382351114 Sep 04 07:34:45 PM UTC 24 Sep 04 07:41:52 PM UTC 24 3709281544 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.839548582 Sep 04 07:34:45 PM UTC 24 Sep 04 07:42:03 PM UTC 24 3302037814 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.1508930114 Sep 04 07:33:38 PM UTC 24 Sep 04 07:42:12 PM UTC 24 4488118800 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.883962366 Sep 04 07:34:21 PM UTC 24 Sep 04 07:42:45 PM UTC 24 4097647750 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1661680345 Sep 04 07:36:01 PM UTC 24 Sep 04 07:42:49 PM UTC 24 3184641734 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.1281231491 Sep 04 07:35:08 PM UTC 24 Sep 04 07:42:55 PM UTC 24 3459327728 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2945445753 Sep 04 07:35:58 PM UTC 24 Sep 04 07:43:06 PM UTC 24 3942952758 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3846161492 Sep 04 07:34:04 PM UTC 24 Sep 04 07:43:33 PM UTC 24 4011718283 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.442383934 Sep 04 07:38:15 PM UTC 24 Sep 04 07:43:38 PM UTC 24 3662454648 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.3003274841 Sep 04 07:36:08 PM UTC 24 Sep 04 07:43:50 PM UTC 24 5212978444 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3497120571 Sep 04 07:36:51 PM UTC 24 Sep 04 07:44:04 PM UTC 24 4202059331 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2924493686 Sep 04 07:35:05 PM UTC 24 Sep 04 07:44:42 PM UTC 24 4779117728 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.778335594 Sep 04 07:35:10 PM UTC 24 Sep 04 07:44:46 PM UTC 24 4447349820 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3475466010 Sep 04 07:41:14 PM UTC 24 Sep 04 07:44:57 PM UTC 24 3235215469 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.1954802028 Sep 04 07:39:39 PM UTC 24 Sep 04 07:45:05 PM UTC 24 2874446672 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.4120232281 Sep 04 07:41:22 PM UTC 24 Sep 04 07:45:08 PM UTC 24 2528334026 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3889288024 Sep 04 07:42:00 PM UTC 24 Sep 04 07:45:12 PM UTC 24 3027779709 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1887345149 Sep 04 07:40:38 PM UTC 24 Sep 04 07:45:27 PM UTC 24 2615956548 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1362826227 Sep 04 07:42:00 PM UTC 24 Sep 04 07:45:41 PM UTC 24 3044381319 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.1629295310 Sep 04 07:36:06 PM UTC 24 Sep 04 07:46:00 PM UTC 24 3841892140 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3374869483 Sep 04 07:44:01 PM UTC 24 Sep 04 07:46:11 PM UTC 24 2680080229 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1873365472 Sep 04 07:43:06 PM UTC 24 Sep 04 07:46:11 PM UTC 24 3332595998 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.725548131 Sep 04 07:43:02 PM UTC 24 Sep 04 07:46:12 PM UTC 24 3683551882 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3462141115 Sep 04 07:36:09 PM UTC 24 Sep 04 07:46:15 PM UTC 24 5552893256 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1486331198 Sep 04 07:35:31 PM UTC 24 Sep 04 07:46:18 PM UTC 24 4719279620 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2158885517 Sep 04 07:44:01 PM UTC 24 Sep 04 07:46:20 PM UTC 24 2784326181 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2909813321 Sep 04 07:36:21 PM UTC 24 Sep 04 07:46:25 PM UTC 24 4373941690 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1169875682 Sep 04 07:34:56 PM UTC 24 Sep 04 07:46:31 PM UTC 24 6211920328 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.765111418 Sep 04 07:34:44 PM UTC 24 Sep 04 07:46:35 PM UTC 24 4461083400 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.4120632602 Sep 04 07:36:50 PM UTC 24 Sep 04 07:46:43 PM UTC 24 4976608908 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.2534905021 Sep 04 07:36:00 PM UTC 24 Sep 04 07:47:13 PM UTC 24 6708443059 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1889640534 Sep 04 07:36:46 PM UTC 24 Sep 04 07:47:52 PM UTC 24 4813686748 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.2976064124 Sep 04 07:42:03 PM UTC 24 Sep 04 07:48:13 PM UTC 24 5867310551 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4194893922 Sep 04 07:41:19 PM UTC 24 Sep 04 07:48:22 PM UTC 24 5162555474 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.514901811 Sep 04 07:44:58 PM UTC 24 Sep 04 07:48:36 PM UTC 24 2505006388 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1542702682 Sep 04 07:40:34 PM UTC 24 Sep 04 07:49:34 PM UTC 24 3651025050 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.1344912739 Sep 04 07:45:04 PM UTC 24 Sep 04 07:51:13 PM UTC 24 5050823470 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.226062758 Sep 04 07:48:20 PM UTC 24 Sep 04 07:55:48 PM UTC 24 4645098574 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.3452130614 Sep 04 07:37:13 PM UTC 24 Sep 04 07:52:41 PM UTC 24 5145265380 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4265195440 Sep 04 07:36:07 PM UTC 24 Sep 04 07:52:45 PM UTC 24 9273934299 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3502055685 Sep 04 07:38:15 PM UTC 24 Sep 04 07:53:09 PM UTC 24 5512452171 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1330669002 Sep 04 07:39:39 PM UTC 24 Sep 04 07:53:29 PM UTC 24 4884768357 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2435237934 Sep 04 07:45:02 PM UTC 24 Sep 04 07:53:35 PM UTC 24 4787031630 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.161169576 Sep 04 07:49:12 PM UTC 24 Sep 04 07:54:15 PM UTC 24 3669245340 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.24939090 Sep 04 07:49:30 PM UTC 24 Sep 04 07:54:36 PM UTC 24 2872376872 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.1447341884 Sep 04 07:35:10 PM UTC 24 Sep 04 07:54:38 PM UTC 24 9386870650 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2206302656 Sep 04 07:49:52 PM UTC 24 Sep 04 07:55:23 PM UTC 24 3165269832 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2106728307 Sep 04 07:49:38 PM UTC 24 Sep 04 07:55:47 PM UTC 24 3615886070 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.804077461 Sep 04 07:48:30 PM UTC 24 Sep 04 07:56:25 PM UTC 24 8293249187 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3225538663 Sep 04 07:49:56 PM UTC 24 Sep 04 07:56:39 PM UTC 24 3773577776 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3276747669 Sep 04 07:49:30 PM UTC 24 Sep 04 07:56:51 PM UTC 24 4959983490 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2834452714 Sep 04 07:49:09 PM UTC 24 Sep 04 07:56:54 PM UTC 24 7240109052 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.2855379685 Sep 04 07:50:14 PM UTC 24 Sep 04 07:56:59 PM UTC 24 3151513088 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1146147032 Sep 04 07:49:57 PM UTC 24 Sep 04 07:57:03 PM UTC 24 5947014292 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2088610433 Sep 04 07:49:58 PM UTC 24 Sep 04 07:57:22 PM UTC 24 4147277780 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.2641269302 Sep 04 07:49:30 PM UTC 24 Sep 04 07:57:37 PM UTC 24 4063321308 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.792715087 Sep 04 07:53:52 PM UTC 24 Sep 04 07:58:17 PM UTC 24 2998410767 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2077672515 Sep 04 07:49:57 PM UTC 24 Sep 04 07:58:28 PM UTC 24 5792371316 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3620456995 Sep 04 07:51:58 PM UTC 24 Sep 04 07:58:38 PM UTC 24 3678761296 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.378589710 Sep 04 07:54:15 PM UTC 24 Sep 04 07:58:40 PM UTC 24 2561025150 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2980165665 Sep 04 07:40:42 PM UTC 24 Sep 04 07:58:45 PM UTC 24 8528885472 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.964619104 Sep 04 07:44:02 PM UTC 24 Sep 04 07:59:00 PM UTC 24 11336291818 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.886491964 Sep 04 07:49:14 PM UTC 24 Sep 04 07:59:13 PM UTC 24 4389458054 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.2445275600 Sep 04 07:54:29 PM UTC 24 Sep 04 07:59:28 PM UTC 24 3011815832 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2917144883 Sep 04 07:40:53 PM UTC 24 Sep 04 07:59:37 PM UTC 24 9710230732 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.2212687772 Sep 04 07:54:15 PM UTC 24 Sep 04 07:59:47 PM UTC 24 3225689419 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.783875544 Sep 04 07:57:05 PM UTC 24 Sep 04 08:00:02 PM UTC 24 2410521538 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2414217129 Sep 04 07:49:41 PM UTC 24 Sep 04 08:00:04 PM UTC 24 19099598830 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1406383888 Sep 04 07:48:07 PM UTC 24 Sep 04 08:00:54 PM UTC 24 8763553392 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3690552751 Sep 04 07:50:10 PM UTC 24 Sep 04 08:00:56 PM UTC 24 7829094920 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3760112941 Sep 04 07:55:35 PM UTC 24 Sep 04 08:01:42 PM UTC 24 4273762400 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.293433616 Sep 04 07:56:43 PM UTC 24 Sep 04 08:01:51 PM UTC 24 2723577534 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.774745726 Sep 04 07:49:58 PM UTC 24 Sep 04 08:01:53 PM UTC 24 7770457916 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2146126725 Sep 04 07:40:42 PM UTC 24 Sep 04 08:01:59 PM UTC 24 7943815352 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.2086324121 Sep 04 07:58:39 PM UTC 24 Sep 04 08:02:17 PM UTC 24 2899359976 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.399662900 Sep 04 07:54:36 PM UTC 24 Sep 04 08:02:35 PM UTC 24 5248695672 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.907136769 Sep 04 07:54:37 PM UTC 24 Sep 04 08:02:35 PM UTC 24 4774682496 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1273749985 Sep 04 07:35:25 PM UTC 24 Sep 04 08:04:16 PM UTC 24 8231752586 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.1447973054 Sep 04 07:58:55 PM UTC 24 Sep 04 08:04:35 PM UTC 24 3659959992 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3648597484 Sep 04 07:48:04 PM UTC 24 Sep 04 08:04:57 PM UTC 24 7505623480 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1256322819 Sep 04 08:01:07 PM UTC 24 Sep 04 08:05:07 PM UTC 24 2457286100 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4134365247 Sep 04 07:51:54 PM UTC 24 Sep 04 08:05:18 PM UTC 24 5202931324 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.3778696365 Sep 04 07:49:56 PM UTC 24 Sep 04 08:05:39 PM UTC 24 5366040200 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.1088803000 Sep 04 08:01:10 PM UTC 24 Sep 04 08:05:53 PM UTC 24 2720776392 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1588212692 Sep 04 08:00:33 PM UTC 24 Sep 04 08:06:04 PM UTC 24 3378594650 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.3038639936 Sep 04 07:38:31 PM UTC 24 Sep 04 08:06:19 PM UTC 24 16183637237 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.3337907531 Sep 04 08:01:16 PM UTC 24 Sep 04 08:06:21 PM UTC 24 3078685367 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.2552518917 Sep 04 08:01:10 PM UTC 24 Sep 04 08:06:28 PM UTC 24 2925659338 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.512421205 Sep 04 07:58:38 PM UTC 24 Sep 04 08:07:05 PM UTC 24 3215044822 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.2674678836 Sep 04 08:01:16 PM UTC 24 Sep 04 08:07:13 PM UTC 24 3543821860 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2534589109 Sep 04 08:03:38 PM UTC 24 Sep 04 08:07:19 PM UTC 24 2924840216 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.1741037811 Sep 04 07:51:55 PM UTC 24 Sep 04 08:07:32 PM UTC 24 5014408200 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.336659281 Sep 04 08:03:38 PM UTC 24 Sep 04 08:07:37 PM UTC 24 2718270346 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.2915265015 Sep 04 08:03:34 PM UTC 24 Sep 04 08:07:37 PM UTC 24 3301381508 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.2893609235 Sep 04 08:03:31 PM UTC 24 Sep 04 08:08:36 PM UTC 24 2757748096 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1559927272 Sep 04 07:49:36 PM UTC 24 Sep 04 08:08:37 PM UTC 24 13763400134 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1926892654 Sep 04 07:58:51 PM UTC 24 Sep 04 08:08:45 PM UTC 24 6267578152 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2284692625 Sep 04 07:47:51 PM UTC 24 Sep 04 08:08:45 PM UTC 24 11015534239 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.2214742400 Sep 04 07:58:51 PM UTC 24 Sep 04 08:08:49 PM UTC 24 3847703512 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2307654549 Sep 04 08:03:31 PM UTC 24 Sep 04 08:08:52 PM UTC 24 3009682776 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.3076103531 Sep 04 08:06:47 PM UTC 24 Sep 04 08:11:52 PM UTC 24 2793370789 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.4065102222 Sep 04 08:08:53 PM UTC 24 Sep 04 08:12:37 PM UTC 24 2962310172 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.1169222394 Sep 04 07:45:05 PM UTC 24 Sep 04 08:13:12 PM UTC 24 12549007266 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3047001165 Sep 04 07:49:18 PM UTC 24 Sep 04 08:14:04 PM UTC 24 9463206924 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1676130746 Sep 04 08:08:58 PM UTC 24 Sep 04 08:15:24 PM UTC 24 5380889776 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3462323552 Sep 04 08:06:49 PM UTC 24 Sep 04 08:15:28 PM UTC 24 5204703942 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1189574748 Sep 04 07:54:35 PM UTC 24 Sep 04 08:15:36 PM UTC 24 7882080952 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.678488786 Sep 04 08:05:25 PM UTC 24 Sep 04 08:15:38 PM UTC 24 4431391229 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2466172348 Sep 04 08:05:26 PM UTC 24 Sep 04 08:15:58 PM UTC 24 4422963592 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.307389165 Sep 04 08:06:33 PM UTC 24 Sep 04 08:16:50 PM UTC 24 7678794920 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1115809558 Sep 04 08:08:51 PM UTC 24 Sep 04 08:16:54 PM UTC 24 5114499882 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.375880189 Sep 04 08:05:24 PM UTC 24 Sep 04 08:17:03 PM UTC 24 9486447654 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3127977660 Sep 04 08:06:07 PM UTC 24 Sep 04 08:17:04 PM UTC 24 7319378080 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3246255013 Sep 04 07:55:35 PM UTC 24 Sep 04 08:17:09 PM UTC 24 12246351796 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.4043659183 Sep 04 08:06:02 PM UTC 24 Sep 04 08:17:55 PM UTC 24 9157009904 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3457817911 Sep 04 08:08:57 PM UTC 24 Sep 04 08:18:26 PM UTC 24 5042247560 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2754151496 Sep 04 08:10:18 PM UTC 24 Sep 04 08:18:59 PM UTC 24 4609922960 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.865997936 Sep 04 08:08:02 PM UTC 24 Sep 04 08:19:06 PM UTC 24 3988450912 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1601672380 Sep 04 08:10:17 PM UTC 24 Sep 04 08:19:35 PM UTC 24 4973472450 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.3688169067 Sep 04 08:00:44 PM UTC 24 Sep 04 08:19:44 PM UTC 24 7093610336 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3435091750 Sep 04 08:06:18 PM UTC 24 Sep 04 08:19:45 PM UTC 24 7232750420 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.3380555069 Sep 04 08:16:19 PM UTC 24 Sep 04 08:20:00 PM UTC 24 2559051305 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2065950102 Sep 04 08:10:13 PM UTC 24 Sep 04 08:20:18 PM UTC 24 4196726600 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3859164151 Sep 04 08:02:01 PM UTC 24 Sep 04 08:20:18 PM UTC 24 6868698718 ps
T674 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.1171267216 Sep 04 08:13:56 PM UTC 24 Sep 04 08:20:22 PM UTC 24 3687030814 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.576155452 Sep 04 07:49:36 PM UTC 24 Sep 04 08:21:04 PM UTC 24 24482164236 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.905477403 Sep 04 07:56:09 PM UTC 24 Sep 04 08:21:06 PM UTC 24 6480985168 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4177938589 Sep 04 08:10:12 PM UTC 24 Sep 04 08:21:07 PM UTC 24 4632113058 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3214121766 Sep 04 08:14:48 PM UTC 24 Sep 04 08:21:21 PM UTC 24 3544782180 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.861097106 Sep 04 08:10:14 PM UTC 24 Sep 04 08:22:04 PM UTC 24 10093072234 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.658693651 Sep 04 08:10:13 PM UTC 24 Sep 04 08:22:11 PM UTC 24 4282481226 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1119786448 Sep 04 08:01:18 PM UTC 24 Sep 04 08:22:11 PM UTC 24 6627410730 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.701409964 Sep 04 08:01:18 PM UTC 24 Sep 04 08:22:18 PM UTC 24 7534019412 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3846287114 Sep 04 08:08:53 PM UTC 24 Sep 04 08:22:32 PM UTC 24 4460566868 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.4105863177 Sep 04 07:58:40 PM UTC 24 Sep 04 08:23:07 PM UTC 24 7271799444 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.400491738 Sep 04 07:58:30 PM UTC 24 Sep 04 08:23:14 PM UTC 24 5693140274 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.3600455382 Sep 04 08:20:40 PM UTC 24 Sep 04 08:23:18 PM UTC 24 2422084741 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3216633836 Sep 04 08:21:11 PM UTC 24 Sep 04 08:23:49 PM UTC 24 2502787025 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2053622293 Sep 04 08:02:01 PM UTC 24 Sep 04 08:24:01 PM UTC 24 7393702087 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.3806813832 Sep 04 08:01:05 PM UTC 24 Sep 04 08:24:05 PM UTC 24 6728924976 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3159517273 Sep 04 07:56:43 PM UTC 24 Sep 04 08:24:22 PM UTC 24 7067639550 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.195206721 Sep 04 08:18:10 PM UTC 24 Sep 04 08:24:27 PM UTC 24 3857232918 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2833543231 Sep 04 08:13:22 PM UTC 24 Sep 04 08:24:28 PM UTC 24 4704995076 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2223813178 Sep 04 08:12:36 PM UTC 24 Sep 04 08:24:55 PM UTC 24 4250222904 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.1902509172 Sep 04 08:08:55 PM UTC 24 Sep 04 08:25:26 PM UTC 24 10694092296 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1424478958 Sep 04 08:21:14 PM UTC 24 Sep 04 08:26:01 PM UTC 24 2839667752 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.723617670 Sep 04 07:36:22 PM UTC 24 Sep 04 08:26:04 PM UTC 24 12593149900 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2051197514 Sep 04 08:19:08 PM UTC 24 Sep 04 08:26:11 PM UTC 24 5077472340 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1721138731 Sep 04 08:18:24 PM UTC 24 Sep 04 08:26:17 PM UTC 24 3874614842 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2163005343 Sep 04 08:22:23 PM UTC 24 Sep 04 08:26:23 PM UTC 24 3018972467 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.240112760 Sep 04 08:18:25 PM UTC 24 Sep 04 08:26:43 PM UTC 24 7888443036 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.734591500 Sep 04 08:07:40 PM UTC 24 Sep 04 08:26:51 PM UTC 24 6307503658 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.13614719 Sep 04 08:01:17 PM UTC 24 Sep 04 08:26:53 PM UTC 24 7023399028 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3020989629 Sep 04 08:03:32 PM UTC 24 Sep 04 08:26:56 PM UTC 24 7878626312 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.3420164380 Sep 04 08:22:20 PM UTC 24 Sep 04 08:27:00 PM UTC 24 2879162641 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1146942079 Sep 04 08:16:20 PM UTC 24 Sep 04 08:27:08 PM UTC 24 4779756452 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4145865733 Sep 04 08:18:43 PM UTC 24 Sep 04 08:27:25 PM UTC 24 6026504200 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2298431549 Sep 04 08:22:20 PM UTC 24 Sep 04 08:27:27 PM UTC 24 3096958800 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.1155841598 Sep 04 08:02:00 PM UTC 24 Sep 04 08:27:27 PM UTC 24 8710145608 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1261199310 Sep 04 08:23:54 PM UTC 24 Sep 04 08:27:29 PM UTC 24 3120167490 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.673338118 Sep 04 08:23:37 PM UTC 24 Sep 04 08:27:48 PM UTC 24 3171461678 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3775400147 Sep 04 08:24:11 PM UTC 24 Sep 04 08:27:55 PM UTC 24 2301998658 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2072974771 Sep 04 08:19:52 PM UTC 24 Sep 04 08:27:59 PM UTC 24 5838640812 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.658966238 Sep 04 08:24:08 PM UTC 24 Sep 04 08:28:09 PM UTC 24 2695196185 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.3903115805 Sep 04 08:19:51 PM UTC 24 Sep 04 08:28:16 PM UTC 24 5269386552 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2333435721 Sep 04 07:50:00 PM UTC 24 Sep 04 08:28:27 PM UTC 24 25281944425 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2625908041 Sep 04 08:20:40 PM UTC 24 Sep 04 08:29:01 PM UTC 24 6050990232 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1961560306 Sep 04 07:45:02 PM UTC 24 Sep 04 08:29:38 PM UTC 24 32780470271 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.951439136 Sep 04 08:24:32 PM UTC 24 Sep 04 08:29:39 PM UTC 24 3616716930 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.59304802 Sep 04 08:20:43 PM UTC 24 Sep 04 08:30:13 PM UTC 24 4764480098 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2170962987 Sep 04 08:20:43 PM UTC 24 Sep 04 08:30:18 PM UTC 24 7445913609 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.1939902687 Sep 04 08:22:24 PM UTC 24 Sep 04 08:31:56 PM UTC 24 4927376088 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.3817883691 Sep 04 08:16:06 PM UTC 24 Sep 04 08:32:03 PM UTC 24 9379974406 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.4294377939 Sep 04 08:16:41 PM UTC 24 Sep 04 08:32:48 PM UTC 24 7551054124 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1906557320 Sep 04 08:24:52 PM UTC 24 Sep 04 08:33:17 PM UTC 24 4532723547 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2177411164 Sep 04 08:23:31 PM UTC 24 Sep 04 08:33:39 PM UTC 24 5099786383 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2510332167 Sep 04 08:18:40 PM UTC 24 Sep 04 08:35:05 PM UTC 24 22861953432 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.3287692619 Sep 04 08:25:39 PM UTC 24 Sep 04 08:35:12 PM UTC 24 4257468452 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.2125614463 Sep 04 08:32:01 PM UTC 24 Sep 04 08:35:27 PM UTC 24 2975886596 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.4040749982 Sep 04 08:25:44 PM UTC 24 Sep 04 08:36:11 PM UTC 24 11457122404 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.2214664654 Sep 04 08:16:07 PM UTC 24 Sep 04 08:38:01 PM UTC 24 13704697850 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3414204949 Sep 04 08:18:39 PM UTC 24 Sep 04 08:39:00 PM UTC 24 21171714530 ps
T901 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1218486776 Sep 04 08:23:36 PM UTC 24 Sep 04 08:39:43 PM UTC 24 6986766960 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4129287786 Sep 04 08:07:28 PM UTC 24 Sep 04 08:40:04 PM UTC 24 21460971707 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1698333333 Sep 04 08:27:18 PM UTC 24 Sep 04 08:42:19 PM UTC 24 5620592342 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.4248720251 Sep 04 08:21:13 PM UTC 24 Sep 04 08:45:36 PM UTC 24 13985699605 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3213311275 Sep 04 08:24:11 PM UTC 24 Sep 04 08:50:02 PM UTC 24 9846946543 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.80044906 Sep 04 07:49:35 PM UTC 24 Sep 04 08:51:11 PM UTC 24 20776277716 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.1533306715 Sep 04 08:28:48 PM UTC 24 Sep 04 08:52:05 PM UTC 24 5491737580 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.1035384391 Sep 04 08:24:49 PM UTC 24 Sep 04 08:56:03 PM UTC 24 20065697884 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.1333294840 Sep 04 07:35:26 PM UTC 24 Sep 04 08:56:21 PM UTC 24 18481317120 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3868824243 Sep 04 07:50:00 PM UTC 24 Sep 04 08:59:34 PM UTC 24 17712388368 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.1422380852 Sep 04 09:22:13 PM UTC 24 Sep 04 09:26:19 PM UTC 24 5843300460 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1537530372 Sep 04 07:50:11 PM UTC 24 Sep 04 08:59:51 PM UTC 24 18706076612 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.4244168372 Sep 04 07:38:31 PM UTC 24 Sep 04 09:14:58 PM UTC 24 45117164140 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1870455754 Sep 04 08:43:01 PM UTC 24 Sep 04 09:21:15 PM UTC 24 11422285085 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1204345038 Sep 04 08:33:34 PM UTC 24 Sep 04 09:21:24 PM UTC 24 11344910272 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.277860316 Sep 04 08:36:57 PM UTC 24 Sep 04 09:22:32 PM UTC 24 11009182170 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.1449848952 Sep 04 07:58:41 PM UTC 24 Sep 04 09:23:00 PM UTC 24 17946292914 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.2978565510 Sep 04 08:03:30 PM UTC 24 Sep 04 09:23:35 PM UTC 24 16981483918 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.624348218 Sep 04 09:22:12 PM UTC 24 Sep 04 09:24:24 PM UTC 24 1887133062 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.58076427 Sep 04 08:32:04 PM UTC 24 Sep 04 09:26:50 PM UTC 24 12068102200 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.707240216 Sep 04 07:41:19 PM UTC 24 Sep 04 09:27:18 PM UTC 24 28247679854 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.4030672561 Sep 04 08:46:18 PM UTC 24 Sep 04 09:27:20 PM UTC 24 11517499536 ps
T659 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.3111763693 Sep 04 08:50:44 PM UTC 24 Sep 04 09:27:35 PM UTC 24 12153676834 ps
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T371 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.110823571 Sep 04 08:35:04 PM UTC 24 Sep 04 09:39:57 PM UTC 24 15361385812 ps
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