Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	506	1			T433	2		T546	2		T415	1
all_values[1]	521	1			T433	1		T546	2		T415	2
all_values[2]	474	1			T546	3		T415	1		T414	2
all_values[3]	474	1			T546	2		T415	2		T414	1
all_values[4]	470	1			T546	2		T414	2		T597	2
all_values[5]	481	1			T546	3		T415	1		T557	1
all_values[6]	518	1			T546	3		T825	1		T415	2
all_values[7]	480	1			T546	1		T415	1		T414	1
all_values[8]	508	1			T433	1		T415	3		T414	2
all_values[9]	473	1			T677	1		T415	1		T414	2
all_values[10]	463	1			T546	4		T414	2		T557	1
all_values[11]	461	1			T433	1		T546	1		T415	1
all_values[12]	492	1			T546	3		T415	2		T414	1
all_values[13]	475	1			T824	1		T825	1		T415	1
all_values[14]	462	1			T677	1		T546	2		T428	1
all_values[15]	450	1			T546	2		T557	1		T814	1
all_values[16]	509	1			T415	1		T414	2		T557	1
all_values[17]	485	1			T433	1		T546	1		T415	2
all_values[18]	483	1			T546	3		T415	1		T414	1
all_values[19]	493	1			T546	3		T415	1		T557	4
all_values[20]	459	1			T546	4		T415	1		T557	8
all_values[21]	447	1			T546	1		T415	4		T522	3
all_values[22]	480	1			T546	2		T415	2		T414	2
all_values[23]	462	1			T546	2		T414	1		T557	2
all_values[24]	448	1			T546	2		T415	1		T414	1
all_values[25]	463	1			T546	3		T597	1		T522	3
all_values[26]	508	1			T546	2		T415	2		T557	1
all_values[27]	484	1			T415	1		T414	1		T557	1
all_values[28]	472	1			T546	2		T415	1		T414	1
all_values[29]	477	1			T546	2		T414	1		T557	2
all_values[30]	469	1			T546	2		T415	2		T414	2
all_values[31]	448	1			T546	1		T415	3		T557	5
all_values[32]	501	1			T433	1		T546	3		T414	3
all_values[33]	488	1			T415	2		T428	1		T611	1
all_values[34]	456	1			T546	1		T557	1		T597	1
all_values[35]	449	1			T546	1		T415	1		T557	2
all_values[36]	493	1			T546	4		T557	1		T428	1
all_values[37]	464	1			T546	1		T414	2		T557	3
all_values[38]	468	1			T433	1		T546	1		T415	3
all_values[39]	455	1			T415	2		T414	2		T557	2
all_values[40]	497	1			T546	1		T824	1		T415	2
all_values[41]	459	1			T546	1		T557	1		T428	1
all_values[42]	506	1			T546	3		T415	2		T557	3
all_values[43]	449	1			T546	3		T415	1		T414	1
all_values[44]	440	1			T546	1		T415	2		T414	1
all_values[45]	485	1			T557	3		T428	1		T597	1
all_values[46]	479	1			T546	1		T414	1		T557	2
all_values[47]	483	1			T546	2		T557	1		T597	1
all_values[48]	447	1			T546	2		T415	1		T557	1
all_values[49]	476	1			T415	1		T414	2		T557	3