Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3339	1			T447	1		T546	8		T543	3
all_values[1]	3394	1			T447	1		T546	12		T543	3
all_values[2]	3321	1			T447	3		T546	10		T543	4
all_values[3]	3505	1			T447	2		T552	1		T546	6
all_values[4]	3366	1			T447	4		T552	1		T546	7
all_values[5]	3341	1			T447	2		T546	13		T543	2
all_values[6]	3460	1			T447	6		T546	14		T543	4
all_values[7]	3485	1			T447	3		T552	1		T546	9
all_values[8]	3354	1			T546	9		T543	6		T556	1
all_values[9]	3403	1			T552	1		T546	8		T543	1
all_values[10]	3423	1			T447	2		T552	1		T546	15
all_values[11]	3389	1			T447	5		T546	6		T543	2
all_values[12]	3361	1			T447	2		T552	1		T546	10
all_values[13]	3391	1			T447	2		T546	9		T543	2
all_values[14]	3357	1			T447	1		T546	14		T543	1
all_values[15]	3363	1			T447	3		T546	9		T543	3
all_values[16]	3416	1			T447	3		T552	2		T546	11
all_values[17]	3446	1			T447	1		T552	2		T546	5
all_values[18]	3399	1			T447	4		T546	6		T543	1
all_values[19]	3304	1			T447	1		T546	3		T543	1
all_values[20]	3374	1			T447	1		T546	2		T543	2
all_values[21]	3557	1			T447	4		T546	9		T543	3
all_values[22]	3453	1			T447	6		T546	9		T543	2
all_values[23]	3428	1			T447	3		T552	1		T546	10
all_values[24]	3332	1			T447	3		T552	1		T546	8
all_values[25]	3365	1			T447	2		T552	1		T546	7
all_values[26]	3428	1			T447	2		T546	11		T543	1
all_values[27]	3428	1			T447	8		T546	4		T543	4
all_values[28]	3351	1			T447	5		T552	1		T546	4
all_values[29]	3475	1			T447	2		T546	8		T543	3
all_values[30]	3463	1			T447	1		T552	1		T546	2
all_values[31]	3388	1			T447	3		T546	4		T543	1
all_values[32]	3475	1			T447	4		T546	10		T543	2
all_values[33]	3416	1			T447	2		T552	1		T546	15
all_values[34]	3447	1			T447	2		T552	1		T546	6
all_values[35]	3346	1			T447	3		T552	1		T546	12
all_values[36]	3441	1			T447	3		T552	2		T546	8
all_values[37]	3354	1			T447	4		T552	3		T546	7
all_values[38]	3364	1			T447	2		T546	9		T543	1
all_values[39]	3393	1			T447	5		T552	1		T546	13
all_values[40]	3334	1			T447	4		T552	2		T546	7
all_values[41]	3429	1			T447	2		T552	1		T546	15
all_values[42]	3350	1			T447	2		T546	10		T543	3
all_values[43]	3356	1			T447	1		T552	1		T546	6
all_values[44]	3371	1			T447	5		T546	13		T543	4
all_values[45]	3387	1			T447	5		T546	6		T543	3
all_values[46]	3431	1			T546	13		T543	3		T556	1
all_values[47]	3431	1			T447	2		T546	14		T543	2
all_values[48]	3436	1			T447	1		T546	6		T543	1
all_values[49]	3351	1			T447	2		T546	13		T543	1
all_values[50]	3367	1			T552	2		T546	6		T543	2
all_values[51]	3446	1			T447	3		T546	10		T543	3
all_values[52]	3387	1			T447	4		T546	4		T543	3
all_values[53]	3462	1			T447	4		T552	2		T546	12
all_values[54]	3371	1			T447	3		T546	9		T543	1
all_values[55]	3335	1			T447	1		T552	2		T546	3
all_values[56]	3304	1			T447	4		T552	1		T546	7
all_values[57]	3486	1			T447	1		T546	12		T543	4
all_values[58]	3371	1			T447	5		T546	10		T543	4
all_values[59]	3391	1			T447	5		T552	1		T546	13
all_values[60]	3319	1			T447	5		T552	1		T546	10
all_values[61]	3412	1			T447	2		T546	8		T543	4
all_values[62]	3402	1			T447	2		T552	3		T546	13
all_values[63]	3404	1			T447	4		T552	1		T546	14