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 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T73,T239,T446
1	0	1	Covered	T45,T79,T81
1	1	0	Covered	T540,T558,T414
1	1	1	Covered	T45,T79,T81

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T79,T81
1	0	1	Covered	T45,T79,T81
1	1	0	Covered	T414,T454,T470
1	1	1	Covered	T446,T122,T382

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T79,T81
1	0	1	Covered	T81,T287,T292
1	1	0	Covered	T92,T447,T546
1	1	1	Covered	T438,T168,T414

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T438,T539,T168
1	1	0	Not Covered
1	1	1	Covered	T9,T31,T5

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T449,T268,T447
1	1	0	Covered	T636,T637
1	1	1	Covered	T9,T31,T5

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T31,T5
1	0	1	Covered	T540,T539,T168
1	1	0	Covered	T638
1	1	1	Covered	T2,T3,T4