Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T113 T124 T315 | T113 T124 T315 | T113 T124 T315 | T113 T124 T315 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T113 T124 T315 | T114 T315 T125 | T114 T315 T125 | T114 T315 T125 | T114 T315 T125 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T114 T315 T125 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T35 T63 T64 | T30 T315 T65 | T30 T315 T65 | T30 T315 T65 | T30 T315 T65 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T30 T315 T65 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T11 T120 T210 | T120 T180 T181 | T120 T180 T181 | T120 T180 T181 | T120 T180 T181 | T15 T120 T51 | T120 T180 T181 | T120 T180 T181 | T58 T306 T59 | T58 T306 T59 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T58 T306 T59 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T60 T306 T131 | T60 T306 T131 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T60 T306 T61 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T62 T306 T132 | T62 T306 T132 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T34 T62 T306 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T5 T120 T323 | T5 T120 T323 | T120 T180 T181 | T120 T180 T181 | T120 T180 T181 | T79 T231 T232 | T182 T325 T183 | T45 T306 T287 | T81 T183 T306 | T120 T180 T181 | T120 T180 T181 | T120 T180 T181 | T120 T180 T181 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T7 T14 T324 | T66 T315 T225 | T133 T306 T134 | T281 T257 T340 | T255 T257 T341 | T172 T120 T326 | T120 T180 T181 | T6 T316 T139 | T6 T316 T139 | T316 T139 T306 | T316 T139 T306 | T6 T316 T139 | T306 T321 T322 | T317 T318 T306 | T306 T321 T322 | T306 T321 T322 | T120 T180 T181 | T120 T180 T181 | T120 T180 T181 | T154 T120 T175 | T120 T180 T181 | T306 T321 T322 | T327 T306 T328 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T327 T306 T328 | T306 T321 T322 | T327 T306 T328 | T306 T321 T322
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T269 T270 T271 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T15 T32 T11 | T15 T269 T120 | T15 T269 T120 | T15 T11 T12 | T15 T11 T12 | T15 T269 T120 | T269 T120 T315 | T269 T120 T315 | T58 T269 T120 | T58 T269 T120 | T269 T120 T315 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T269 T120 T315 | T58 T269 T120 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T60 T269 T120 | T60 T269 T120 | T269 T120 T315 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T269 T120 T315 | T60 T269 T120 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T62 T269 T120 | T62 T269 T120 | T269 T120 T315 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T269 T120 T315 | T34 T62 T269 | T34 T269 T120 | T269 T120 T315 | T34 T269 T120 | T34 T269 T120 | T34 T269 T120 | T5 T269 T120 | T5 T269 T120 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T45 T79 T81 | T45 T79 T81 | T45 T79 T81 | T45 T79 T81 | T11 T12 T269 | T11 T12 T269 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T7 T14 T281 | T66 T269 T120 | T133 T269 T120 | T45 T79 T81 | T45 T255 T79 | T172 T269 T120 | T269 T120 T315 | T6 T316 T139 | T6 T316 T139 | T6 T316 T139 | T6 T316 T139 | T6 T316 T139 | T269 T120 T315 | T317 T318 T269 | T317 T318 T269 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T154 T269 T120 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T5 T6 T7 | T5 T113 T34 | T113 T30 T114 | T5 T34 T15 | T6 T7 T45 | T113 T30 T114 | T30 T32 T269 | T15 T32 T60 | T5 T34 T79 | T7 T45 T14 | T6 T316 T139 | T113 T114 T124 | T30 T114 T35 | T30 T32 T269 | T32 T269 T120 | T15 T32 T58 | T60 T58 T269 | T60 T62 T269 | T5 T34 T79 | T45 T79 T81 | T7 T14 T255 | T6 T316 T139 | T269 T120 T315 | T113 T124 T269 | T113 T114 T124 | T114 T35 T63 | T30 T35 T63 | T30 T32 T269 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T11 T269 | T15 T58 T11 | T58 T269 T120 | T60 T269 T120 | T60 T269 T120 | T62 T269 T120 | T34 T62 T269 | T5 T34 T79 | T45 T79 T81 | T269 T120 T315 | T269 T120 T315 | T7 T45 T14 | T6 T316 T139 | T154 T269 T120 | T269 T120 T315 | T113 T124 T269 | T113 T124 T269 | T113 T114 T124 | T114 T269 T120 | T114 T35 T63 | T35 T63 T64 | T35 T63 T64 | T30 T269 T120 | T30 T269 T120 | T30 T32 T269 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T15 T32 T11 | T15 T11 T12 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T269 T120 T315 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T34 T62 T269 | T5 T34 T269 | T79 T231 T232 | T45 T79 T81 | T11 T12 T269 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T7 T14 T66 | T45 T255 T79 | T6 T316 T139 | T6 T316 T139 | T269 T120 T315 | T154 T269 T120 | T269 T120 T315 | T269 T120 T315 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T35 T63 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T32 T269 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T15 T32 T11 | T15 T269 T120 | T15 T11 T12 | T15 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T269 T120 T315 | T269 T120 T315 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T269 T120 T315 | T269 T120 T315 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T34 T62 T269 | T34 T269 T120 | T34 T269 T120 | T5 T269 T120 | T269 T120 T315 | T45 T79 T81 | T45 T79 T81 | T45 T79 T81 | T11 T12 T269 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T7 T14 T281 | T66 T133 T269 | T45 T255 T79 | T172 T269 T120 | T6 T316 T139 | T6 T316 T139 | T6 T316 T139 | T317 T318 T269 | T269 T120 T315 | T269 T120 T315 | T154 T269 T120 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T5 T6 T7 | T5 T113 T34 | T6 T7 T45 | T113 T30 T114 | T5 T34 T15 | T6 T7 T45 | T113 T30 T114 | T30 T32 T315 | T15 T32 T60 | T5 T34 T79 | T7 T45 T14 | T6 T316 T139 | T113 T114 T124 | T30 T114 T35 | T30 T32 T315 | T32 T306 T43 | T15 T32 T58 | T60 T58 T306 | T60 T62 T306 | T5 T34 T79 | T45 T81 T182 | T7 T14 T255 | T6 T316 T139 | T327 T306 T328 | T113 T124 T315 | T113 T114 T124 | T114 T35 T63 | T30 T35 T63 | T30 T32 T315 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T11 T120 | T15 T58 T120 | T58 T306 T59 | T60 T306 T131 | T60 T306 T61 | T62 T306 T132 | T34 T62 T306 | T5 T79 T231 | T45 T81 T182 | T315 T319 T320 | T315 T319 T320 | T7 T14 T255 | T6 T316 T139 | T154 T120 T327 | T327 T306 T328 | T327 T306 T328 | T113 T124 T315 | T113 T124 T315 | T113 T114 T124 | T114 T315 T125 | T114 T35 T63 | T35 T63 T64 | T35 T63 T64 | T30 T315 T65 | T315 T319 T320 | T30 T32 T315 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T11 T120 | T15 T120 T51 | T58 T120 T306 | T306 T321 T322 | T58 T306 T59 | T306 T321 T322 | T60 T306 T131 | T306 T321 T322 | T60 T306 T61 | T62 T306 T132 | T62 T306 T132 | T306 T321 T322 | T34 T62 T306 | T5 T120 T306 | T79 T231 T232 | T45 T81 T182 | T120 T315 T180 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T7 T14 T66 | T255 T281 T257 | T6 T316 T139 | T6 T316 T139 | T120 T306 T180 | T154 T120 T327 | T306 T321 T322 | T327 T306 T328 | T327 T306 T328 | T113 T124 T315 | T113 T124 T315 | T113 T124 T315 | T315 T319 T320 | T113 T124 T315 | T114 T315 T125 | T114 T315 T125 | T315 T319 T320 | T315 T319 T320 | T114 T35 T63 | T35 T63 T64 | T35 T63 T64 | T315 T319 T320 | T35 T63 T64 | T30 T315 T65 | T30 T315 T65 | T315 T319 T320 | T315 T319 T320 | T30 T32 T315 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T11 T120 | T120 T180 T181 | T120 T180 T181 | T15 T120 T51 | T58 T120 T306 | T58 T306 T59 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T58 T306 T59 | T306 T321 T322 | T306 T321 T322 | T60 T306 T131 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T60 T306 T61 | T306 T321 T322 | T306 T321 T322 | T62 T306 T132 | T62 T306 T132 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T34 T62 T306 | T306 T321 T322 | T306 T321 T322 | T5 T120 T323 | T120 T180 T181 | T79 T231 T232 | T45 T182 T325 | T81 T183 T120 | T120 T180 T181 | T120 T315 T180 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T7 T14 T324 | T66 T133 T315 | T255 T281 T257 | T172 T120 T326 | T6 T316 T139 | T316 T139 T306 | T6 T316 T139 | T317 T318 T306 | T120 T306 T180 | T120 T180 T181 | T154 T120 T175 | T327 T306 T328 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T327 T306 T328 | T327 T306 T328
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T5 T6 T7 | T5 T113 T34 | T6 T7 T45 | T113 T30 T114 | T5 T34 T15 | T6 T7 T45 | T113 T30 T114 | T30 T32 T315 | T15 T32 T60 | T5 T34 T79 | T7 T45 T14 | T6 T316 T139 | T113 T114 T124 | T30 T114 T35 | T30 T32 T315 | T32 T306 T43 | T15 T32 T58 | T60 T58 T306 | T60 T62 T306 | T5 T34 T79 | T45 T81 T183 | T7 T14 T255 | T6 T316 T139 | T327 T306 T328 | T113 T124 T315 | T113 T114 T124 | T114 T35 T63 | T30 T35 T63 | T30 T32 T315 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T11 T120 | T15 T58 T120 | T58 T306 T59 | T60 T306 T131 | T60 T306 T61 | T62 T306 T132 | T34 T62 T306 | T5 T79 T231 | T45 T81 T183 | T315 T319 T320 | T315 T319 T320 | T7 T14 T255 | T6 T316 T139 | T154 T120 T327 | T327 T306 T328 | T306 T321 T322 | T113 T124 T315 | T315 T319 T320 | T113 T114 T124 | T114 T315 T125 | T114 T35 T63 | T35 T63 T64 | T35 T63 T64 | T30 T315 T65 | T315 T319 T320 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T11 T120 T210 | T15 T120 T51 | T58 T306 T59 | T306 T321 T322 | T58 T306 T59 | T306 T321 T322 | T60 T306 T131 | T306 T321 T322 | T60 T306 T61 | T62 T306 T132 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T5 T120 T306 | T79 T231 T232 | T45 T81 T183 | T120 T315 T180 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T7 T14 T66 | T255 T257 T341 | T6 T316 T139 | T317 T318 T306 | T120 T180 T181 | T120 T327 T306 | T306 T321 T322 | T327 T306 T328 | T306 T321 T322 | T113 T124 T315 | T113 T124 T315 | T315 T319 T320 | T315 T319 T320 | T113 T124 T315 | T114 T315 T125 | T114 T315 T125 | T315 T319 T320 | T315 T319 T320 | T35 T63 T64 | T35 T63 T64 | T315 T319 T320 | T315 T319 T320 | T35 T63 T64 | T30 T315 T65 | T30 T315 T65 | T315 T319 T320 | T315 T319 T320 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T32 T306 T43 | T11 T120 T210 | T120 T180 T181 | T120 T180 T181 | T120 T180 T181 | T58 T306 T59 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T60 T306 T131 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T60 T306 T61 | T306 T321 T322 | T306 T321 T322 | T62 T306 T132 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T5 T120 T323 | T120 T180 T181 | T79 T231 T232 | T45 T306 T287 | T120 T180 T181 | T120 T180 T181 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T315 T319 T320 | T7 T14 T324 | T133 T306 T134 | T255 T257 T341 | T120 T180 T181 | T6 T316 T139 | T316 T139 T306 | T306 T321 T322 | T306 T321 T322 | T120 T180 T181 | T120 T180 T181 | T120 T180 T181 | T327 T306 T328 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322 | T306 T321 T322
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T5 T6 T7 | T5 T113 T34 | T6 T7 T45 | T113 T30 T114 | T5 T34 T15 | T6 T7 T45 | T113 T30 T114 | T30 T32 T269 | T15 T32 T60 | T5 T34 T79 | T7 T45 T14 | T6 T316 T139 | T113 T114 T124 | T30 T114 T35 | T30 T32 T269 | T32 T269 T120 | T15 T32 T58 | T60 T58 T269 | T60 T62 T269 | T5 T34 T79 | T45 T79 T81 | T7 T14 T255 | T6 T316 T139 | T269 T120 T315 | T113 T124 T269 | T113 T114 T124 | T114 T35 T63 | T30 T35 T63 | T30 T32 T269 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T11 T269 | T15 T58 T11 | T58 T269 T120 | T60 T269 T120 | T60 T269 T120 | T62 T269 T120 | T34 T62 T269 | T5 T34 T79 | T45 T79 T81 | T269 T120 T315 | T269 T120 T315 | T7 T45 T14 | T6 T316 T139 | T154 T269 T120 | T269 T120 T315 | T269 T120 T315 | T113 T124 T269 | T113 T124 T269 | T113 T114 T124 | T114 T269 T120 | T114 T35 T63 | T35 T63 T64 | T35 T63 T64 | T30 T269 T120 | T30 T269 T120 | T30 T32 T269 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T15 T32 T11 | T15 T11 T12 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T269 T120 T315 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T34 T62 T269 | T5 T34 T269 | T79 T231 T232 | T45 T79 T81 | T11 T12 T269 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T7 T14 T66 | T45 T255 T79 | T6 T316 T139 | T6 T316 T139 | T269 T120 T315 | T154 T269 T120 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T113 T124 T269 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T269 T120 | T114 T35 T63 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T35 T63 T64 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T269 T120 | T30 T32 T269 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T32 T269 T120 | T15 T32 T11 | T15 T269 T120 | T15 T11 T12 | T15 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T58 T269 T120 | T269 T120 T315 | T269 T120 T315 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T60 T269 T120 | T269 T120 T315 | T269 T120 T315 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T62 T269 T120 | T34 T62 T269 | T34 T269 T120 | T34 T269 T120 | T5 T269 T120 | T269 T120 T315 | T45 T79 T81 | T45 T79 T81 | T45 T79 T81 | T11 T12 T269 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T7 T14 T281 | T66 T133 T269 | T45 T255 T79 | T172 T269 T120 | T6 T316 T139 | T6 T316 T139 | T6 T316 T139 | T317 T318 T269 | T269 T120 T315 | T269 T120 T315 | T154 T269 T120 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315 | T269 T120 T315
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T5 T6 T7
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T5 T6 T7
101 1/1 assign max_value_o = max_tree[0];
Tests: T5 T6 T7
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);