| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 2 | 0 | 2 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| falling | 145555 | 1 | T96 | 5 | T97 | 2 | T98 | 44 | ||||
| rising | 145633 | 1 | T96 | 5 | T97 | 2 | T98 | 44 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 5895705 | 1 | T96 | 180 | T97 | 109 | T98 | 1293 | ||||
| auto[1] | 153030 | 1 | T96 | 5 | T97 | 2 | T98 | 46 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |