Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.52 94.02 95.39 94.99 97.53 99.59


Total tests in report: 2926
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.03 40.03 44.94 44.94 46.52 46.52 27.65 27.65 63.08 63.08 57.87 57.87 0.14 0.14 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1043640595
48.39 8.35 52.76 7.82 55.73 9.21 29.80 2.15 70.69 7.61 80.94 23.08 0.39 0.25 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.3671950904
53.70 5.32 64.01 11.25 63.24 7.51 33.06 3.26 80.58 9.88 80.94 0.00 0.39 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3844850526
57.95 4.25 64.01 0.00 63.65 0.41 33.06 0.00 80.61 0.03 80.94 0.00 25.45 25.06 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.4045203578
61.47 3.52 69.99 5.97 67.45 3.81 40.21 7.15 82.80 2.19 82.69 1.75 25.70 0.25 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.932471286
64.97 3.49 74.81 4.82 69.54 2.09 44.83 4.62 82.96 0.16 82.69 0.00 34.97 9.27 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3269762800
68.01 3.05 79.60 4.80 73.29 3.75 48.32 3.49 84.67 1.71 87.24 4.55 34.97 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1778511807
70.91 2.89 79.60 0.00 73.29 0.00 48.32 0.00 84.67 0.00 87.24 0.00 52.33 17.37 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.4118532508
73.25 2.34 79.60 0.00 73.29 0.00 62.34 14.02 84.67 0.00 87.24 0.00 52.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1681880981
75.51 2.27 80.97 1.37 75.79 2.51 67.62 5.28 86.42 1.74 87.41 0.17 54.87 2.54 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.2633852953
77.42 1.90 80.97 0.00 75.86 0.06 67.62 0.00 86.42 0.00 87.41 0.00 66.22 11.35 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1169005043
78.86 1.45 81.09 0.12 75.95 0.09 75.74 8.12 86.59 0.17 87.59 0.17 66.22 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.1766652694
80.27 1.41 83.58 2.49 77.94 1.99 76.82 1.08 89.46 2.87 87.59 0.00 66.22 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.48236390
81.58 1.31 84.95 1.37 79.11 1.17 77.15 0.33 90.80 1.34 91.26 3.67 66.22 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1487252626
82.84 1.26 84.96 0.01 80.54 1.42 77.37 0.22 90.81 0.01 91.26 0.00 72.12 5.90 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1663190629
84.07 1.23 87.29 2.33 81.69 1.15 79.72 2.35 91.67 0.86 91.96 0.70 72.12 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3694627042
85.26 1.19 87.29 0.00 81.69 0.01 79.72 0.00 91.67 0.00 91.96 0.00 79.25 7.13 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3106533782
86.22 0.96 87.93 0.65 85.42 3.73 80.17 0.45 91.76 0.10 91.96 0.00 80.06 0.81 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.3278824742
87.07 0.85 88.60 0.67 85.67 0.25 80.19 0.01 92.06 0.30 95.80 3.85 80.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2016372361
87.79 0.72 88.60 0.00 85.74 0.06 80.19 0.00 92.06 0.00 95.80 0.00 84.33 4.27 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2099173813
88.50 0.71 88.60 0.00 85.80 0.06 80.19 0.00 92.06 0.00 95.80 0.00 88.53 4.21 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2640973180
89.07 0.57 89.64 1.04 86.23 0.44 81.89 1.70 92.31 0.24 95.80 0.00 88.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1154172586
89.62 0.55 90.72 1.08 86.39 0.16 83.40 1.51 92.36 0.05 96.33 0.52 88.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.650258269
90.09 0.47 90.72 0.00 86.52 0.13 83.40 0.00 92.37 0.02 96.33 0.00 91.19 2.66 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.90903704
90.54 0.46 91.79 1.07 87.01 0.49 84.14 0.74 92.81 0.44 96.33 0.00 91.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.169985749
90.97 0.43 91.87 0.08 87.05 0.03 86.57 2.43 92.83 0.02 96.33 0.00 91.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.551354972
91.38 0.40 92.60 0.73 88.23 1.18 86.97 0.40 92.94 0.11 96.33 0.00 91.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.748829420
91.69 0.32 92.94 0.34 88.23 0.00 87.29 0.32 92.94 0.00 96.33 0.00 92.43 1.25 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3456740196
92.01 0.32 92.94 0.00 88.24 0.01 87.29 0.00 92.94 0.00 96.33 0.00 94.32 1.89 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3938796771
92.27 0.26 92.94 0.00 88.24 0.00 88.86 1.57 92.94 0.00 96.33 0.00 94.32 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3227125488
92.53 0.26 93.34 0.40 88.72 0.48 89.06 0.20 93.43 0.49 96.33 0.00 94.32 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3831009326
92.78 0.24 93.34 0.00 88.72 0.00 89.06 0.00 93.43 0.00 96.33 0.00 95.79 1.47 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.633701848
93.01 0.24 93.34 0.00 88.72 0.01 89.06 0.00 93.43 0.00 96.33 0.00 97.20 1.41 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.967885738
93.23 0.22 93.34 0.00 88.72 0.00 90.38 1.33 93.43 0.00 96.33 0.00 97.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2211569267
93.40 0.17 93.65 0.31 88.95 0.23 90.59 0.20 93.70 0.27 96.33 0.00 97.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.147796572
93.55 0.15 93.74 0.09 89.72 0.77 90.60 0.01 93.70 0.00 96.33 0.00 97.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.3783395322
93.69 0.15 93.74 0.00 90.57 0.85 90.60 0.00 93.70 0.00 96.33 0.00 97.23 0.02 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.1790770761
93.84 0.14 93.74 0.00 90.57 0.00 91.25 0.65 93.70 0.00 96.50 0.17 97.27 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3939480237
93.97 0.13 93.79 0.04 90.91 0.35 91.28 0.03 94.09 0.39 96.50 0.00 97.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4167627519
94.10 0.12 93.79 0.00 90.91 0.00 92.02 0.74 94.09 0.00 96.50 0.00 97.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3027898118
94.22 0.12 93.99 0.21 91.23 0.32 92.23 0.20 94.09 0.00 96.50 0.00 97.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4260663534
94.33 0.11 94.16 0.17 91.39 0.15 92.42 0.20 94.26 0.17 96.50 0.00 97.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1208950703
94.44 0.10 94.16 0.01 91.39 0.00 93.03 0.61 94.26 0.00 96.50 0.00 97.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3413841310
94.53 0.09 94.46 0.29 91.43 0.04 93.22 0.19 94.28 0.02 96.50 0.00 97.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2931946607
94.61 0.08 94.52 0.07 91.56 0.13 93.45 0.23 94.36 0.08 96.50 0.00 97.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1681324670
94.69 0.08 94.52 0.00 91.81 0.25 93.45 0.00 94.41 0.05 96.50 0.00 97.43 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1088981568
94.76 0.07 94.53 0.01 92.00 0.20 93.45 0.01 94.64 0.23 96.50 0.00 97.43 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2313363782
94.82 0.06 94.53 0.00 92.00 0.00 93.45 0.00 94.64 0.00 96.50 0.00 97.80 0.38 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2729676015
94.88 0.06 94.53 0.00 92.00 0.00 93.81 0.35 94.64 0.00 96.50 0.00 97.80 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2163936305
94.94 0.06 94.53 0.01 92.03 0.03 93.93 0.13 94.65 0.02 96.68 0.17 97.80 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1015750608
94.99 0.05 94.53 0.00 92.34 0.31 93.93 0.00 94.65 0.00 96.68 0.00 97.81 0.01 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3948764293
95.04 0.05 94.53 0.00 92.37 0.03 94.03 0.09 94.65 0.00 96.85 0.17 97.81 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4042103053
95.09 0.05 94.53 0.00 92.37 0.00 94.03 0.00 94.65 0.00 96.85 0.00 98.11 0.29 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.2328136154
95.14 0.05 94.56 0.03 92.39 0.02 94.07 0.04 94.68 0.02 97.03 0.17 98.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3284576817
95.18 0.04 94.57 0.01 92.41 0.01 94.07 0.00 94.70 0.02 97.20 0.17 98.12 0.01 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.3333742713
95.21 0.04 94.58 0.01 92.42 0.01 94.07 0.01 94.71 0.01 97.38 0.17 98.13 0.01 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.3798577423
95.25 0.04 94.58 0.01 92.43 0.01 94.08 0.01 94.72 0.01 97.55 0.17 98.14 0.01 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.1018525497
95.29 0.03 94.58 0.00 92.46 0.02 94.26 0.18 94.72 0.00 97.55 0.00 98.14 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1658694610
95.32 0.03 94.58 0.00 92.63 0.17 94.27 0.01 94.72 0.00 97.55 0.00 98.14 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3606696191
95.35 0.03 94.65 0.07 92.63 0.00 94.37 0.09 94.73 0.01 97.55 0.00 98.14 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3483417585
95.37 0.03 94.65 0.00 92.65 0.02 94.37 0.00 94.73 0.01 97.55 0.00 98.27 0.13 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3043781655
95.40 0.03 94.72 0.07 92.68 0.03 94.37 0.01 94.78 0.05 97.55 0.00 98.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.2819388232
95.42 0.03 94.76 0.04 92.71 0.03 94.42 0.05 94.80 0.02 97.55 0.00 98.28 0.01 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3746803092
95.44 0.02 94.76 0.00 92.73 0.02 94.42 0.00 94.80 0.00 97.55 0.00 98.40 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.845897790
95.47 0.02 94.76 0.00 92.73 0.00 94.55 0.13 94.80 0.00 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2346328414
95.49 0.02 94.76 0.00 92.85 0.12 94.55 0.00 94.80 0.00 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3610647228
95.50 0.02 94.76 0.00 92.96 0.11 94.55 0.00 94.80 0.00 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.576864232
95.52 0.02 94.78 0.01 93.01 0.06 94.57 0.02 94.82 0.02 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.939980815
95.54 0.02 94.78 0.00 93.01 0.00 94.68 0.11 94.82 0.00 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.1184165405
95.56 0.02 94.78 0.01 93.04 0.02 94.75 0.07 94.82 0.00 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1678958313
95.57 0.02 94.78 0.00 93.07 0.04 94.79 0.04 94.85 0.02 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.525104867
95.59 0.02 94.78 0.00 93.07 0.00 94.88 0.10 94.85 0.00 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.687131276
95.61 0.02 94.78 0.00 93.09 0.01 94.88 0.00 94.85 0.00 97.55 0.00 98.48 0.08 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.4110653915
95.62 0.02 94.78 0.00 93.18 0.09 94.88 0.00 94.85 0.00 97.55 0.00 98.48 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.2425477131
95.64 0.01 94.79 0.01 93.24 0.06 94.88 0.00 94.86 0.02 97.55 0.00 98.48 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.604975400
95.65 0.01 94.79 0.00 93.31 0.07 94.88 0.00 94.87 0.01 97.55 0.00 98.48 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.296976557
95.66 0.01 94.79 0.00 93.38 0.07 94.88 0.00 94.87 0.00 97.55 0.00 98.48 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.1383920079
95.67 0.01 94.80 0.01 93.41 0.03 94.90 0.01 94.89 0.02 97.55 0.00 98.48 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3917597515
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96.08 0.01 94.94 0.00 94.01 0.01 95.38 0.00 94.99 0.00 97.55 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.361509189
96.08 0.01 94.94 0.00 94.02 0.01 95.38 0.00 94.99 0.00 97.55 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1149998089
96.08 0.01 94.94 0.00 94.02 0.00 95.39 0.01 94.99 0.00 97.55 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3839569514
96.08 0.01 94.94 0.00 94.02 0.00 95.39 0.01 94.99 0.00 97.55 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.4190887929
96.08 0.01 94.94 0.00 94.02 0.00 95.39 0.01 94.99 0.00 97.55 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.4137523344
96.08 0.01 94.94 0.00 94.02 0.00 95.39 0.01 94.99 0.00 97.55 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.545958564
96.08 0.01 94.94 0.00 94.02 0.00 95.39 0.01 94.99 0.00 97.55 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3570509049

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2997137789
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.1888526938
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3718553733
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.638018789
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1636446404
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2806156432
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3098324512
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.824555148
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.2753112951
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2036147031
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.649745155
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1722290606
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1953743654
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2337573265
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3407733184
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.3869420589
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2180071133
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2265559278
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.413497816
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1464731590
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.318653278
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1949166182
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.823766534
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.3289715597
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.1272968819
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.299207502
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.1774352295
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.485781667
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.3131549714
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.178278279
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1633038520
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1868156948
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.389599822
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1477931222
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1582361342
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3810295388
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.3775844034
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.799350251
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.22541620
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2307897109
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.1955004826
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2760819651
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.254371845
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.414528820
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.716673406
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.132953970
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2287699662
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1455090938
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.378626494
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.295979043
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.555785308
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.1051641692
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.575279436
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2001855780
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.420283822
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.955825944
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.2953778882
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.396529989
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1137002189
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4084785939
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3170678082
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1330662900
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.2574126655
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3880365843
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.938941653
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2202070248
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4052162334
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.3364472047
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.511219462
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4075844731
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2984691966
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.1322288628
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2307744818
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1842759948
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.563509791
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.644650015
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2124465112
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.1939855644
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.2335750981
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.1991640637
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.824656568
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1185449286
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.3512702604
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.547508464
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.489608505
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.1756136400
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3287211578
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.4142161698
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2422787344
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3509749809
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2465327829
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.2033137363
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.2158008594
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3814217090
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2374532154
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.3226710793
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2066080208
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.2870271734
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.776193051
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3591630764
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.4056085128
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1977840661
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3198830543
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.835839733
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.652058898
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3696875884
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.2063583840
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.2604728157
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.903118191
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3580504956
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2785036051
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3433679963
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2970279226
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.2028002585
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3644086355
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3817727570
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.141509931
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/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.1565919834
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Total test records in report: 2926
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2317201809 Sep 09 10:41:32 PM UTC 24 Sep 09 10:43:09 PM UTC 24 2133096216 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.1600953000 Sep 09 10:41:29 PM UTC 24 Sep 09 10:44:16 PM UTC 24 2237699638 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.1241410096 Sep 09 10:41:09 PM UTC 24 Sep 09 10:44:24 PM UTC 24 2484903688 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2951998220 Sep 09 10:41:32 PM UTC 24 Sep 09 10:44:50 PM UTC 24 2261661610 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.4209816887 Sep 09 10:41:30 PM UTC 24 Sep 09 10:45:15 PM UTC 24 2711353020 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.4182953009 Sep 09 10:41:59 PM UTC 24 Sep 09 10:45:41 PM UTC 24 3029332970 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.650258269 Sep 09 10:41:28 PM UTC 24 Sep 09 10:46:04 PM UTC 24 2433277650 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1043640595 Sep 09 10:41:53 PM UTC 24 Sep 09 10:46:14 PM UTC 24 3384035914 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1681324670 Sep 09 10:42:05 PM UTC 24 Sep 09 10:46:19 PM UTC 24 3893935071 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.72843555 Sep 09 10:43:41 PM UTC 24 Sep 09 10:47:15 PM UTC 24 2449233928 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.2937855451 Sep 09 10:43:09 PM UTC 24 Sep 09 10:47:18 PM UTC 24 2885819782 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.1211759066 Sep 09 10:40:07 PM UTC 24 Sep 09 10:47:33 PM UTC 24 4224202600 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.932471286 Sep 09 10:39:27 PM UTC 24 Sep 09 10:47:44 PM UTC 24 4428577938 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.488391186 Sep 09 10:41:46 PM UTC 24 Sep 09 10:48:00 PM UTC 24 3609259045 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.525104867 Sep 09 10:43:24 PM UTC 24 Sep 09 10:48:25 PM UTC 24 3006263720 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2532049534 Sep 09 10:44:32 PM UTC 24 Sep 09 10:49:08 PM UTC 24 2891384696 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.2545438082 Sep 09 10:43:41 PM UTC 24 Sep 09 10:49:09 PM UTC 24 2545844370 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.1342920385 Sep 09 10:43:39 PM UTC 24 Sep 09 10:49:12 PM UTC 24 5674259240 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.160418533 Sep 09 10:43:49 PM UTC 24 Sep 09 10:49:20 PM UTC 24 2826076344 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1015750608 Sep 09 10:40:32 PM UTC 24 Sep 09 10:49:25 PM UTC 24 5060054440 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1661041090 Sep 09 10:47:08 PM UTC 24 Sep 09 10:49:33 PM UTC 24 3588425856 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2418334480 Sep 09 10:47:07 PM UTC 24 Sep 09 10:49:44 PM UTC 24 2894508694 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.2176425665 Sep 09 10:41:29 PM UTC 24 Sep 09 10:50:20 PM UTC 24 3625299940 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3227125488 Sep 09 10:43:18 PM UTC 24 Sep 09 10:50:26 PM UTC 24 4054332043 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1557562514 Sep 09 10:45:29 PM UTC 24 Sep 09 10:50:29 PM UTC 24 2858247288 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3027898118 Sep 09 10:46:20 PM UTC 24 Sep 09 10:50:34 PM UTC 24 3682559616 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.4232971452 Sep 09 10:42:49 PM UTC 24 Sep 09 10:50:42 PM UTC 24 3309586040 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.477660668 Sep 09 10:43:25 PM UTC 24 Sep 09 10:50:50 PM UTC 24 3558365080 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.169985749 Sep 09 10:43:25 PM UTC 24 Sep 09 10:50:51 PM UTC 24 3731178392 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.57894832 Sep 09 10:40:07 PM UTC 24 Sep 09 10:50:54 PM UTC 24 5955050072 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2085591501 Sep 09 10:48:58 PM UTC 24 Sep 09 10:50:56 PM UTC 24 2645532775 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3599218274 Sep 09 10:48:46 PM UTC 24 Sep 09 10:51:05 PM UTC 24 2861915152 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3917597515 Sep 09 10:43:31 PM UTC 24 Sep 09 10:51:08 PM UTC 24 3329470712 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.914312629 Sep 09 10:43:29 PM UTC 24 Sep 09 10:51:17 PM UTC 24 4327994754 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.887514692 Sep 09 10:41:53 PM UTC 24 Sep 09 10:51:49 PM UTC 24 4353693172 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2846273073 Sep 09 10:47:09 PM UTC 24 Sep 09 10:52:28 PM UTC 24 3800530144 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3902812946 Sep 09 10:42:19 PM UTC 24 Sep 09 10:52:28 PM UTC 24 5488865374 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.3457491275 Sep 09 10:43:47 PM UTC 24 Sep 09 10:52:35 PM UTC 24 4065912024 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.2601554263 Sep 09 10:43:48 PM UTC 24 Sep 09 10:52:40 PM UTC 24 3509469288 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3939378344 Sep 09 10:42:00 PM UTC 24 Sep 09 10:52:44 PM UTC 24 4779417531 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3904529379 Sep 09 10:43:10 PM UTC 24 Sep 09 10:52:47 PM UTC 24 4765319810 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1406445299 Sep 09 10:42:20 PM UTC 24 Sep 09 10:53:30 PM UTC 24 5109570814 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.631936214 Sep 09 10:43:53 PM UTC 24 Sep 09 10:53:42 PM UTC 24 5317785164 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3121563180 Sep 09 10:43:39 PM UTC 24 Sep 09 10:53:56 PM UTC 24 6802173500 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.2640356628 Sep 09 10:41:17 PM UTC 24 Sep 09 10:54:14 PM UTC 24 5764353098 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1101921976 Sep 09 10:45:55 PM UTC 24 Sep 09 10:54:42 PM UTC 24 7121959424 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.929650134 Sep 09 10:43:29 PM UTC 24 Sep 09 10:55:22 PM UTC 24 4721677256 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3413841310 Sep 09 10:45:09 PM UTC 24 Sep 09 10:56:19 PM UTC 24 6554240200 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.363221612 Sep 09 10:52:52 PM UTC 24 Sep 09 10:56:21 PM UTC 24 3142378322 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3907265363 Sep 09 10:43:28 PM UTC 24 Sep 09 10:58:02 PM UTC 24 5749510631 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.483954049 Sep 09 10:52:43 PM UTC 24 Sep 09 10:58:07 PM UTC 24 4412398658 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.1184165405 Sep 09 10:54:53 PM UTC 24 Sep 09 10:58:57 PM UTC 24 2946515732 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.836694198 Sep 09 10:54:11 PM UTC 24 Sep 09 10:59:35 PM UTC 24 3021858069 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3284576817 Sep 09 10:52:13 PM UTC 24 Sep 09 10:59:55 PM UTC 24 4067317466 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2090013078 Sep 09 10:43:51 PM UTC 24 Sep 09 11:00:12 PM UTC 24 6059332202 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1904710470 Sep 09 10:53:15 PM UTC 24 Sep 09 11:00:20 PM UTC 24 9051528666 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.502826799 Sep 09 10:54:50 PM UTC 24 Sep 09 11:00:21 PM UTC 24 4159750156 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1645040214 Sep 09 10:52:43 PM UTC 24 Sep 09 11:00:27 PM UTC 24 7201630208 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.1766652694 Sep 09 10:48:59 PM UTC 24 Sep 09 11:00:36 PM UTC 24 7334467440 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3209132582 Sep 09 10:55:04 PM UTC 24 Sep 09 11:00:42 PM UTC 24 5358544616 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2214133217 Sep 09 10:55:03 PM UTC 24 Sep 09 11:00:48 PM UTC 24 3265941800 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.320345534 Sep 09 10:57:08 PM UTC 24 Sep 09 11:01:01 PM UTC 24 2263102360 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.1281166257 Sep 09 10:57:09 PM UTC 24 Sep 09 11:01:14 PM UTC 24 3085749723 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.3526063946 Sep 09 10:54:10 PM UTC 24 Sep 09 11:01:21 PM UTC 24 4453360742 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1644048736 Sep 09 10:43:52 PM UTC 24 Sep 09 11:01:48 PM UTC 24 7969744786 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2060789510 Sep 09 10:44:32 PM UTC 24 Sep 09 11:01:53 PM UTC 24 7727283148 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4053477299 Sep 09 10:54:47 PM UTC 24 Sep 09 11:01:55 PM UTC 24 4229890290 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.2144609438 Sep 09 10:54:19 PM UTC 24 Sep 09 11:02:08 PM UTC 24 4427001204 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.4137523344 Sep 09 10:55:37 PM UTC 24 Sep 09 11:02:12 PM UTC 24 2872239460 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.294223880 Sep 09 10:55:26 PM UTC 24 Sep 09 11:02:37 PM UTC 24 6273195372 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.3639330600 Sep 09 10:43:30 PM UTC 24 Sep 09 11:02:39 PM UTC 24 8984133980 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3523570733 Sep 09 10:59:02 PM UTC 24 Sep 09 11:03:28 PM UTC 24 3055786664 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.313203349 Sep 09 10:41:46 PM UTC 24 Sep 09 11:03:02 PM UTC 24 7444434560 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1436635817 Sep 09 10:43:55 PM UTC 24 Sep 09 11:03:43 PM UTC 24 6851050704 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.2486724488 Sep 09 10:59:05 PM UTC 24 Sep 09 11:03:48 PM UTC 24 3013248650 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1722204626 Sep 09 10:55:03 PM UTC 24 Sep 09 11:03:59 PM UTC 24 7671158672 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.453578539 Sep 09 10:54:54 PM UTC 24 Sep 09 11:04:00 PM UTC 24 18120120638 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.2633852953 Sep 09 10:59:04 PM UTC 24 Sep 09 11:04:03 PM UTC 24 3033911020 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.515126291 Sep 09 10:54:20 PM UTC 24 Sep 09 11:04:15 PM UTC 24 5339243338 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.518859312 Sep 09 10:54:02 PM UTC 24 Sep 09 11:04:17 PM UTC 24 5353576972 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1208950703 Sep 09 10:54:09 PM UTC 24 Sep 09 11:04:20 PM UTC 24 5172795834 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1678958313 Sep 09 10:41:52 PM UTC 24 Sep 09 11:04:40 PM UTC 24 8351883944 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2468366717 Sep 09 10:55:05 PM UTC 24 Sep 09 11:06:36 PM UTC 24 6072331212 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1234914487 Sep 09 10:56:05 PM UTC 24 Sep 09 11:06:48 PM UTC 24 4363600076 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1568913955 Sep 09 10:40:07 PM UTC 24 Sep 09 11:07:19 PM UTC 24 13357987367 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.2251790656 Sep 09 10:59:39 PM UTC 24 Sep 09 11:07:22 PM UTC 24 5534008688 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.700878423 Sep 09 11:03:13 PM UTC 24 Sep 09 11:07:35 PM UTC 24 2942118420 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.2650194336 Sep 09 10:42:59 PM UTC 24 Sep 09 11:07:55 PM UTC 24 7658564072 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.990105573 Sep 09 11:03:46 PM UTC 24 Sep 09 11:08:17 PM UTC 24 3199702188 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1250674215 Sep 09 11:03:48 PM UTC 24 Sep 09 11:08:37 PM UTC 24 3314817245 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.264629794 Sep 09 11:04:10 PM UTC 24 Sep 09 11:09:07 PM UTC 24 2977206296 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.2449916971 Sep 09 11:03:55 PM UTC 24 Sep 09 11:09:09 PM UTC 24 3049637430 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3839569514 Sep 09 11:02:49 PM UTC 24 Sep 09 11:09:55 PM UTC 24 3013847080 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.4068956323 Sep 09 10:55:25 PM UTC 24 Sep 09 11:09:56 PM UTC 24 5244043580 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.1282288816 Sep 09 11:06:04 PM UTC 24 Sep 09 11:10:03 PM UTC 24 2291471487 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.8919743 Sep 09 11:03:21 PM UTC 24 Sep 09 11:10:09 PM UTC 24 3474420424 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.2944143942 Sep 09 11:00:17 PM UTC 24 Sep 09 11:10:15 PM UTC 24 5616915708 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2683478510 Sep 09 10:52:42 PM UTC 24 Sep 09 11:10:30 PM UTC 24 7457120842 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2782542376 Sep 09 10:55:25 PM UTC 24 Sep 09 11:10:33 PM UTC 24 11268348254 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.1688320264 Sep 09 11:05:54 PM UTC 24 Sep 09 11:10:37 PM UTC 24 2256572560 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.4212213576 Sep 09 11:06:02 PM UTC 24 Sep 09 11:10:50 PM UTC 24 2526224940 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.1714588180 Sep 09 11:05:59 PM UTC 24 Sep 09 11:10:58 PM UTC 24 3675906450 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.2666845221 Sep 09 11:08:23 PM UTC 24 Sep 09 11:11:56 PM UTC 24 3167589200 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.2711228006 Sep 09 10:55:37 PM UTC 24 Sep 09 11:12:13 PM UTC 24 5553288820 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3473587213 Sep 09 11:04:40 PM UTC 24 Sep 09 11:12:20 PM UTC 24 4816372088 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2532074210 Sep 09 11:09:18 PM UTC 24 Sep 09 11:13:15 PM UTC 24 2516674732 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1226933643 Sep 09 11:03:53 PM UTC 24 Sep 09 11:13:24 PM UTC 24 3218047412 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.2182214977 Sep 09 11:08:34 PM UTC 24 Sep 09 11:13:29 PM UTC 24 2401918974 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2163936305 Sep 09 11:03:52 PM UTC 24 Sep 09 11:14:38 PM UTC 24 6395833595 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.610072115 Sep 09 10:42:03 PM UTC 24 Sep 09 11:14:45 PM UTC 24 21808859480 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.399283761 Sep 09 11:08:55 PM UTC 24 Sep 09 11:14:49 PM UTC 24 3207252132 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1604200923 Sep 09 11:08:38 PM UTC 24 Sep 09 11:15:14 PM UTC 24 3364894111 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3746803092 Sep 09 10:54:52 PM UTC 24 Sep 09 11:15:38 PM UTC 24 15596810590 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.2936585673 Sep 09 11:12:20 PM UTC 24 Sep 09 11:16:43 PM UTC 24 2352948075 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3174678527 Sep 09 10:53:51 PM UTC 24 Sep 09 11:16:47 PM UTC 24 13225071313 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1135476312 Sep 09 10:54:45 PM UTC 24 Sep 09 11:17:22 PM UTC 24 11496041378 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4042103053 Sep 09 11:09:58 PM UTC 24 Sep 09 11:17:49 PM UTC 24 3884811848 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3622011924 Sep 09 11:13:04 PM UTC 24 Sep 09 11:18:10 PM UTC 24 2863276986 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4260663534 Sep 09 11:11:54 PM UTC 24 Sep 09 11:19:28 PM UTC 24 4537796444 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3239867578 Sep 09 11:02:51 PM UTC 24 Sep 09 11:19:35 PM UTC 24 5373132414 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.551354972 Sep 09 11:05:54 PM UTC 24 Sep 09 11:20:47 PM UTC 24 6377884191 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1632378369 Sep 09 11:03:47 PM UTC 24 Sep 09 11:21:01 PM UTC 24 4540938910 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.897075938 Sep 09 11:09:58 PM UTC 24 Sep 09 11:21:09 PM UTC 24 8888857710 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.924492441 Sep 09 11:12:22 PM UTC 24 Sep 09 11:21:58 PM UTC 24 6817336468 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.649228526 Sep 09 11:14:20 PM UTC 24 Sep 09 11:22:03 PM UTC 24 4609524980 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.332356569 Sep 09 11:15:51 PM UTC 24 Sep 09 11:22:07 PM UTC 24 5447616170 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.875591268 Sep 09 11:14:17 PM UTC 24 Sep 09 11:22:22 PM UTC 24 5276955772 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3939480237 Sep 09 11:02:27 PM UTC 24 Sep 09 11:22:35 PM UTC 24 10779649430 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.3462052398 Sep 09 11:00:37 PM UTC 24 Sep 09 11:22:35 PM UTC 24 8351151350 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.2677098029 Sep 09 11:06:04 PM UTC 24 Sep 09 11:23:05 PM UTC 24 6285039064 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3336919641 Sep 09 10:52:42 PM UTC 24 Sep 09 11:23:12 PM UTC 24 13123767920 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.954123750 Sep 09 11:15:53 PM UTC 24 Sep 09 11:23:13 PM UTC 24 5379575488 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.428972094 Sep 09 11:12:22 PM UTC 24 Sep 09 11:23:38 PM UTC 24 5467326561 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.2785742433 Sep 09 11:20:20 PM UTC 24 Sep 09 11:23:45 PM UTC 24 2381735739 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3831009326 Sep 09 11:12:37 PM UTC 24 Sep 09 11:23:52 PM UTC 24 4232048280 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.986530424 Sep 09 10:54:12 PM UTC 24 Sep 09 11:24:12 PM UTC 24 25227229000 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1869381351 Sep 09 10:49:06 PM UTC 24 Sep 09 11:24:22 PM UTC 24 24979595192 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.2819388232 Sep 09 11:12:08 PM UTC 24 Sep 09 11:25:11 PM UTC 24 6080181180 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.647434992 Sep 09 10:41:27 PM UTC 24 Sep 09 11:25:15 PM UTC 24 11982280328 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.48236390 Sep 09 11:13:03 PM UTC 24 Sep 09 11:25:58 PM UTC 24 4486069116 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3347029032 Sep 09 11:16:18 PM UTC 24 Sep 09 11:26:01 PM UTC 24 4448473750 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3283527737 Sep 09 11:11:57 PM UTC 24 Sep 09 11:26:25 PM UTC 24 8641819608 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3881524410 Sep 09 11:15:57 PM UTC 24 Sep 09 11:26:34 PM UTC 24 4541487640 ps
T674 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.3995581215 Sep 09 11:18:50 PM UTC 24 Sep 09 11:27:07 PM UTC 24 4251262204 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2762702278 Sep 09 11:18:01 PM UTC 24 Sep 09 11:27:08 PM UTC 24 4218261658 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1347445960 Sep 09 11:20:20 PM UTC 24 Sep 09 11:27:08 PM UTC 24 2826324310 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.4272521011 Sep 09 11:24:59 PM UTC 24 Sep 09 11:27:16 PM UTC 24 2577191287 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3373462243 Sep 09 11:17:32 PM UTC 24 Sep 09 11:27:39 PM UTC 24 3870924980 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.779773861 Sep 09 11:17:33 PM UTC 24 Sep 09 11:28:08 PM UTC 24 4854268246 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.545958564 Sep 09 11:26:51 PM UTC 24 Sep 09 11:29:01 PM UTC 24 2120687400 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4127308517 Sep 09 10:52:51 PM UTC 24 Sep 09 11:29:12 PM UTC 24 25020240849 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3483417585 Sep 09 11:25:52 PM UTC 24 Sep 09 11:29:34 PM UTC 24 3209837876 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2935641620 Sep 09 11:12:09 PM UTC 24 Sep 09 11:29:47 PM UTC 24 9167493737 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2429683235 Sep 09 11:05:56 PM UTC 24 Sep 09 11:29:48 PM UTC 24 9582419176 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3844850526 Sep 09 11:12:20 PM UTC 24 Sep 09 11:29:48 PM UTC 24 6041004944 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1967632225 Sep 09 11:18:31 PM UTC 24 Sep 09 11:29:55 PM UTC 24 4159502530 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.2016988991 Sep 09 11:23:22 PM UTC 24 Sep 09 11:29:57 PM UTC 24 4848319040 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.1604261595 Sep 09 11:06:05 PM UTC 24 Sep 09 11:30:04 PM UTC 24 7194163692 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.298636626 Sep 09 11:25:05 PM UTC 24 Sep 09 11:30:49 PM UTC 24 5320370880 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2016372361 Sep 09 11:26:50 PM UTC 24 Sep 09 11:31:06 PM UTC 24 2674958654 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1487252626 Sep 09 11:23:37 PM UTC 24 Sep 09 11:31:23 PM UTC 24 7774060204 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.1883473787 Sep 09 11:24:40 PM UTC 24 Sep 09 11:31:38 PM UTC 24 3953757464 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1614457088 Sep 09 11:21:29 PM UTC 24 Sep 09 11:31:47 PM UTC 24 4708001750 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3071546281 Sep 09 11:25:06 PM UTC 24 Sep 09 11:31:49 PM UTC 24 5339002736 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2080902541 Sep 09 11:28:32 PM UTC 24 Sep 09 11:31:51 PM UTC 24 2723495288 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3522928696 Sep 09 11:25:06 PM UTC 24 Sep 09 11:31:58 PM UTC 24 3821148012 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2588726994 Sep 09 11:27:16 PM UTC 24 Sep 09 11:32:01 PM UTC 24 3069547671 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2505071185 Sep 09 11:15:53 PM UTC 24 Sep 09 11:32:36 PM UTC 24 10768002196 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.2432968117 Sep 09 11:27:17 PM UTC 24 Sep 09 11:33:01 PM UTC 24 2856743274 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.2366791570 Sep 09 11:02:52 PM UTC 24 Sep 09 11:33:07 PM UTC 24 9129640968 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4153440088 Sep 09 11:25:06 PM UTC 24 Sep 09 11:33:25 PM UTC 24 5855922656 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.1845872034 Sep 09 11:28:32 PM UTC 24 Sep 09 11:33:30 PM UTC 24 3342555492 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2432012627 Sep 09 11:29:56 PM UTC 24 Sep 09 11:33:51 PM UTC 24 3222887789 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2371774520 Sep 09 11:25:07 PM UTC 24 Sep 09 11:33:55 PM UTC 24 5643551833 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.684295099 Sep 09 11:25:02 PM UTC 24 Sep 09 11:34:09 PM UTC 24 5245204072 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.936361420 Sep 09 11:29:55 PM UTC 24 Sep 09 11:34:15 PM UTC 24 2674842281 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1658694610 Sep 09 11:04:50 PM UTC 24 Sep 09 11:34:40 PM UTC 24 7647335768 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2275152754 Sep 09 11:03:36 PM UTC 24 Sep 09 11:35:19 PM UTC 24 8626132590 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2287187359 Sep 09 11:31:09 PM UTC 24 Sep 09 11:35:40 PM UTC 24 3851825231 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.2641393814 Sep 09 11:28:31 PM UTC 24 Sep 09 11:37:09 PM UTC 24 5628055474 ps
T675 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.3711952062 Sep 09 11:23:55 PM UTC 24 Sep 09 11:37:22 PM UTC 24 8102760860 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.3401501040 Sep 09 11:14:20 PM UTC 24 Sep 09 11:37:26 PM UTC 24 11387186646 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2726936299 Sep 09 11:28:30 PM UTC 24 Sep 09 11:37:28 PM UTC 24 4425206902 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1681880981 Sep 09 11:07:32 PM UTC 24 Sep 09 11:37:58 PM UTC 24 9439810704 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.1053813358 Sep 09 11:35:27 PM UTC 24 Sep 09 11:38:32 PM UTC 24 2055072624 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1561530077 Sep 09 11:05:59 PM UTC 24 Sep 09 11:39:13 PM UTC 24 11390350764 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.1336661186 Sep 09 11:34:20 PM UTC 24 Sep 09 11:39:50 PM UTC 24 4216464846 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.89217200 Sep 09 11:31:11 PM UTC 24 Sep 09 11:40:09 PM UTC 24 4392778706 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.956965357 Sep 09 11:05:58 PM UTC 24 Sep 09 11:40:51 PM UTC 24 11482251794 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3012151301 Sep 09 11:32:06 PM UTC 24 Sep 09 11:41:10 PM UTC 24 6378826250 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.1915358009 Sep 09 11:25:52 PM UTC 24 Sep 09 11:44:24 PM UTC 24 12489195688 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.663191475 Sep 09 10:54:51 PM UTC 24 Sep 09 11:45:55 PM UTC 24 20479656333 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2887267213 Sep 09 11:12:23 PM UTC 24 Sep 09 11:46:47 PM UTC 24 25211968950 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3165966197 Sep 09 11:28:31 PM UTC 24 Sep 09 11:46:59 PM UTC 24 8299509079 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.3190051820 Sep 09 11:21:35 PM UTC 24 Sep 09 11:47:25 PM UTC 24 13765845495 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.746173287 Sep 09 11:07:28 PM UTC 24 Sep 09 11:47:46 PM UTC 24 13093021804 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4130643959 Sep 09 11:23:27 PM UTC 24 Sep 09 11:49:14 PM UTC 24 27260117800 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.3172710396 Sep 09 11:24:59 PM UTC 24 Sep 09 11:51:32 PM UTC 24 15941086003 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.4031226689 Sep 09 11:35:42 PM UTC 24 Sep 09 11:52:32 PM UTC 24 5217943212 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1154172586 Sep 09 11:21:28 PM UTC 24 Sep 09 11:53:25 PM UTC 24 18657493718 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3694627042 Sep 09 11:35:01 PM UTC 24 Sep 09 11:57:38 PM UTC 24 5821615240 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3703308820 Sep 09 11:24:54 PM UTC 24 Sep 09 11:58:50 PM UTC 24 25933979240 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.3554549052 Sep 09 10:42:59 PM UTC 24 Sep 10 12:02:10 AM UTC 24 18943957992 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.3368106815 Sep 09 11:03:52 PM UTC 24 Sep 10 12:03:09 AM UTC 24 15276692832 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.3853913338 Sep 09 11:30:31 PM UTC 24 Sep 10 12:03:40 AM UTC 24 26123997475 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2411896472 Sep 09 11:30:20 PM UTC 24 Sep 10 12:03:59 AM UTC 24 12037318669 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3947214919 Sep 09 10:55:36 PM UTC 24 Sep 10 12:04:41 AM UTC 24 19371938490 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2642917927 Sep 09 10:55:32 PM UTC 24 Sep 10 12:07:41 AM UTC 24 16615449028 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2211569267 Sep 09 10:41:39 PM UTC 24 Sep 10 12:11:15 AM UTC 24 43648154125 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.2743140116 Sep 09 11:08:34 PM UTC 24 Sep 10 12:13:10 AM UTC 24 14285281520 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.662574988 Sep 10 12:11:57 AM UTC 24 Sep 10 12:13:43 AM UTC 24 2661582032 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.4152611233 Sep 10 12:13:53 AM UTC 24 Sep 10 12:20:56 AM UTC 24 5930042935 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2563182869 Sep 09 10:49:05 PM UTC 24 Sep 10 12:25:15 AM UTC 24 47406273366 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.261139965 Sep 09 11:36:24 PM UTC 24 Sep 10 12:25:18 AM UTC 24 11941412168 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1788997611 Sep 09 10:45:10 PM UTC 24 Sep 10 12:25:25 AM UTC 24 26808961910 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1383818823 Sep 09 11:41:19 PM UTC 24 Sep 10 12:29:28 AM UTC 24 11654140162 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2931946607 Sep 09 11:54:03 PM UTC 24 Sep 10 12:30:08 AM UTC 24 11668957232 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.1689840204 Sep 10 12:26:20 AM UTC 24 Sep 10 12:31:41 AM UTC 24 2570211600 ps
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