Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	147736	1			T96	4		T97	7		T98	44
values[2]	9558	1			T97	1		T547	2		T437	6
values[3]	3605	1			T829	56		T534	57		T551	3
values[4]	2031	1			T829	38		T534	25		T551	11
values[5]	1342	1			T829	34		T534	8		T551	8
values[6]	873	1			T829	24		T534	5		T551	4
values[7]	640	1			T829	31		T551	5		T796	4
values[8]	541	1			T829	9		T551	7		T796	2
values[9]	461	1			T551	4		T796	2		T780	2
values[10]	382	1			T551	8		T796	1		T780	1
values[11]	475	1			T551	28		T796	3		T780	3
values[12]	411	1			T551	19		T796	1		T780	4
values[13]	410	1			T551	8		T796	1		T780	4
values[14]	375	1			T551	4		T796	3		T780	1
values[15]	375	1			T551	3		T796	1		T780	1
values[16]	356	1			T551	5		T796	3		T780	3
values[17]	438	1			T551	7		T796	3		T780	6
values[18]	356	1			T551	4		T796	2		T780	8
values[19]	325	1			T551	4		T796	4		T780	5
values[20]	381	1			T551	3		T796	3		T500	6
values[21]	301	1			T551	4		T796	4		T500	12
values[22]	325	1			T551	7		T796	2		T500	4
values[23]	354	1			T551	16		T796	2		T500	12
values[24]	345	1			T551	15		T796	1		T500	10
values[25]	345	1			T551	11		T796	5		T500	11
values[26]	331	1			T551	4		T796	1		T500	5
values[27]	348	1			T551	2		T796	3		T500	13
values[28]	321	1			T551	3		T796	2		T500	3
values[29]	344	1			T551	3		T796	3		T500	12
values[30]	306	1			T551	8		T796	12		T500	6
values[31]	361	1			T551	9		T796	6		T500	13
values[32]	337	1			T551	10		T796	6		T500	10
values[33]	307	1			T551	3		T796	1		T500	8
values[34]	373	1			T551	7		T796	2		T500	6
values[35]	362	1			T551	15		T796	1		T500	4
values[36]	285	1			T551	5		T796	1		T500	4
values[37]	289	1			T551	4		T796	3		T500	5
values[38]	369	1			T551	3		T796	5		T500	8
values[39]	329	1			T551	7		T796	6		T500	6
values[40]	363	1			T551	3		T796	6		T500	12
values[41]	354	1			T551	4		T796	6		T500	7
values[42]	298	1			T551	9		T796	13		T500	5
values[43]	352	1			T551	5		T796	8		T500	5
values[44]	341	1			T551	3		T796	3		T500	14
values[45]	274	1			T551	4		T796	2		T500	9
values[46]	291	1			T551	7		T796	1		T500	7
values[47]	265	1			T551	6		T796	3		T500	6
values[48]	305	1			T551	3		T796	5		T500	12
values[49]	325	1			T551	2		T796	3		T500	14
values[50]	274	1			T551	5		T796	1		T500	3
values[51]	284	1			T551	2		T796	2		T500	7
values[52]	280	1			T551	5		T796	3		T500	8
values[53]	259	1			T551	14		T796	1		T500	9
values[54]	256	1			T551	3		T796	3		T500	7
values[55]	251	1			T551	5		T796	5		T500	8
values[56]	275	1			T551	2		T796	1		T500	4
values[57]	256	1			T551	2		T796	3		T500	19
values[58]	255	1			T551	5		T796	2		T500	6
values[59]	268	1			T551	3		T796	2		T500	4
values[60]	215	1			T551	3		T796	2		T500	4
values[61]	232	1			T551	11		T796	1		T500	6
values[62]	217	1			T551	6		T796	3		T500	3
values[63]	254	1			T551	13		T796	2		T500	5
values[64]	266	1			T551	9		T796	4		T500	8
values[65]	208	1			T551	9		T796	2		T500	9
values[66]	173	1			T551	11		T796	2		T500	7
values[67]	137	1			T551	9		T796	1		T500	3
values[68]	130	1			T551	6		T796	1		T500	5
values[69]	118	1			T551	4		T796	4		T811	16
values[70]	136	1			T551	8		T796	1		T811	9
values[71]	114	1			T551	11		T796	1		T811	8
values[72]	94	1			T551	14		T796	2		T811	5
values[73]	95	1			T551	12		T796	1		T811	5
values[74]	100	1			T551	13		T796	1		T811	9
values[75]	89	1			T551	11		T796	3		T811	6
values[76]	87	1			T551	17		T796	2		T811	13
values[77]	79	1			T551	12		T796	2		T811	4
values[78]	66	1			T551	9		T796	1		T811	1
values[79]	81	1			T551	17		T796	4		T798	1
values[80]	85	1			T551	16		T796	1		T798	1
values[81]	77	1			T551	17		T796	1		T798	1
values[82]	73	1			T551	9		T796	1		T798	1
values[83]	74	1			T551	16		T796	3		T798	1
values[84]	82	1			T551	13		T796	4		T798	1
values[85]	66	1			T551	7		T796	4		T798	1
values[86]	73	1			T551	5		T796	4		T798	1
values[87]	82	1			T551	11		T796	6		T798	1
values[88]	71	1			T551	6		T796	10		T798	1
values[89]	84	1			T551	10		T796	13		T798	1
values[90]	78	1			T551	7		T796	6		T798	1
values[91]	71	1			T551	15		T796	3		T798	1
values[92]	82	1			T551	28		T796	6		T798	1
values[93]	84	1			T551	9		T796	11		T798	1
values[94]	107	1			T551	19		T796	8		T798	1
values[95]	88	1			T551	8		T796	8		T798	1
values[96]	81	1			T551	4		T796	8		T798	1
values[97]	58	1			T551	4		T796	5		T798	1
values[98]	84	1			T551	11		T796	13		T798	1
values[99]	91	1			T551	18		T796	7		T798	1
values[100]	64	1			T551	10		T796	2		T798	1
values[101]	59	1			T551	3		T796	4		T798	1
values[102]	48	1			T551	5		T796	2		T798	2
values[103]	58	1			T551	1		T796	3		T798	3
values[104]	79	1			T551	5		T796	2		T798	7
values[105]	65	1			T551	4		T796	4		T798	2
values[106]	53	1			T551	1		T796	5		T798	1
values[107]	54	1			T551	4		T796	4		T798	3
values[108]	51	1			T551	2		T796	3		T798	3
values[109]	51	1			T551	6		T796	6		T798	2
values[110]	47	1			T551	4		T796	3		T798	2
values[111]	53	1			T551	4		T796	1		T798	5
values[112]	45	1			T551	6		T796	3		T798	2
values[113]	50	1			T551	4		T796	7		T798	2
values[114]	59	1			T551	1		T796	9		T798	3
values[115]	56	1			T551	2		T796	4		T798	1
values[116]	53	1			T551	5		T796	6		T798	1
values[117]	50	1			T551	4		T796	4		T798	1
values[118]	65	1			T551	4		T796	3		T798	1
values[119]	51	1			T551	1		T796	2		T798	3
values[120]	60	1			T551	7		T796	7		T798	1
values[121]	58	1			T551	1		T796	3		T798	1
values[122]	48	1			T796	1		T798	3		T516	3
values[123]	49	1			T796	2		T798	1		T516	1
values[124]	54	1			T796	3		T798	2		T516	1
values[125]	61	1			T796	19		T798	2		T516	3
values[126]	93	1			T796	21		T798	3		T516	1
values[127]	771	1			T796	20		T798	35		T516	25
values[128]	6650	1			T796	6		T798	298		T516	270