Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	169939	1			T96	4		T97	8		T98	39
values[2]	3909	1			T102	2		T547	1		T437	2
values[3]	1835	1			T547	1		T575	2		T567	1
values[4]	1563	1			T575	2		T797	1		T571	27
values[5]	1219	1			T575	2		T797	1		T571	31
values[6]	1208	1			T575	2		T797	1		T571	30
values[7]	1113	1			T575	2		T797	1		T571	35
values[8]	931	1			T575	1		T797	1		T571	33
values[9]	804	1			T575	1		T797	1		T571	20
values[10]	752	1			T575	1		T797	1		T571	2
values[11]	600	1			T575	3		T797	1		T803	10
values[12]	528	1			T575	2		T797	1		T803	13
values[13]	409	1			T575	2		T797	1		T803	25
values[14]	401	1			T575	3		T797	1		T803	34
values[15]	389	1			T575	3		T797	1		T803	33
values[16]	306	1			T575	1		T797	1		T803	20
values[17]	336	1			T575	2		T797	1		T803	19
values[18]	385	1			T575	1		T797	1		T803	44
values[19]	327	1			T575	1		T797	1		T803	23
values[20]	249	1			T575	4		T797	1		T803	6
values[21]	230	1			T575	2		T797	1		T803	1
values[22]	249	1			T575	2		T797	1		T460	2
values[23]	231	1			T575	2		T797	1		T460	2
values[24]	285	1			T575	3		T797	1		T460	2
values[25]	280	1			T575	1		T797	1		T460	2
values[26]	260	1			T575	2		T797	1		T460	2
values[27]	244	1			T575	1		T797	1		T460	2
values[28]	258	1			T575	2		T797	1		T460	2
values[29]	226	1			T575	2		T797	1		T460	2
values[30]	212	1			T575	2		T797	1		T460	2
values[31]	200	1			T575	2		T797	1		T460	2
values[32]	177	1			T575	2		T797	1		T460	2
values[33]	195	1			T575	2		T797	1		T460	2
values[34]	167	1			T575	3		T797	1		T460	2
values[35]	146	1			T575	4		T797	1		T460	2
values[36]	118	1			T575	2		T797	1		T460	2
values[37]	94	1			T575	1		T797	1		T460	2
values[38]	88	1			T575	3		T797	1		T460	2
values[39]	87	1			T575	3		T797	1		T460	2
values[40]	98	1			T575	1		T797	1		T460	2
values[41]	74	1			T575	1		T797	1		T460	2
values[42]	73	1			T575	2		T797	1		T460	2
values[43]	74	1			T575	3		T797	1		T460	2
values[44]	62	1			T575	4		T797	1		T460	2
values[45]	62	1			T575	6		T797	1		T460	2
values[46]	62	1			T575	7		T797	1		T460	2
values[47]	73	1			T575	6		T797	1		T460	2
values[48]	87	1			T575	4		T797	1		T460	2
values[49]	74	1			T575	2		T797	1		T460	2
values[50]	81	1			T575	1		T797	1		T460	2
values[51]	73	1			T575	4		T797	1		T460	2
values[52]	66	1			T575	2		T797	1		T460	2
values[53]	77	1			T575	3		T797	1		T460	2
values[54]	95	1			T575	3		T797	1		T460	2
values[55]	93	1			T575	4		T797	1		T460	2
values[56]	68	1			T575	2		T797	1		T460	2
values[57]	56	1			T575	2		T797	1		T460	2
values[58]	65	1			T575	4		T797	1		T460	2
values[59]	56	1			T575	1		T797	1		T460	2
values[60]	55	1			T575	2		T797	1		T460	2
values[61]	64	1			T575	4		T797	1		T460	2
values[62]	69	1			T575	3		T797	1		T460	2
values[63]	59	1			T575	1		T797	1		T460	2
values[64]	62	1			T575	2		T797	1		T460	2
values[65]	54	1			T575	2		T797	1		T460	2
values[66]	73	1			T575	2		T797	1		T460	2
values[67]	81	1			T575	6		T797	1		T460	2
values[68]	92	1			T575	6		T797	1		T460	2
values[69]	87	1			T575	2		T797	2		T460	2
values[70]	75	1			T575	2		T797	1		T460	2
values[71]	72	1			T575	1		T797	1		T460	2
values[72]	78	1			T575	2		T797	1		T460	2
values[73]	67	1			T575	1		T797	1		T460	2
values[74]	53	1			T575	1		T797	1		T460	2
values[75]	70	1			T575	4		T797	1		T460	2
values[76]	70	1			T575	8		T797	1		T460	2
values[77]	62	1			T575	3		T797	1		T460	2
values[78]	56	1			T575	2		T797	1		T460	2
values[79]	50	1			T575	4		T797	1		T460	2
values[80]	62	1			T575	9		T797	1		T460	2
values[81]	60	1			T575	4		T797	1		T460	2
values[82]	58	1			T575	2		T797	1		T460	2
values[83]	53	1			T575	2		T797	1		T460	2
values[84]	62	1			T575	1		T797	1		T460	2
values[85]	65	1			T575	1		T797	1		T460	3
values[86]	69	1			T575	4		T797	1		T460	2
values[87]	60	1			T575	3		T797	1		T460	2
values[88]	63	1			T575	5		T797	1		T460	2
values[89]	61	1			T575	4		T797	1		T460	2
values[90]	57	1			T575	1		T797	1		T460	2
values[91]	66	1			T575	3		T797	1		T460	2
values[92]	68	1			T575	1		T797	1		T460	2
values[93]	93	1			T575	3		T797	1		T460	4
values[94]	97	1			T575	3		T797	1		T460	2
values[95]	72	1			T575	1		T797	1		T460	2
values[96]	68	1			T575	2		T797	1		T460	2
values[97]	63	1			T575	3		T797	1		T460	3
values[98]	64	1			T575	2		T797	1		T460	2
values[99]	76	1			T575	1		T797	1		T460	3
values[100]	82	1			T575	4		T797	1		T460	3
values[101]	76	1			T575	1		T797	1		T460	3
values[102]	91	1			T575	2		T797	1		T460	4
values[103]	103	1			T575	4		T797	1		T460	2
values[104]	75	1			T575	1		T797	1		T460	3
values[105]	88	1			T575	1		T797	1		T460	6
values[106]	66	1			T575	5		T797	1		T460	3
values[107]	82	1			T575	7		T797	1		T460	2
values[108]	90	1			T575	8		T797	1		T460	4
values[109]	92	1			T575	3		T797	1		T460	3
values[110]	76	1			T575	5		T797	1		T460	3
values[111]	85	1			T575	9		T797	1		T460	2
values[112]	122	1			T575	11		T797	3		T460	3
values[113]	130	1			T575	13		T797	3		T460	3
values[114]	101	1			T575	12		T797	4		T460	2
values[115]	107	1			T575	17		T797	4		T460	2
values[116]	96	1			T575	8		T797	2		T460	2
values[117]	95	1			T575	6		T797	1		T460	4
values[118]	99	1			T575	7		T797	4		T460	3
values[119]	87	1			T575	8		T797	6		T460	2
values[120]	103	1			T575	6		T797	2		T460	3
values[121]	107	1			T575	11		T797	1		T460	4
values[122]	111	1			T575	3		T797	1		T460	4
values[123]	130	1			T575	7		T797	2		T460	9
values[124]	209	1			T575	9		T797	5		T460	5
values[125]	355	1			T575	21		T797	4		T460	2
values[126]	797	1			T575	30		T797	9		T460	21
values[127]	3097	1			T575	11		T797	95		T460	208
values[128]	5701	1			T575	3		T797	181		T460	494