Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
128967 | 
1 | 
 | 
 | 
T96 | 
9 | 
 | 
T97 | 
7 | 
 | 
T98 | 
24 | 
| auto[1] | 
72072 | 
1 | 
 | 
 | 
T97 | 
1 | 
 | 
T98 | 
17 | 
 | 
T102 | 
2 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
50406 | 
1 | 
 | 
 | 
T96 | 
4 | 
 | 
T97 | 
2 | 
 | 
T98 | 
9 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
141746 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
59293 | 
1 | 
 | 
 | 
T96 | 
1 | 
 | 
T97 | 
3 | 
 | 
T98 | 
15 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15516 | 
1 | 
 | 
 | 
T98 | 
3 | 
 | 
T102 | 
1 | 
 | 
T155 | 
1 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
126805 | 
1 | 
 | 
 | 
T96 | 
2 | 
 | 
T97 | 
3 | 
 | 
T98 | 
49 | 
| auto[1] | 
71060 | 
1 | 
 | 
 | 
T96 | 
1 | 
 | 
T97 | 
6 | 
 | 
T98 | 
6 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
48192 | 
1 | 
 | 
 | 
T97 | 
5 | 
 | 
T98 | 
21 | 
 | 
T155 | 
9 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
140212 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
57653 | 
1 | 
 | 
 | 
T96 | 
1 | 
 | 
T97 | 
2 | 
 | 
T98 | 
14 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
14730 | 
1 | 
 | 
 | 
T97 | 
1 | 
 | 
T98 | 
3 | 
 | 
T155 | 
3 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
135633 | 
1 | 
 | 
 | 
T96 | 
2 | 
 | 
T97 | 
4 | 
 | 
T98 | 
15 | 
| auto[1] | 
71957 | 
1 | 
 | 
 | 
T96 | 
1 | 
 | 
T97 | 
1 | 
 | 
T98 | 
34 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
52149 | 
1 | 
 | 
 | 
T98 | 
14 | 
 | 
T155 | 
3 | 
 | 
T230 | 
5 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
145653 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
61937 | 
1 | 
 | 
 | 
T96 | 
1 | 
 | 
T97 | 
3 | 
 | 
T98 | 
18 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
16383 | 
1 | 
 | 
 | 
T98 | 
5 | 
 | 
T230 | 
1 | 
 | 
T437 | 
10 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
128058 | 
1 | 
 | 
 | 
T96 | 
2 | 
 | 
T97 | 
8 | 
 | 
T98 | 
20 | 
| auto[1] | 
68462 | 
1 | 
 | 
 | 
T96 | 
2 | 
 | 
T98 | 
24 | 
 | 
T155 | 
1 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
49653 | 
1 | 
 | 
 | 
T96 | 
3 | 
 | 
T97 | 
3 | 
 | 
T98 | 
15 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
138505 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
58015 | 
1 | 
 | 
 | 
T96 | 
3 | 
 | 
T97 | 
4 | 
 | 
T98 | 
11 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15384 | 
1 | 
 | 
 | 
T96 | 
3 | 
 | 
T97 | 
1 | 
 | 
T98 | 
6 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
130823 | 
1 | 
 | 
 | 
T96 | 
2 | 
 | 
T97 | 
4 | 
 | 
T98 | 
29 | 
| auto[1] | 
72394 | 
1 | 
 | 
 | 
T96 | 
1 | 
 | 
T98 | 
7 | 
 | 
T102 | 
5 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
52043 | 
1 | 
 | 
 | 
T96 | 
1 | 
 | 
T97 | 
1 | 
 | 
T98 | 
8 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
141530 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
61687 | 
1 | 
 | 
 | 
T96 | 
2 | 
 | 
T97 | 
1 | 
 | 
T98 | 
7 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
16411 | 
1 | 
 | 
 | 
T98 | 
1 | 
 | 
T155 | 
1 | 
 | 
T230 | 
1 |