Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	511	1			T533	2		T534	1		T575	2
all_values[1]	456	1			T533	3		T829	1		T657	1
all_values[2]	517	1			T544	1		T533	2		T575	4
all_values[3]	514	1			T533	5		T657	2		T575	1
all_values[4]	456	1			T544	2		T533	2		T657	7
all_values[5]	514	1			T631	1		T533	4		T534	3
all_values[6]	511	1			T536	1		T544	1		T533	2
all_values[7]	507	1			T544	2		T533	3		T657	3
all_values[8]	496	1			T544	2		T533	1		T657	4
all_values[9]	477	1			T533	1		T657	1		T575	3
all_values[10]	474	1			T544	1		T631	1		T533	3
all_values[11]	489	1			T544	2		T533	2		T534	1
all_values[12]	497	1			T536	1		T657	2		T575	1
all_values[13]	510	1			T544	1		T533	6		T575	2
all_values[14]	487	1			T544	1		T631	1		T533	2
all_values[15]	447	1			T536	1		T544	1		T631	1
all_values[16]	509	1			T544	1		T533	3		T534	1
all_values[17]	449	1			T544	3		T533	1		T534	1
all_values[18]	491	1			T544	3		T533	4		T843	1
all_values[19]	506	1			T631	2		T533	3		T534	1
all_values[20]	523	1			T544	1		T631	1		T533	4
all_values[21]	500	1			T544	2		T533	4		T657	1
all_values[22]	455	1			T544	1		T657	3		T575	2
all_values[23]	505	1			T544	2		T631	1		T533	2
all_values[24]	487	1			T533	2		T657	2		T575	1
all_values[25]	514	1			T533	5		T843	1		T657	1
all_values[26]	495	1			T533	3		T829	1		T534	1
all_values[27]	505	1			T544	2		T631	1		T533	2
all_values[28]	476	1			T544	2		T533	1		T575	4
all_values[29]	528	1			T533	1		T657	3		T575	2
all_values[30]	516	1			T544	1		T533	4		T829	1
all_values[31]	484	1			T631	1		T533	1		T657	1
all_values[32]	468	1			T536	1		T533	4		T843	1
all_values[33]	493	1			T544	1		T533	2		T534	1
all_values[34]	438	1			T544	1		T533	3		T575	2
all_values[35]	467	1			T544	2		T533	2		T657	3
all_values[36]	482	1			T544	2		T631	1		T657	4
all_values[37]	501	1			T533	4		T534	1		T657	1
all_values[38]	505	1			T544	2		T533	4		T534	1
all_values[39]	482	1			T533	1		T657	2		T575	3
all_values[40]	516	1			T544	1		T533	2		T657	4
all_values[41]	496	1			T536	1		T544	1		T533	4
all_values[42]	519	1			T544	3		T533	2		T657	2
all_values[43]	453	1			T544	5		T533	2		T534	1
all_values[44]	476	1			T544	2		T631	1		T533	1
all_values[45]	496	1			T536	1		T544	1		T533	1
all_values[46]	525	1			T536	1		T544	2		T631	1
all_values[47]	459	1			T533	4		T657	2		T575	1
all_values[48]	463	1			T544	1		T533	4		T657	3
all_values[49]	449	1			T533	3		T534	1		T657	4