Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3572	1			T453	1		T452	2		T544	10
all_values[1]	3627	1			T453	1		T544	7		T533	20
all_values[2]	3570	1			T453	1		T452	1		T544	8
all_values[3]	3596	1			T453	3		T452	1		T544	9
all_values[4]	3693	1			T453	2		T452	1		T544	13
all_values[5]	3626	1			T453	1		T452	1		T544	7
all_values[6]	3575	1			T453	3		T452	1		T544	12
all_values[7]	3599	1			T453	1		T544	11		T533	9
all_values[8]	3649	1			T453	1		T537	2		T544	5
all_values[9]	3668	1			T452	2		T544	10		T533	27
all_values[10]	3560	1			T452	1		T537	1		T544	11
all_values[11]	3595	1			T453	2		T544	9		T533	11
all_values[12]	3643	1			T453	1		T452	1		T544	11
all_values[13]	3538	1			T453	2		T452	2		T544	13
all_values[14]	3448	1			T453	2		T452	2		T537	1
all_values[15]	3670	1			T452	1		T537	1		T544	11
all_values[16]	3631	1			T544	18		T533	15		T657	25
all_values[17]	3630	1			T453	2		T452	1		T544	11
all_values[18]	3623	1			T453	2		T544	9		T533	25
all_values[19]	3508	1			T544	14		T533	15		T657	37
all_values[20]	3616	1			T453	2		T452	2		T537	1
all_values[21]	3599	1			T453	2		T452	1		T537	2
all_values[22]	3674	1			T453	2		T452	1		T544	6
all_values[23]	3538	1			T453	2		T452	2		T544	8
all_values[24]	3479	1			T452	1		T537	2		T544	7
all_values[25]	3604	1			T453	1		T452	1		T544	11
all_values[26]	3627	1			T453	2		T452	1		T544	10
all_values[27]	3577	1			T453	2		T537	1		T544	7
all_values[28]	3680	1			T453	2		T452	3		T544	10
all_values[29]	3587	1			T453	2		T452	1		T544	8
all_values[30]	3623	1			T453	1		T452	1		T537	2
all_values[31]	3604	1			T453	1		T452	2		T544	22
all_values[32]	3573	1			T453	1		T544	11		T533	26
all_values[33]	3632	1			T453	1		T544	11		T533	15
all_values[34]	3630	1			T452	2		T544	9		T533	18
all_values[35]	3624	1			T453	1		T452	1		T544	14
all_values[36]	3671	1			T453	2		T544	9		T533	16
all_values[37]	3529	1			T452	2		T537	1		T544	11
all_values[38]	3594	1			T453	1		T452	2		T544	10
all_values[39]	3558	1			T453	1		T537	2		T544	9
all_values[40]	3634	1			T453	2		T537	1		T544	17
all_values[41]	3619	1			T453	1		T452	1		T544	8
all_values[42]	3623	1			T452	1		T537	1		T544	14
all_values[43]	3604	1			T453	2		T452	2		T537	1
all_values[44]	3538	1			T453	5		T452	4		T537	1
all_values[45]	3601	1			T453	2		T452	3		T544	8
all_values[46]	3571	1			T453	1		T537	2		T544	13
all_values[47]	3613	1			T453	3		T537	1		T544	17
all_values[48]	3485	1			T453	2		T544	18		T533	12
all_values[49]	3616	1			T453	1		T452	2		T544	9
all_values[50]	3562	1			T453	1		T452	3		T544	9
all_values[51]	3563	1			T453	2		T452	4		T537	1
all_values[52]	3576	1			T453	3		T452	1		T544	9
all_values[53]	3661	1			T453	4		T452	2		T544	6
all_values[54]	3706	1			T452	2		T544	6		T533	20
all_values[55]	3567	1			T453	1		T452	2		T537	1
all_values[56]	3703	1			T452	1		T537	2		T544	14
all_values[57]	3586	1			T453	2		T537	2		T544	10
all_values[58]	3604	1			T544	17		T533	30		T657	27
all_values[59]	3577	1			T452	1		T537	2		T544	7
all_values[60]	3582	1			T453	4		T452	1		T537	1
all_values[61]	3530	1			T453	3		T452	1		T537	2
all_values[62]	3550	1			T452	2		T544	12		T533	14
all_values[63]	3686	1			T453	6		T452	1		T544	8