Go
back
67 always_ff @(posedge clk_i or negedge rst_ni) begin
68 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
69 1/1 err_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
71 1/1 err_q <= 1'b1;
Tests: T373 T374 T375
72 end
MISSING_ELSE
73 end
74
75 // integrity error output is permanent and should be used for alert generation
76 // register errors are transactional
77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
78
79 // outgoing integrity generation
80 tlul_pkg::tl_d2h_t tl_o_pre;
81 tlul_rsp_intg_gen #(
82 .EnableRspIntgGen(1),
83 .EnableDataIntgGen(1)
84 ) u_rsp_intg_gen (
85 .tl_i(tl_o_pre),
86 .tl_o(tl_o)
87 );
88
89 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
90 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
91
92 tlul_adapter_reg #(
93 .RegAw(AW),
94 .RegDw(DW),
95 .EnableDataIntgGen(0)
96 ) u_reg_if (
97 .clk_i (clk_i),
98 .rst_ni (rst_ni),
99
100 .tl_i (tl_reg_h2d),
101 .tl_o (tl_reg_d2h),
102
103 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104 .intg_error_o(),
105
106 .we_o (reg_we),
107 .re_o (reg_re),
108 .addr_o (reg_addr),
109 .wdata_o (reg_wdata),
110 .be_o (reg_be),
111 .busy_i (reg_busy),
112 .rdata_i (reg_rdata),
113 .error_i (reg_error)
114 );
115
116 // cdc oversampling signals
117
118 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
119 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T1 T2 T3
120
121 // Define SW related signals
122 // Format: <reg>_<field>_{wd|we|qs}
123 // or <reg>_{wd|we|qs} if field == 1 or 0
124 logic intr_state_we;
125 logic intr_state_io_status_change_qs;
126 logic intr_state_io_status_change_wd;
127 logic intr_state_init_status_change_qs;
128 logic intr_state_init_status_change_wd;
129 logic intr_enable_we;
130 logic intr_enable_io_status_change_qs;
131 logic intr_enable_io_status_change_wd;
132 logic intr_enable_init_status_change_qs;
133 logic intr_enable_init_status_change_wd;
134 logic intr_test_we;
135 logic intr_test_io_status_change_wd;
136 logic intr_test_init_status_change_wd;
137 logic alert_test_we;
138 logic alert_test_recov_alert_wd;
139 logic alert_test_fatal_alert_wd;
140 logic cfg_regwen_we;
141 logic cfg_regwen_qs;
142 logic cfg_regwen_wd;
143 logic alert_trig_we;
144 logic alert_trig_val_0_qs;
145 logic alert_trig_val_0_wd;
146 logic alert_trig_val_1_qs;
147 logic alert_trig_val_1_wd;
148 logic alert_trig_val_2_qs;
149 logic alert_trig_val_2_wd;
150 logic alert_trig_val_3_qs;
151 logic alert_trig_val_3_wd;
152 logic alert_trig_val_4_qs;
153 logic alert_trig_val_4_wd;
154 logic alert_trig_val_5_qs;
155 logic alert_trig_val_5_wd;
156 logic alert_trig_val_6_qs;
157 logic alert_trig_val_6_wd;
158 logic alert_trig_val_7_qs;
159 logic alert_trig_val_7_wd;
160 logic alert_trig_val_8_qs;
161 logic alert_trig_val_8_wd;
162 logic alert_trig_val_9_qs;
163 logic alert_trig_val_9_wd;
164 logic alert_trig_val_10_qs;
165 logic alert_trig_val_10_wd;
166 logic alert_en_0_we;
167 logic [3:0] alert_en_0_qs;
168 logic [3:0] alert_en_0_wd;
169 logic alert_en_1_we;
170 logic [3:0] alert_en_1_qs;
171 logic [3:0] alert_en_1_wd;
172 logic alert_en_2_we;
173 logic [3:0] alert_en_2_qs;
174 logic [3:0] alert_en_2_wd;
175 logic alert_en_3_we;
176 logic [3:0] alert_en_3_qs;
177 logic [3:0] alert_en_3_wd;
178 logic alert_en_4_we;
179 logic [3:0] alert_en_4_qs;
180 logic [3:0] alert_en_4_wd;
181 logic alert_en_5_we;
182 logic [3:0] alert_en_5_qs;
183 logic [3:0] alert_en_5_wd;
184 logic alert_en_6_we;
185 logic [3:0] alert_en_6_qs;
186 logic [3:0] alert_en_6_wd;
187 logic alert_en_7_we;
188 logic [3:0] alert_en_7_qs;
189 logic [3:0] alert_en_7_wd;
190 logic alert_en_8_we;
191 logic [3:0] alert_en_8_qs;
192 logic [3:0] alert_en_8_wd;
193 logic alert_en_9_we;
194 logic [3:0] alert_en_9_qs;
195 logic [3:0] alert_en_9_wd;
196 logic alert_en_10_we;
197 logic [3:0] alert_en_10_qs;
198 logic [3:0] alert_en_10_wd;
199 logic fatal_alert_en_we;
200 logic fatal_alert_en_val_0_qs;
201 logic fatal_alert_en_val_0_wd;
202 logic fatal_alert_en_val_1_qs;
203 logic fatal_alert_en_val_1_wd;
204 logic fatal_alert_en_val_2_qs;
205 logic fatal_alert_en_val_2_wd;
206 logic fatal_alert_en_val_3_qs;
207 logic fatal_alert_en_val_3_wd;
208 logic fatal_alert_en_val_4_qs;
209 logic fatal_alert_en_val_4_wd;
210 logic fatal_alert_en_val_5_qs;
211 logic fatal_alert_en_val_5_wd;
212 logic fatal_alert_en_val_6_qs;
213 logic fatal_alert_en_val_6_wd;
214 logic fatal_alert_en_val_7_qs;
215 logic fatal_alert_en_val_7_wd;
216 logic fatal_alert_en_val_8_qs;
217 logic fatal_alert_en_val_8_wd;
218 logic fatal_alert_en_val_9_qs;
219 logic fatal_alert_en_val_9_wd;
220 logic fatal_alert_en_val_10_qs;
221 logic fatal_alert_en_val_10_wd;
222 logic recov_alert_we;
223 logic recov_alert_val_0_qs;
224 logic recov_alert_val_0_wd;
225 logic recov_alert_val_1_qs;
226 logic recov_alert_val_1_wd;
227 logic recov_alert_val_2_qs;
228 logic recov_alert_val_2_wd;
229 logic recov_alert_val_3_qs;
230 logic recov_alert_val_3_wd;
231 logic recov_alert_val_4_qs;
232 logic recov_alert_val_4_wd;
233 logic recov_alert_val_5_qs;
234 logic recov_alert_val_5_wd;
235 logic recov_alert_val_6_qs;
236 logic recov_alert_val_6_wd;
237 logic recov_alert_val_7_qs;
238 logic recov_alert_val_7_wd;
239 logic recov_alert_val_8_qs;
240 logic recov_alert_val_8_wd;
241 logic recov_alert_val_9_qs;
242 logic recov_alert_val_9_wd;
243 logic recov_alert_val_10_qs;
244 logic recov_alert_val_10_wd;
245 logic fatal_alert_val_0_qs;
246 logic fatal_alert_val_1_qs;
247 logic fatal_alert_val_2_qs;
248 logic fatal_alert_val_3_qs;
249 logic fatal_alert_val_4_qs;
250 logic fatal_alert_val_5_qs;
251 logic fatal_alert_val_6_qs;
252 logic fatal_alert_val_7_qs;
253 logic fatal_alert_val_8_qs;
254 logic fatal_alert_val_9_qs;
255 logic fatal_alert_val_10_qs;
256 logic fatal_alert_val_11_qs;
257 logic status_ast_init_done_qs;
258 logic [1:0] status_io_pok_qs;
259 logic manual_pad_attr_regwen_0_we;
260 logic manual_pad_attr_regwen_0_qs;
261 logic manual_pad_attr_regwen_0_wd;
262 logic manual_pad_attr_regwen_1_we;
263 logic manual_pad_attr_regwen_1_qs;
264 logic manual_pad_attr_regwen_1_wd;
265 logic manual_pad_attr_regwen_2_we;
266 logic manual_pad_attr_regwen_2_qs;
267 logic manual_pad_attr_regwen_2_wd;
268 logic manual_pad_attr_regwen_3_we;
269 logic manual_pad_attr_regwen_3_qs;
270 logic manual_pad_attr_regwen_3_wd;
271 logic manual_pad_attr_0_re;
272 logic manual_pad_attr_0_we;
273 logic manual_pad_attr_0_pull_en_0_qs;
274 logic manual_pad_attr_0_pull_en_0_wd;
275 logic manual_pad_attr_0_pull_select_0_qs;
276 logic manual_pad_attr_0_pull_select_0_wd;
277 logic manual_pad_attr_0_input_disable_0_qs;
278 logic manual_pad_attr_0_input_disable_0_wd;
279 logic manual_pad_attr_1_re;
280 logic manual_pad_attr_1_we;
281 logic manual_pad_attr_1_pull_en_1_qs;
282 logic manual_pad_attr_1_pull_en_1_wd;
283 logic manual_pad_attr_1_pull_select_1_qs;
284 logic manual_pad_attr_1_pull_select_1_wd;
285 logic manual_pad_attr_1_input_disable_1_qs;
286 logic manual_pad_attr_1_input_disable_1_wd;
287 logic manual_pad_attr_2_re;
288 logic manual_pad_attr_2_we;
289 logic manual_pad_attr_2_pull_en_2_qs;
290 logic manual_pad_attr_2_pull_en_2_wd;
291 logic manual_pad_attr_2_pull_select_2_qs;
292 logic manual_pad_attr_2_pull_select_2_wd;
293 logic manual_pad_attr_2_input_disable_2_qs;
294 logic manual_pad_attr_2_input_disable_2_wd;
295 logic manual_pad_attr_3_re;
296 logic manual_pad_attr_3_we;
297 logic manual_pad_attr_3_pull_en_3_qs;
298 logic manual_pad_attr_3_pull_en_3_wd;
299 logic manual_pad_attr_3_pull_select_3_qs;
300 logic manual_pad_attr_3_pull_select_3_wd;
301 logic manual_pad_attr_3_input_disable_3_qs;
302 logic manual_pad_attr_3_input_disable_3_wd;
303
304 // Register instances
305 // R[intr_state]: V(False)
306 // F[io_status_change]: 0:0
307 prim_subreg #(
308 .DW (1),
309 .SwAccess(prim_subreg_pkg::SwAccessW1C),
310 .RESVAL (1'h0),
311 .Mubi (1'b0)
312 ) u_intr_state_io_status_change (
313 .clk_i (clk_i),
314 .rst_ni (rst_ni),
315
316 // from register interface
317 .we (intr_state_we),
318 .wd (intr_state_io_status_change_wd),
319
320 // from internal hardware
321 .de (hw2reg.intr_state.io_status_change.de),
322 .d (hw2reg.intr_state.io_status_change.d),
323
324 // to internal hardware
325 .qe (),
326 .q (reg2hw.intr_state.io_status_change.q),
327 .ds (),
328
329 // to register interface (read)
330 .qs (intr_state_io_status_change_qs)
331 );
332
333 // F[init_status_change]: 1:1
334 prim_subreg #(
335 .DW (1),
336 .SwAccess(prim_subreg_pkg::SwAccessW1C),
337 .RESVAL (1'h0),
338 .Mubi (1'b0)
339 ) u_intr_state_init_status_change (
340 .clk_i (clk_i),
341 .rst_ni (rst_ni),
342
343 // from register interface
344 .we (intr_state_we),
345 .wd (intr_state_init_status_change_wd),
346
347 // from internal hardware
348 .de (hw2reg.intr_state.init_status_change.de),
349 .d (hw2reg.intr_state.init_status_change.d),
350
351 // to internal hardware
352 .qe (),
353 .q (reg2hw.intr_state.init_status_change.q),
354 .ds (),
355
356 // to register interface (read)
357 .qs (intr_state_init_status_change_qs)
358 );
359
360
361 // R[intr_enable]: V(False)
362 // F[io_status_change]: 0:0
363 prim_subreg #(
364 .DW (1),
365 .SwAccess(prim_subreg_pkg::SwAccessRW),
366 .RESVAL (1'h0),
367 .Mubi (1'b0)
368 ) u_intr_enable_io_status_change (
369 .clk_i (clk_i),
370 .rst_ni (rst_ni),
371
372 // from register interface
373 .we (intr_enable_we),
374 .wd (intr_enable_io_status_change_wd),
375
376 // from internal hardware
377 .de (1'b0),
378 .d ('0),
379
380 // to internal hardware
381 .qe (),
382 .q (reg2hw.intr_enable.io_status_change.q),
383 .ds (),
384
385 // to register interface (read)
386 .qs (intr_enable_io_status_change_qs)
387 );
388
389 // F[init_status_change]: 1:1
390 prim_subreg #(
391 .DW (1),
392 .SwAccess(prim_subreg_pkg::SwAccessRW),
393 .RESVAL (1'h0),
394 .Mubi (1'b0)
395 ) u_intr_enable_init_status_change (
396 .clk_i (clk_i),
397 .rst_ni (rst_ni),
398
399 // from register interface
400 .we (intr_enable_we),
401 .wd (intr_enable_init_status_change_wd),
402
403 // from internal hardware
404 .de (1'b0),
405 .d ('0),
406
407 // to internal hardware
408 .qe (),
409 .q (reg2hw.intr_enable.init_status_change.q),
410 .ds (),
411
412 // to register interface (read)
413 .qs (intr_enable_init_status_change_qs)
414 );
415
416
417 // R[intr_test]: V(True)
418 logic intr_test_qe;
419 logic [1:0] intr_test_flds_we;
420 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T124 T184 T185
421 // F[io_status_change]: 0:0
422 prim_subreg_ext #(
423 .DW (1)
424 ) u_intr_test_io_status_change (
425 .re (1'b0),
426 .we (intr_test_we),
427 .wd (intr_test_io_status_change_wd),
428 .d ('0),
429 .qre (),
430 .qe (intr_test_flds_we[0]),
431 .q (reg2hw.intr_test.io_status_change.q),
432 .ds (),
433 .qs ()
434 );
435 1/1 assign reg2hw.intr_test.io_status_change.qe = intr_test_qe;
Tests: T124 T184 T185
436
437 // F[init_status_change]: 1:1
438 prim_subreg_ext #(
439 .DW (1)
440 ) u_intr_test_init_status_change (
441 .re (1'b0),
442 .we (intr_test_we),
443 .wd (intr_test_init_status_change_wd),
444 .d ('0),
445 .qre (),
446 .qe (intr_test_flds_we[1]),
447 .q (reg2hw.intr_test.init_status_change.q),
448 .ds (),
449 .qs ()
450 );
451 1/1 assign reg2hw.intr_test.init_status_change.qe = intr_test_qe;
Tests: T124 T184 T185
452
453
454 // R[alert_test]: V(True)
455 logic alert_test_qe;
456 logic [1:0] alert_test_flds_we;
457 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T78 T79 T80
458 // F[recov_alert]: 0:0
459 prim_subreg_ext #(
460 .DW (1)
461 ) u_alert_test_recov_alert (
462 .re (1'b0),
463 .we (alert_test_we),
464 .wd (alert_test_recov_alert_wd),
465 .d ('0),
466 .qre (),
467 .qe (alert_test_flds_we[0]),
468 .q (reg2hw.alert_test.recov_alert.q),
469 .ds (),
470 .qs ()
471 );
472 1/1 assign reg2hw.alert_test.recov_alert.qe = alert_test_qe;
Tests: T78 T79 T80
473
474 // F[fatal_alert]: 1:1
475 prim_subreg_ext #(
476 .DW (1)
477 ) u_alert_test_fatal_alert (
478 .re (1'b0),
479 .we (alert_test_we),
480 .wd (alert_test_fatal_alert_wd),
481 .d ('0),
482 .qre (),
483 .qe (alert_test_flds_we[1]),
484 .q (reg2hw.alert_test.fatal_alert.q),
485 .ds (),
486 .qs ()
487 );
488 1/1 assign reg2hw.alert_test.fatal_alert.qe = alert_test_qe;
Tests: T78 T79 T80
489
490
491 // R[cfg_regwen]: V(False)
492 prim_subreg #(
493 .DW (1),
494 .SwAccess(prim_subreg_pkg::SwAccessW0C),
495 .RESVAL (1'h1),
496 .Mubi (1'b0)
497 ) u_cfg_regwen (
498 .clk_i (clk_i),
499 .rst_ni (rst_ni),
500
501 // from register interface
502 .we (cfg_regwen_we),
503 .wd (cfg_regwen_wd),
504
505 // from internal hardware
506 .de (1'b0),
507 .d ('0),
508
509 // to internal hardware
510 .qe (),
511 .q (),
512 .ds (),
513
514 // to register interface (read)
515 .qs (cfg_regwen_qs)
516 );
517
518
519 // Subregister 0 of Multireg alert_trig
520 // R[alert_trig]: V(False)
521 // F[val_0]: 0:0
522 prim_subreg #(
523 .DW (1),
524 .SwAccess(prim_subreg_pkg::SwAccessRW),
525 .RESVAL (1'h0),
526 .Mubi (1'b0)
527 ) u_alert_trig_val_0 (
528 .clk_i (clk_i),
529 .rst_ni (rst_ni),
530
531 // from register interface
532 .we (alert_trig_we),
533 .wd (alert_trig_val_0_wd),
534
535 // from internal hardware
536 .de (1'b0),
537 .d ('0),
538
539 // to internal hardware
540 .qe (),
541 .q (reg2hw.alert_trig[0].q),
542 .ds (),
543
544 // to register interface (read)
545 .qs (alert_trig_val_0_qs)
546 );
547
548 // F[val_1]: 1:1
549 prim_subreg #(
550 .DW (1),
551 .SwAccess(prim_subreg_pkg::SwAccessRW),
552 .RESVAL (1'h0),
553 .Mubi (1'b0)
554 ) u_alert_trig_val_1 (
555 .clk_i (clk_i),
556 .rst_ni (rst_ni),
557
558 // from register interface
559 .we (alert_trig_we),
560 .wd (alert_trig_val_1_wd),
561
562 // from internal hardware
563 .de (1'b0),
564 .d ('0),
565
566 // to internal hardware
567 .qe (),
568 .q (reg2hw.alert_trig[1].q),
569 .ds (),
570
571 // to register interface (read)
572 .qs (alert_trig_val_1_qs)
573 );
574
575 // F[val_2]: 2:2
576 prim_subreg #(
577 .DW (1),
578 .SwAccess(prim_subreg_pkg::SwAccessRW),
579 .RESVAL (1'h0),
580 .Mubi (1'b0)
581 ) u_alert_trig_val_2 (
582 .clk_i (clk_i),
583 .rst_ni (rst_ni),
584
585 // from register interface
586 .we (alert_trig_we),
587 .wd (alert_trig_val_2_wd),
588
589 // from internal hardware
590 .de (1'b0),
591 .d ('0),
592
593 // to internal hardware
594 .qe (),
595 .q (reg2hw.alert_trig[2].q),
596 .ds (),
597
598 // to register interface (read)
599 .qs (alert_trig_val_2_qs)
600 );
601
602 // F[val_3]: 3:3
603 prim_subreg #(
604 .DW (1),
605 .SwAccess(prim_subreg_pkg::SwAccessRW),
606 .RESVAL (1'h0),
607 .Mubi (1'b0)
608 ) u_alert_trig_val_3 (
609 .clk_i (clk_i),
610 .rst_ni (rst_ni),
611
612 // from register interface
613 .we (alert_trig_we),
614 .wd (alert_trig_val_3_wd),
615
616 // from internal hardware
617 .de (1'b0),
618 .d ('0),
619
620 // to internal hardware
621 .qe (),
622 .q (reg2hw.alert_trig[3].q),
623 .ds (),
624
625 // to register interface (read)
626 .qs (alert_trig_val_3_qs)
627 );
628
629 // F[val_4]: 4:4
630 prim_subreg #(
631 .DW (1),
632 .SwAccess(prim_subreg_pkg::SwAccessRW),
633 .RESVAL (1'h0),
634 .Mubi (1'b0)
635 ) u_alert_trig_val_4 (
636 .clk_i (clk_i),
637 .rst_ni (rst_ni),
638
639 // from register interface
640 .we (alert_trig_we),
641 .wd (alert_trig_val_4_wd),
642
643 // from internal hardware
644 .de (1'b0),
645 .d ('0),
646
647 // to internal hardware
648 .qe (),
649 .q (reg2hw.alert_trig[4].q),
650 .ds (),
651
652 // to register interface (read)
653 .qs (alert_trig_val_4_qs)
654 );
655
656 // F[val_5]: 5:5
657 prim_subreg #(
658 .DW (1),
659 .SwAccess(prim_subreg_pkg::SwAccessRW),
660 .RESVAL (1'h0),
661 .Mubi (1'b0)
662 ) u_alert_trig_val_5 (
663 .clk_i (clk_i),
664 .rst_ni (rst_ni),
665
666 // from register interface
667 .we (alert_trig_we),
668 .wd (alert_trig_val_5_wd),
669
670 // from internal hardware
671 .de (1'b0),
672 .d ('0),
673
674 // to internal hardware
675 .qe (),
676 .q (reg2hw.alert_trig[5].q),
677 .ds (),
678
679 // to register interface (read)
680 .qs (alert_trig_val_5_qs)
681 );
682
683 // F[val_6]: 6:6
684 prim_subreg #(
685 .DW (1),
686 .SwAccess(prim_subreg_pkg::SwAccessRW),
687 .RESVAL (1'h0),
688 .Mubi (1'b0)
689 ) u_alert_trig_val_6 (
690 .clk_i (clk_i),
691 .rst_ni (rst_ni),
692
693 // from register interface
694 .we (alert_trig_we),
695 .wd (alert_trig_val_6_wd),
696
697 // from internal hardware
698 .de (1'b0),
699 .d ('0),
700
701 // to internal hardware
702 .qe (),
703 .q (reg2hw.alert_trig[6].q),
704 .ds (),
705
706 // to register interface (read)
707 .qs (alert_trig_val_6_qs)
708 );
709
710 // F[val_7]: 7:7
711 prim_subreg #(
712 .DW (1),
713 .SwAccess(prim_subreg_pkg::SwAccessRW),
714 .RESVAL (1'h0),
715 .Mubi (1'b0)
716 ) u_alert_trig_val_7 (
717 .clk_i (clk_i),
718 .rst_ni (rst_ni),
719
720 // from register interface
721 .we (alert_trig_we),
722 .wd (alert_trig_val_7_wd),
723
724 // from internal hardware
725 .de (1'b0),
726 .d ('0),
727
728 // to internal hardware
729 .qe (),
730 .q (reg2hw.alert_trig[7].q),
731 .ds (),
732
733 // to register interface (read)
734 .qs (alert_trig_val_7_qs)
735 );
736
737 // F[val_8]: 8:8
738 prim_subreg #(
739 .DW (1),
740 .SwAccess(prim_subreg_pkg::SwAccessRW),
741 .RESVAL (1'h0),
742 .Mubi (1'b0)
743 ) u_alert_trig_val_8 (
744 .clk_i (clk_i),
745 .rst_ni (rst_ni),
746
747 // from register interface
748 .we (alert_trig_we),
749 .wd (alert_trig_val_8_wd),
750
751 // from internal hardware
752 .de (1'b0),
753 .d ('0),
754
755 // to internal hardware
756 .qe (),
757 .q (reg2hw.alert_trig[8].q),
758 .ds (),
759
760 // to register interface (read)
761 .qs (alert_trig_val_8_qs)
762 );
763
764 // F[val_9]: 9:9
765 prim_subreg #(
766 .DW (1),
767 .SwAccess(prim_subreg_pkg::SwAccessRW),
768 .RESVAL (1'h0),
769 .Mubi (1'b0)
770 ) u_alert_trig_val_9 (
771 .clk_i (clk_i),
772 .rst_ni (rst_ni),
773
774 // from register interface
775 .we (alert_trig_we),
776 .wd (alert_trig_val_9_wd),
777
778 // from internal hardware
779 .de (1'b0),
780 .d ('0),
781
782 // to internal hardware
783 .qe (),
784 .q (reg2hw.alert_trig[9].q),
785 .ds (),
786
787 // to register interface (read)
788 .qs (alert_trig_val_9_qs)
789 );
790
791 // F[val_10]: 10:10
792 prim_subreg #(
793 .DW (1),
794 .SwAccess(prim_subreg_pkg::SwAccessRW),
795 .RESVAL (1'h0),
796 .Mubi (1'b0)
797 ) u_alert_trig_val_10 (
798 .clk_i (clk_i),
799 .rst_ni (rst_ni),
800
801 // from register interface
802 .we (alert_trig_we),
803 .wd (alert_trig_val_10_wd),
804
805 // from internal hardware
806 .de (1'b0),
807 .d ('0),
808
809 // to internal hardware
810 .qe (),
811 .q (reg2hw.alert_trig[10].q),
812 .ds (),
813
814 // to register interface (read)
815 .qs (alert_trig_val_10_qs)
816 );
817
818
819 // Subregister 0 of Multireg alert_en
820 // R[alert_en_0]: V(False)
821 // Create REGWEN-gated WE signal
822 logic alert_en_0_gated_we;
823 1/1 assign alert_en_0_gated_we = alert_en_0_we & cfg_regwen_qs;
Tests: T157 T158 T76
824 prim_subreg #(
825 .DW (4),
826 .SwAccess(prim_subreg_pkg::SwAccessRW),
827 .RESVAL (4'h6),
828 .Mubi (1'b1)
829 ) u_alert_en_0 (
830 .clk_i (clk_i),
831 .rst_ni (rst_ni),
832
833 // from register interface
834 .we (alert_en_0_gated_we),
835 .wd (alert_en_0_wd),
836
837 // from internal hardware
838 .de (1'b0),
839 .d ('0),
840
841 // to internal hardware
842 .qe (),
843 .q (reg2hw.alert_en[0].q),
844 .ds (),
845
846 // to register interface (read)
847 .qs (alert_en_0_qs)
848 );
849
850
851 // Subregister 1 of Multireg alert_en
852 // R[alert_en_1]: V(False)
853 // Create REGWEN-gated WE signal
854 logic alert_en_1_gated_we;
855 1/1 assign alert_en_1_gated_we = alert_en_1_we & cfg_regwen_qs;
Tests: T157 T76 T159
856 prim_subreg #(
857 .DW (4),
858 .SwAccess(prim_subreg_pkg::SwAccessRW),
859 .RESVAL (4'h6),
860 .Mubi (1'b1)
861 ) u_alert_en_1 (
862 .clk_i (clk_i),
863 .rst_ni (rst_ni),
864
865 // from register interface
866 .we (alert_en_1_gated_we),
867 .wd (alert_en_1_wd),
868
869 // from internal hardware
870 .de (1'b0),
871 .d ('0),
872
873 // to internal hardware
874 .qe (),
875 .q (reg2hw.alert_en[1].q),
876 .ds (),
877
878 // to register interface (read)
879 .qs (alert_en_1_qs)
880 );
881
882
883 // Subregister 2 of Multireg alert_en
884 // R[alert_en_2]: V(False)
885 // Create REGWEN-gated WE signal
886 logic alert_en_2_gated_we;
887 1/1 assign alert_en_2_gated_we = alert_en_2_we & cfg_regwen_qs;
Tests: T157 T158 T76
888 prim_subreg #(
889 .DW (4),
890 .SwAccess(prim_subreg_pkg::SwAccessRW),
891 .RESVAL (4'h6),
892 .Mubi (1'b1)
893 ) u_alert_en_2 (
894 .clk_i (clk_i),
895 .rst_ni (rst_ni),
896
897 // from register interface
898 .we (alert_en_2_gated_we),
899 .wd (alert_en_2_wd),
900
901 // from internal hardware
902 .de (1'b0),
903 .d ('0),
904
905 // to internal hardware
906 .qe (),
907 .q (reg2hw.alert_en[2].q),
908 .ds (),
909
910 // to register interface (read)
911 .qs (alert_en_2_qs)
912 );
913
914
915 // Subregister 3 of Multireg alert_en
916 // R[alert_en_3]: V(False)
917 // Create REGWEN-gated WE signal
918 logic alert_en_3_gated_we;
919 1/1 assign alert_en_3_gated_we = alert_en_3_we & cfg_regwen_qs;
Tests: T157 T76 T159
920 prim_subreg #(
921 .DW (4),
922 .SwAccess(prim_subreg_pkg::SwAccessRW),
923 .RESVAL (4'h6),
924 .Mubi (1'b1)
925 ) u_alert_en_3 (
926 .clk_i (clk_i),
927 .rst_ni (rst_ni),
928
929 // from register interface
930 .we (alert_en_3_gated_we),
931 .wd (alert_en_3_wd),
932
933 // from internal hardware
934 .de (1'b0),
935 .d ('0),
936
937 // to internal hardware
938 .qe (),
939 .q (reg2hw.alert_en[3].q),
940 .ds (),
941
942 // to register interface (read)
943 .qs (alert_en_3_qs)
944 );
945
946
947 // Subregister 4 of Multireg alert_en
948 // R[alert_en_4]: V(False)
949 // Create REGWEN-gated WE signal
950 logic alert_en_4_gated_we;
951 1/1 assign alert_en_4_gated_we = alert_en_4_we & cfg_regwen_qs;
Tests: T157 T158 T76
952 prim_subreg #(
953 .DW (4),
954 .SwAccess(prim_subreg_pkg::SwAccessRW),
955 .RESVAL (4'h6),
956 .Mubi (1'b1)
957 ) u_alert_en_4 (
958 .clk_i (clk_i),
959 .rst_ni (rst_ni),
960
961 // from register interface
962 .we (alert_en_4_gated_we),
963 .wd (alert_en_4_wd),
964
965 // from internal hardware
966 .de (1'b0),
967 .d ('0),
968
969 // to internal hardware
970 .qe (),
971 .q (reg2hw.alert_en[4].q),
972 .ds (),
973
974 // to register interface (read)
975 .qs (alert_en_4_qs)
976 );
977
978
979 // Subregister 5 of Multireg alert_en
980 // R[alert_en_5]: V(False)
981 // Create REGWEN-gated WE signal
982 logic alert_en_5_gated_we;
983 1/1 assign alert_en_5_gated_we = alert_en_5_we & cfg_regwen_qs;
Tests: T157 T76 T159
984 prim_subreg #(
985 .DW (4),
986 .SwAccess(prim_subreg_pkg::SwAccessRW),
987 .RESVAL (4'h6),
988 .Mubi (1'b1)
989 ) u_alert_en_5 (
990 .clk_i (clk_i),
991 .rst_ni (rst_ni),
992
993 // from register interface
994 .we (alert_en_5_gated_we),
995 .wd (alert_en_5_wd),
996
997 // from internal hardware
998 .de (1'b0),
999 .d ('0),
1000
1001 // to internal hardware
1002 .qe (),
1003 .q (reg2hw.alert_en[5].q),
1004 .ds (),
1005
1006 // to register interface (read)
1007 .qs (alert_en_5_qs)
1008 );
1009
1010
1011 // Subregister 6 of Multireg alert_en
1012 // R[alert_en_6]: V(False)
1013 // Create REGWEN-gated WE signal
1014 logic alert_en_6_gated_we;
1015 1/1 assign alert_en_6_gated_we = alert_en_6_we & cfg_regwen_qs;
Tests: T157 T76 T159
1016 prim_subreg #(
1017 .DW (4),
1018 .SwAccess(prim_subreg_pkg::SwAccessRW),
1019 .RESVAL (4'h6),
1020 .Mubi (1'b1)
1021 ) u_alert_en_6 (
1022 .clk_i (clk_i),
1023 .rst_ni (rst_ni),
1024
1025 // from register interface
1026 .we (alert_en_6_gated_we),
1027 .wd (alert_en_6_wd),
1028
1029 // from internal hardware
1030 .de (1'b0),
1031 .d ('0),
1032
1033 // to internal hardware
1034 .qe (),
1035 .q (reg2hw.alert_en[6].q),
1036 .ds (),
1037
1038 // to register interface (read)
1039 .qs (alert_en_6_qs)
1040 );
1041
1042
1043 // Subregister 7 of Multireg alert_en
1044 // R[alert_en_7]: V(False)
1045 // Create REGWEN-gated WE signal
1046 logic alert_en_7_gated_we;
1047 1/1 assign alert_en_7_gated_we = alert_en_7_we & cfg_regwen_qs;
Tests: T157 T76 T159
1048 prim_subreg #(
1049 .DW (4),
1050 .SwAccess(prim_subreg_pkg::SwAccessRW),
1051 .RESVAL (4'h6),
1052 .Mubi (1'b1)
1053 ) u_alert_en_7 (
1054 .clk_i (clk_i),
1055 .rst_ni (rst_ni),
1056
1057 // from register interface
1058 .we (alert_en_7_gated_we),
1059 .wd (alert_en_7_wd),
1060
1061 // from internal hardware
1062 .de (1'b0),
1063 .d ('0),
1064
1065 // to internal hardware
1066 .qe (),
1067 .q (reg2hw.alert_en[7].q),
1068 .ds (),
1069
1070 // to register interface (read)
1071 .qs (alert_en_7_qs)
1072 );
1073
1074
1075 // Subregister 8 of Multireg alert_en
1076 // R[alert_en_8]: V(False)
1077 // Create REGWEN-gated WE signal
1078 logic alert_en_8_gated_we;
1079 1/1 assign alert_en_8_gated_we = alert_en_8_we & cfg_regwen_qs;
Tests: T157 T76 T159
1080 prim_subreg #(
1081 .DW (4),
1082 .SwAccess(prim_subreg_pkg::SwAccessRW),
1083 .RESVAL (4'h6),
1084 .Mubi (1'b1)
1085 ) u_alert_en_8 (
1086 .clk_i (clk_i),
1087 .rst_ni (rst_ni),
1088
1089 // from register interface
1090 .we (alert_en_8_gated_we),
1091 .wd (alert_en_8_wd),
1092
1093 // from internal hardware
1094 .de (1'b0),
1095 .d ('0),
1096
1097 // to internal hardware
1098 .qe (),
1099 .q (reg2hw.alert_en[8].q),
1100 .ds (),
1101
1102 // to register interface (read)
1103 .qs (alert_en_8_qs)
1104 );
1105
1106
1107 // Subregister 9 of Multireg alert_en
1108 // R[alert_en_9]: V(False)
1109 // Create REGWEN-gated WE signal
1110 logic alert_en_9_gated_we;
1111 1/1 assign alert_en_9_gated_we = alert_en_9_we & cfg_regwen_qs;
Tests: T157 T76 T159
1112 prim_subreg #(
1113 .DW (4),
1114 .SwAccess(prim_subreg_pkg::SwAccessRW),
1115 .RESVAL (4'h6),
1116 .Mubi (1'b1)
1117 ) u_alert_en_9 (
1118 .clk_i (clk_i),
1119 .rst_ni (rst_ni),
1120
1121 // from register interface
1122 .we (alert_en_9_gated_we),
1123 .wd (alert_en_9_wd),
1124
1125 // from internal hardware
1126 .de (1'b0),
1127 .d ('0),
1128
1129 // to internal hardware
1130 .qe (),
1131 .q (reg2hw.alert_en[9].q),
1132 .ds (),
1133
1134 // to register interface (read)
1135 .qs (alert_en_9_qs)
1136 );
1137
1138
1139 // Subregister 10 of Multireg alert_en
1140 // R[alert_en_10]: V(False)
1141 // Create REGWEN-gated WE signal
1142 logic alert_en_10_gated_we;
1143 1/1 assign alert_en_10_gated_we = alert_en_10_we & cfg_regwen_qs;
Tests: T157 T76 T159
1144 prim_subreg #(
1145 .DW (4),
1146 .SwAccess(prim_subreg_pkg::SwAccessRW),
1147 .RESVAL (4'h6),
1148 .Mubi (1'b1)
1149 ) u_alert_en_10 (
1150 .clk_i (clk_i),
1151 .rst_ni (rst_ni),
1152
1153 // from register interface
1154 .we (alert_en_10_gated_we),
1155 .wd (alert_en_10_wd),
1156
1157 // from internal hardware
1158 .de (1'b0),
1159 .d ('0),
1160
1161 // to internal hardware
1162 .qe (),
1163 .q (reg2hw.alert_en[10].q),
1164 .ds (),
1165
1166 // to register interface (read)
1167 .qs (alert_en_10_qs)
1168 );
1169
1170
1171 // Subregister 0 of Multireg fatal_alert_en
1172 // R[fatal_alert_en]: V(False)
1173 // Create REGWEN-gated WE signal
1174 logic fatal_alert_en_gated_we;
1175 1/1 assign fatal_alert_en_gated_we = fatal_alert_en_we & cfg_regwen_qs;
Tests: T158 T376 T377
1176 // F[val_0]: 0:0
1177 prim_subreg #(
1178 .DW (1),
1179 .SwAccess(prim_subreg_pkg::SwAccessRW),
1180 .RESVAL (1'h0),
1181 .Mubi (1'b0)
1182 ) u_fatal_alert_en_val_0 (
1183 .clk_i (clk_i),
1184 .rst_ni (rst_ni),
1185
1186 // from register interface
1187 .we (fatal_alert_en_gated_we),
1188 .wd (fatal_alert_en_val_0_wd),
1189
1190 // from internal hardware
1191 .de (1'b0),
1192 .d ('0),
1193
1194 // to internal hardware
1195 .qe (),
1196 .q (reg2hw.fatal_alert_en[0].q),
1197 .ds (),
1198
1199 // to register interface (read)
1200 .qs (fatal_alert_en_val_0_qs)
1201 );
1202
1203 // F[val_1]: 1:1
1204 prim_subreg #(
1205 .DW (1),
1206 .SwAccess(prim_subreg_pkg::SwAccessRW),
1207 .RESVAL (1'h0),
1208 .Mubi (1'b0)
1209 ) u_fatal_alert_en_val_1 (
1210 .clk_i (clk_i),
1211 .rst_ni (rst_ni),
1212
1213 // from register interface
1214 .we (fatal_alert_en_gated_we),
1215 .wd (fatal_alert_en_val_1_wd),
1216
1217 // from internal hardware
1218 .de (1'b0),
1219 .d ('0),
1220
1221 // to internal hardware
1222 .qe (),
1223 .q (reg2hw.fatal_alert_en[1].q),
1224 .ds (),
1225
1226 // to register interface (read)
1227 .qs (fatal_alert_en_val_1_qs)
1228 );
1229
1230 // F[val_2]: 2:2
1231 prim_subreg #(
1232 .DW (1),
1233 .SwAccess(prim_subreg_pkg::SwAccessRW),
1234 .RESVAL (1'h0),
1235 .Mubi (1'b0)
1236 ) u_fatal_alert_en_val_2 (
1237 .clk_i (clk_i),
1238 .rst_ni (rst_ni),
1239
1240 // from register interface
1241 .we (fatal_alert_en_gated_we),
1242 .wd (fatal_alert_en_val_2_wd),
1243
1244 // from internal hardware
1245 .de (1'b0),
1246 .d ('0),
1247
1248 // to internal hardware
1249 .qe (),
1250 .q (reg2hw.fatal_alert_en[2].q),
1251 .ds (),
1252
1253 // to register interface (read)
1254 .qs (fatal_alert_en_val_2_qs)
1255 );
1256
1257 // F[val_3]: 3:3
1258 prim_subreg #(
1259 .DW (1),
1260 .SwAccess(prim_subreg_pkg::SwAccessRW),
1261 .RESVAL (1'h0),
1262 .Mubi (1'b0)
1263 ) u_fatal_alert_en_val_3 (
1264 .clk_i (clk_i),
1265 .rst_ni (rst_ni),
1266
1267 // from register interface
1268 .we (fatal_alert_en_gated_we),
1269 .wd (fatal_alert_en_val_3_wd),
1270
1271 // from internal hardware
1272 .de (1'b0),
1273 .d ('0),
1274
1275 // to internal hardware
1276 .qe (),
1277 .q (reg2hw.fatal_alert_en[3].q),
1278 .ds (),
1279
1280 // to register interface (read)
1281 .qs (fatal_alert_en_val_3_qs)
1282 );
1283
1284 // F[val_4]: 4:4
1285 prim_subreg #(
1286 .DW (1),
1287 .SwAccess(prim_subreg_pkg::SwAccessRW),
1288 .RESVAL (1'h0),
1289 .Mubi (1'b0)
1290 ) u_fatal_alert_en_val_4 (
1291 .clk_i (clk_i),
1292 .rst_ni (rst_ni),
1293
1294 // from register interface
1295 .we (fatal_alert_en_gated_we),
1296 .wd (fatal_alert_en_val_4_wd),
1297
1298 // from internal hardware
1299 .de (1'b0),
1300 .d ('0),
1301
1302 // to internal hardware
1303 .qe (),
1304 .q (reg2hw.fatal_alert_en[4].q),
1305 .ds (),
1306
1307 // to register interface (read)
1308 .qs (fatal_alert_en_val_4_qs)
1309 );
1310
1311 // F[val_5]: 5:5
1312 prim_subreg #(
1313 .DW (1),
1314 .SwAccess(prim_subreg_pkg::SwAccessRW),
1315 .RESVAL (1'h0),
1316 .Mubi (1'b0)
1317 ) u_fatal_alert_en_val_5 (
1318 .clk_i (clk_i),
1319 .rst_ni (rst_ni),
1320
1321 // from register interface
1322 .we (fatal_alert_en_gated_we),
1323 .wd (fatal_alert_en_val_5_wd),
1324
1325 // from internal hardware
1326 .de (1'b0),
1327 .d ('0),
1328
1329 // to internal hardware
1330 .qe (),
1331 .q (reg2hw.fatal_alert_en[5].q),
1332 .ds (),
1333
1334 // to register interface (read)
1335 .qs (fatal_alert_en_val_5_qs)
1336 );
1337
1338 // F[val_6]: 6:6
1339 prim_subreg #(
1340 .DW (1),
1341 .SwAccess(prim_subreg_pkg::SwAccessRW),
1342 .RESVAL (1'h0),
1343 .Mubi (1'b0)
1344 ) u_fatal_alert_en_val_6 (
1345 .clk_i (clk_i),
1346 .rst_ni (rst_ni),
1347
1348 // from register interface
1349 .we (fatal_alert_en_gated_we),
1350 .wd (fatal_alert_en_val_6_wd),
1351
1352 // from internal hardware
1353 .de (1'b0),
1354 .d ('0),
1355
1356 // to internal hardware
1357 .qe (),
1358 .q (reg2hw.fatal_alert_en[6].q),
1359 .ds (),
1360
1361 // to register interface (read)
1362 .qs (fatal_alert_en_val_6_qs)
1363 );
1364
1365 // F[val_7]: 7:7
1366 prim_subreg #(
1367 .DW (1),
1368 .SwAccess(prim_subreg_pkg::SwAccessRW),
1369 .RESVAL (1'h0),
1370 .Mubi (1'b0)
1371 ) u_fatal_alert_en_val_7 (
1372 .clk_i (clk_i),
1373 .rst_ni (rst_ni),
1374
1375 // from register interface
1376 .we (fatal_alert_en_gated_we),
1377 .wd (fatal_alert_en_val_7_wd),
1378
1379 // from internal hardware
1380 .de (1'b0),
1381 .d ('0),
1382
1383 // to internal hardware
1384 .qe (),
1385 .q (reg2hw.fatal_alert_en[7].q),
1386 .ds (),
1387
1388 // to register interface (read)
1389 .qs (fatal_alert_en_val_7_qs)
1390 );
1391
1392 // F[val_8]: 8:8
1393 prim_subreg #(
1394 .DW (1),
1395 .SwAccess(prim_subreg_pkg::SwAccessRW),
1396 .RESVAL (1'h0),
1397 .Mubi (1'b0)
1398 ) u_fatal_alert_en_val_8 (
1399 .clk_i (clk_i),
1400 .rst_ni (rst_ni),
1401
1402 // from register interface
1403 .we (fatal_alert_en_gated_we),
1404 .wd (fatal_alert_en_val_8_wd),
1405
1406 // from internal hardware
1407 .de (1'b0),
1408 .d ('0),
1409
1410 // to internal hardware
1411 .qe (),
1412 .q (reg2hw.fatal_alert_en[8].q),
1413 .ds (),
1414
1415 // to register interface (read)
1416 .qs (fatal_alert_en_val_8_qs)
1417 );
1418
1419 // F[val_9]: 9:9
1420 prim_subreg #(
1421 .DW (1),
1422 .SwAccess(prim_subreg_pkg::SwAccessRW),
1423 .RESVAL (1'h0),
1424 .Mubi (1'b0)
1425 ) u_fatal_alert_en_val_9 (
1426 .clk_i (clk_i),
1427 .rst_ni (rst_ni),
1428
1429 // from register interface
1430 .we (fatal_alert_en_gated_we),
1431 .wd (fatal_alert_en_val_9_wd),
1432
1433 // from internal hardware
1434 .de (1'b0),
1435 .d ('0),
1436
1437 // to internal hardware
1438 .qe (),
1439 .q (reg2hw.fatal_alert_en[9].q),
1440 .ds (),
1441
1442 // to register interface (read)
1443 .qs (fatal_alert_en_val_9_qs)
1444 );
1445
1446 // F[val_10]: 10:10
1447 prim_subreg #(
1448 .DW (1),
1449 .SwAccess(prim_subreg_pkg::SwAccessRW),
1450 .RESVAL (1'h0),
1451 .Mubi (1'b0)
1452 ) u_fatal_alert_en_val_10 (
1453 .clk_i (clk_i),
1454 .rst_ni (rst_ni),
1455
1456 // from register interface
1457 .we (fatal_alert_en_gated_we),
1458 .wd (fatal_alert_en_val_10_wd),
1459
1460 // from internal hardware
1461 .de (1'b0),
1462 .d ('0),
1463
1464 // to internal hardware
1465 .qe (),
1466 .q (reg2hw.fatal_alert_en[10].q),
1467 .ds (),
1468
1469 // to register interface (read)
1470 .qs (fatal_alert_en_val_10_qs)
1471 );
1472
1473
1474 // Subregister 0 of Multireg recov_alert
1475 // R[recov_alert]: V(False)
1476 // F[val_0]: 0:0
1477 prim_subreg #(
1478 .DW (1),
1479 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1480 .RESVAL (1'h0),
1481 .Mubi (1'b0)
1482 ) u_recov_alert_val_0 (
1483 .clk_i (clk_i),
1484 .rst_ni (rst_ni),
1485
1486 // from register interface
1487 .we (recov_alert_we),
1488 .wd (recov_alert_val_0_wd),
1489
1490 // from internal hardware
1491 .de (hw2reg.recov_alert[0].de),
1492 .d (hw2reg.recov_alert[0].d),
1493
1494 // to internal hardware
1495 .qe (),
1496 .q (reg2hw.recov_alert[0].q),
1497 .ds (),
1498
1499 // to register interface (read)
1500 .qs (recov_alert_val_0_qs)
1501 );
1502
1503 // F[val_1]: 1:1
1504 prim_subreg #(
1505 .DW (1),
1506 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1507 .RESVAL (1'h0),
1508 .Mubi (1'b0)
1509 ) u_recov_alert_val_1 (
1510 .clk_i (clk_i),
1511 .rst_ni (rst_ni),
1512
1513 // from register interface
1514 .we (recov_alert_we),
1515 .wd (recov_alert_val_1_wd),
1516
1517 // from internal hardware
1518 .de (hw2reg.recov_alert[1].de),
1519 .d (hw2reg.recov_alert[1].d),
1520
1521 // to internal hardware
1522 .qe (),
1523 .q (reg2hw.recov_alert[1].q),
1524 .ds (),
1525
1526 // to register interface (read)
1527 .qs (recov_alert_val_1_qs)
1528 );
1529
1530 // F[val_2]: 2:2
1531 prim_subreg #(
1532 .DW (1),
1533 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1534 .RESVAL (1'h0),
1535 .Mubi (1'b0)
1536 ) u_recov_alert_val_2 (
1537 .clk_i (clk_i),
1538 .rst_ni (rst_ni),
1539
1540 // from register interface
1541 .we (recov_alert_we),
1542 .wd (recov_alert_val_2_wd),
1543
1544 // from internal hardware
1545 .de (hw2reg.recov_alert[2].de),
1546 .d (hw2reg.recov_alert[2].d),
1547
1548 // to internal hardware
1549 .qe (),
1550 .q (reg2hw.recov_alert[2].q),
1551 .ds (),
1552
1553 // to register interface (read)
1554 .qs (recov_alert_val_2_qs)
1555 );
1556
1557 // F[val_3]: 3:3
1558 prim_subreg #(
1559 .DW (1),
1560 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1561 .RESVAL (1'h0),
1562 .Mubi (1'b0)
1563 ) u_recov_alert_val_3 (
1564 .clk_i (clk_i),
1565 .rst_ni (rst_ni),
1566
1567 // from register interface
1568 .we (recov_alert_we),
1569 .wd (recov_alert_val_3_wd),
1570
1571 // from internal hardware
1572 .de (hw2reg.recov_alert[3].de),
1573 .d (hw2reg.recov_alert[3].d),
1574
1575 // to internal hardware
1576 .qe (),
1577 .q (reg2hw.recov_alert[3].q),
1578 .ds (),
1579
1580 // to register interface (read)
1581 .qs (recov_alert_val_3_qs)
1582 );
1583
1584 // F[val_4]: 4:4
1585 prim_subreg #(
1586 .DW (1),
1587 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1588 .RESVAL (1'h0),
1589 .Mubi (1'b0)
1590 ) u_recov_alert_val_4 (
1591 .clk_i (clk_i),
1592 .rst_ni (rst_ni),
1593
1594 // from register interface
1595 .we (recov_alert_we),
1596 .wd (recov_alert_val_4_wd),
1597
1598 // from internal hardware
1599 .de (hw2reg.recov_alert[4].de),
1600 .d (hw2reg.recov_alert[4].d),
1601
1602 // to internal hardware
1603 .qe (),
1604 .q (reg2hw.recov_alert[4].q),
1605 .ds (),
1606
1607 // to register interface (read)
1608 .qs (recov_alert_val_4_qs)
1609 );
1610
1611 // F[val_5]: 5:5
1612 prim_subreg #(
1613 .DW (1),
1614 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1615 .RESVAL (1'h0),
1616 .Mubi (1'b0)
1617 ) u_recov_alert_val_5 (
1618 .clk_i (clk_i),
1619 .rst_ni (rst_ni),
1620
1621 // from register interface
1622 .we (recov_alert_we),
1623 .wd (recov_alert_val_5_wd),
1624
1625 // from internal hardware
1626 .de (hw2reg.recov_alert[5].de),
1627 .d (hw2reg.recov_alert[5].d),
1628
1629 // to internal hardware
1630 .qe (),
1631 .q (reg2hw.recov_alert[5].q),
1632 .ds (),
1633
1634 // to register interface (read)
1635 .qs (recov_alert_val_5_qs)
1636 );
1637
1638 // F[val_6]: 6:6
1639 prim_subreg #(
1640 .DW (1),
1641 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1642 .RESVAL (1'h0),
1643 .Mubi (1'b0)
1644 ) u_recov_alert_val_6 (
1645 .clk_i (clk_i),
1646 .rst_ni (rst_ni),
1647
1648 // from register interface
1649 .we (recov_alert_we),
1650 .wd (recov_alert_val_6_wd),
1651
1652 // from internal hardware
1653 .de (hw2reg.recov_alert[6].de),
1654 .d (hw2reg.recov_alert[6].d),
1655
1656 // to internal hardware
1657 .qe (),
1658 .q (reg2hw.recov_alert[6].q),
1659 .ds (),
1660
1661 // to register interface (read)
1662 .qs (recov_alert_val_6_qs)
1663 );
1664
1665 // F[val_7]: 7:7
1666 prim_subreg #(
1667 .DW (1),
1668 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1669 .RESVAL (1'h0),
1670 .Mubi (1'b0)
1671 ) u_recov_alert_val_7 (
1672 .clk_i (clk_i),
1673 .rst_ni (rst_ni),
1674
1675 // from register interface
1676 .we (recov_alert_we),
1677 .wd (recov_alert_val_7_wd),
1678
1679 // from internal hardware
1680 .de (hw2reg.recov_alert[7].de),
1681 .d (hw2reg.recov_alert[7].d),
1682
1683 // to internal hardware
1684 .qe (),
1685 .q (reg2hw.recov_alert[7].q),
1686 .ds (),
1687
1688 // to register interface (read)
1689 .qs (recov_alert_val_7_qs)
1690 );
1691
1692 // F[val_8]: 8:8
1693 prim_subreg #(
1694 .DW (1),
1695 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1696 .RESVAL (1'h0),
1697 .Mubi (1'b0)
1698 ) u_recov_alert_val_8 (
1699 .clk_i (clk_i),
1700 .rst_ni (rst_ni),
1701
1702 // from register interface
1703 .we (recov_alert_we),
1704 .wd (recov_alert_val_8_wd),
1705
1706 // from internal hardware
1707 .de (hw2reg.recov_alert[8].de),
1708 .d (hw2reg.recov_alert[8].d),
1709
1710 // to internal hardware
1711 .qe (),
1712 .q (reg2hw.recov_alert[8].q),
1713 .ds (),
1714
1715 // to register interface (read)
1716 .qs (recov_alert_val_8_qs)
1717 );
1718
1719 // F[val_9]: 9:9
1720 prim_subreg #(
1721 .DW (1),
1722 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1723 .RESVAL (1'h0),
1724 .Mubi (1'b0)
1725 ) u_recov_alert_val_9 (
1726 .clk_i (clk_i),
1727 .rst_ni (rst_ni),
1728
1729 // from register interface
1730 .we (recov_alert_we),
1731 .wd (recov_alert_val_9_wd),
1732
1733 // from internal hardware
1734 .de (hw2reg.recov_alert[9].de),
1735 .d (hw2reg.recov_alert[9].d),
1736
1737 // to internal hardware
1738 .qe (),
1739 .q (reg2hw.recov_alert[9].q),
1740 .ds (),
1741
1742 // to register interface (read)
1743 .qs (recov_alert_val_9_qs)
1744 );
1745
1746 // F[val_10]: 10:10
1747 prim_subreg #(
1748 .DW (1),
1749 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1750 .RESVAL (1'h0),
1751 .Mubi (1'b0)
1752 ) u_recov_alert_val_10 (
1753 .clk_i (clk_i),
1754 .rst_ni (rst_ni),
1755
1756 // from register interface
1757 .we (recov_alert_we),
1758 .wd (recov_alert_val_10_wd),
1759
1760 // from internal hardware
1761 .de (hw2reg.recov_alert[10].de),
1762 .d (hw2reg.recov_alert[10].d),
1763
1764 // to internal hardware
1765 .qe (),
1766 .q (reg2hw.recov_alert[10].q),
1767 .ds (),
1768
1769 // to register interface (read)
1770 .qs (recov_alert_val_10_qs)
1771 );
1772
1773
1774 // Subregister 0 of Multireg fatal_alert
1775 // R[fatal_alert]: V(False)
1776 // F[val_0]: 0:0
1777 prim_subreg #(
1778 .DW (1),
1779 .SwAccess(prim_subreg_pkg::SwAccessRO),
1780 .RESVAL (1'h0),
1781 .Mubi (1'b0)
1782 ) u_fatal_alert_val_0 (
1783 .clk_i (clk_i),
1784 .rst_ni (rst_ni),
1785
1786 // from register interface
1787 .we (1'b0),
1788 .wd ('0),
1789
1790 // from internal hardware
1791 .de (hw2reg.fatal_alert[0].de),
1792 .d (hw2reg.fatal_alert[0].d),
1793
1794 // to internal hardware
1795 .qe (),
1796 .q (reg2hw.fatal_alert[0].q),
1797 .ds (),
1798
1799 // to register interface (read)
1800 .qs (fatal_alert_val_0_qs)
1801 );
1802
1803 // F[val_1]: 1:1
1804 prim_subreg #(
1805 .DW (1),
1806 .SwAccess(prim_subreg_pkg::SwAccessRO),
1807 .RESVAL (1'h0),
1808 .Mubi (1'b0)
1809 ) u_fatal_alert_val_1 (
1810 .clk_i (clk_i),
1811 .rst_ni (rst_ni),
1812
1813 // from register interface
1814 .we (1'b0),
1815 .wd ('0),
1816
1817 // from internal hardware
1818 .de (hw2reg.fatal_alert[1].de),
1819 .d (hw2reg.fatal_alert[1].d),
1820
1821 // to internal hardware
1822 .qe (),
1823 .q (reg2hw.fatal_alert[1].q),
1824 .ds (),
1825
1826 // to register interface (read)
1827 .qs (fatal_alert_val_1_qs)
1828 );
1829
1830 // F[val_2]: 2:2
1831 prim_subreg #(
1832 .DW (1),
1833 .SwAccess(prim_subreg_pkg::SwAccessRO),
1834 .RESVAL (1'h0),
1835 .Mubi (1'b0)
1836 ) u_fatal_alert_val_2 (
1837 .clk_i (clk_i),
1838 .rst_ni (rst_ni),
1839
1840 // from register interface
1841 .we (1'b0),
1842 .wd ('0),
1843
1844 // from internal hardware
1845 .de (hw2reg.fatal_alert[2].de),
1846 .d (hw2reg.fatal_alert[2].d),
1847
1848 // to internal hardware
1849 .qe (),
1850 .q (reg2hw.fatal_alert[2].q),
1851 .ds (),
1852
1853 // to register interface (read)
1854 .qs (fatal_alert_val_2_qs)
1855 );
1856
1857 // F[val_3]: 3:3
1858 prim_subreg #(
1859 .DW (1),
1860 .SwAccess(prim_subreg_pkg::SwAccessRO),
1861 .RESVAL (1'h0),
1862 .Mubi (1'b0)
1863 ) u_fatal_alert_val_3 (
1864 .clk_i (clk_i),
1865 .rst_ni (rst_ni),
1866
1867 // from register interface
1868 .we (1'b0),
1869 .wd ('0),
1870
1871 // from internal hardware
1872 .de (hw2reg.fatal_alert[3].de),
1873 .d (hw2reg.fatal_alert[3].d),
1874
1875 // to internal hardware
1876 .qe (),
1877 .q (reg2hw.fatal_alert[3].q),
1878 .ds (),
1879
1880 // to register interface (read)
1881 .qs (fatal_alert_val_3_qs)
1882 );
1883
1884 // F[val_4]: 4:4
1885 prim_subreg #(
1886 .DW (1),
1887 .SwAccess(prim_subreg_pkg::SwAccessRO),
1888 .RESVAL (1'h0),
1889 .Mubi (1'b0)
1890 ) u_fatal_alert_val_4 (
1891 .clk_i (clk_i),
1892 .rst_ni (rst_ni),
1893
1894 // from register interface
1895 .we (1'b0),
1896 .wd ('0),
1897
1898 // from internal hardware
1899 .de (hw2reg.fatal_alert[4].de),
1900 .d (hw2reg.fatal_alert[4].d),
1901
1902 // to internal hardware
1903 .qe (),
1904 .q (reg2hw.fatal_alert[4].q),
1905 .ds (),
1906
1907 // to register interface (read)
1908 .qs (fatal_alert_val_4_qs)
1909 );
1910
1911 // F[val_5]: 5:5
1912 prim_subreg #(
1913 .DW (1),
1914 .SwAccess(prim_subreg_pkg::SwAccessRO),
1915 .RESVAL (1'h0),
1916 .Mubi (1'b0)
1917 ) u_fatal_alert_val_5 (
1918 .clk_i (clk_i),
1919 .rst_ni (rst_ni),
1920
1921 // from register interface
1922 .we (1'b0),
1923 .wd ('0),
1924
1925 // from internal hardware
1926 .de (hw2reg.fatal_alert[5].de),
1927 .d (hw2reg.fatal_alert[5].d),
1928
1929 // to internal hardware
1930 .qe (),
1931 .q (reg2hw.fatal_alert[5].q),
1932 .ds (),
1933
1934 // to register interface (read)
1935 .qs (fatal_alert_val_5_qs)
1936 );
1937
1938 // F[val_6]: 6:6
1939 prim_subreg #(
1940 .DW (1),
1941 .SwAccess(prim_subreg_pkg::SwAccessRO),
1942 .RESVAL (1'h0),
1943 .Mubi (1'b0)
1944 ) u_fatal_alert_val_6 (
1945 .clk_i (clk_i),
1946 .rst_ni (rst_ni),
1947
1948 // from register interface
1949 .we (1'b0),
1950 .wd ('0),
1951
1952 // from internal hardware
1953 .de (hw2reg.fatal_alert[6].de),
1954 .d (hw2reg.fatal_alert[6].d),
1955
1956 // to internal hardware
1957 .qe (),
1958 .q (reg2hw.fatal_alert[6].q),
1959 .ds (),
1960
1961 // to register interface (read)
1962 .qs (fatal_alert_val_6_qs)
1963 );
1964
1965 // F[val_7]: 7:7
1966 prim_subreg #(
1967 .DW (1),
1968 .SwAccess(prim_subreg_pkg::SwAccessRO),
1969 .RESVAL (1'h0),
1970 .Mubi (1'b0)
1971 ) u_fatal_alert_val_7 (
1972 .clk_i (clk_i),
1973 .rst_ni (rst_ni),
1974
1975 // from register interface
1976 .we (1'b0),
1977 .wd ('0),
1978
1979 // from internal hardware
1980 .de (hw2reg.fatal_alert[7].de),
1981 .d (hw2reg.fatal_alert[7].d),
1982
1983 // to internal hardware
1984 .qe (),
1985 .q (reg2hw.fatal_alert[7].q),
1986 .ds (),
1987
1988 // to register interface (read)
1989 .qs (fatal_alert_val_7_qs)
1990 );
1991
1992 // F[val_8]: 8:8
1993 prim_subreg #(
1994 .DW (1),
1995 .SwAccess(prim_subreg_pkg::SwAccessRO),
1996 .RESVAL (1'h0),
1997 .Mubi (1'b0)
1998 ) u_fatal_alert_val_8 (
1999 .clk_i (clk_i),
2000 .rst_ni (rst_ni),
2001
2002 // from register interface
2003 .we (1'b0),
2004 .wd ('0),
2005
2006 // from internal hardware
2007 .de (hw2reg.fatal_alert[8].de),
2008 .d (hw2reg.fatal_alert[8].d),
2009
2010 // to internal hardware
2011 .qe (),
2012 .q (reg2hw.fatal_alert[8].q),
2013 .ds (),
2014
2015 // to register interface (read)
2016 .qs (fatal_alert_val_8_qs)
2017 );
2018
2019 // F[val_9]: 9:9
2020 prim_subreg #(
2021 .DW (1),
2022 .SwAccess(prim_subreg_pkg::SwAccessRO),
2023 .RESVAL (1'h0),
2024 .Mubi (1'b0)
2025 ) u_fatal_alert_val_9 (
2026 .clk_i (clk_i),
2027 .rst_ni (rst_ni),
2028
2029 // from register interface
2030 .we (1'b0),
2031 .wd ('0),
2032
2033 // from internal hardware
2034 .de (hw2reg.fatal_alert[9].de),
2035 .d (hw2reg.fatal_alert[9].d),
2036
2037 // to internal hardware
2038 .qe (),
2039 .q (reg2hw.fatal_alert[9].q),
2040 .ds (),
2041
2042 // to register interface (read)
2043 .qs (fatal_alert_val_9_qs)
2044 );
2045
2046 // F[val_10]: 10:10
2047 prim_subreg #(
2048 .DW (1),
2049 .SwAccess(prim_subreg_pkg::SwAccessRO),
2050 .RESVAL (1'h0),
2051 .Mubi (1'b0)
2052 ) u_fatal_alert_val_10 (
2053 .clk_i (clk_i),
2054 .rst_ni (rst_ni),
2055
2056 // from register interface
2057 .we (1'b0),
2058 .wd ('0),
2059
2060 // from internal hardware
2061 .de (hw2reg.fatal_alert[10].de),
2062 .d (hw2reg.fatal_alert[10].d),
2063
2064 // to internal hardware
2065 .qe (),
2066 .q (reg2hw.fatal_alert[10].q),
2067 .ds (),
2068
2069 // to register interface (read)
2070 .qs (fatal_alert_val_10_qs)
2071 );
2072
2073 // F[val_11]: 11:11
2074 prim_subreg #(
2075 .DW (1),
2076 .SwAccess(prim_subreg_pkg::SwAccessRO),
2077 .RESVAL (1'h0),
2078 .Mubi (1'b0)
2079 ) u_fatal_alert_val_11 (
2080 .clk_i (clk_i),
2081 .rst_ni (rst_ni),
2082
2083 // from register interface
2084 .we (1'b0),
2085 .wd ('0),
2086
2087 // from internal hardware
2088 .de (hw2reg.fatal_alert[11].de),
2089 .d (hw2reg.fatal_alert[11].d),
2090
2091 // to internal hardware
2092 .qe (),
2093 .q (reg2hw.fatal_alert[11].q),
2094 .ds (),
2095
2096 // to register interface (read)
2097 .qs (fatal_alert_val_11_qs)
2098 );
2099
2100
2101 // R[status]: V(False)
2102 // F[ast_init_done]: 0:0
2103 prim_subreg #(
2104 .DW (1),
2105 .SwAccess(prim_subreg_pkg::SwAccessRO),
2106 .RESVAL (1'h0),
2107 .Mubi (1'b0)
2108 ) u_status_ast_init_done (
2109 .clk_i (clk_i),
2110 .rst_ni (rst_ni),
2111
2112 // from register interface
2113 .we (1'b0),
2114 .wd ('0),
2115
2116 // from internal hardware
2117 .de (hw2reg.status.ast_init_done.de),
2118 .d (hw2reg.status.ast_init_done.d),
2119
2120 // to internal hardware
2121 .qe (),
2122 .q (),
2123 .ds (),
2124
2125 // to register interface (read)
2126 .qs (status_ast_init_done_qs)
2127 );
2128
2129 // F[io_pok]: 2:1
2130 prim_subreg #(
2131 .DW (2),
2132 .SwAccess(prim_subreg_pkg::SwAccessRO),
2133 .RESVAL (2'h0),
2134 .Mubi (1'b0)
2135 ) u_status_io_pok (
2136 .clk_i (clk_i),
2137 .rst_ni (rst_ni),
2138
2139 // from register interface
2140 .we (1'b0),
2141 .wd ('0),
2142
2143 // from internal hardware
2144 .de (hw2reg.status.io_pok.de),
2145 .d (hw2reg.status.io_pok.d),
2146
2147 // to internal hardware
2148 .qe (),
2149 .q (),
2150 .ds (),
2151
2152 // to register interface (read)
2153 .qs (status_io_pok_qs)
2154 );
2155
2156
2157 // Subregister 0 of Multireg manual_pad_attr_regwen
2158 // R[manual_pad_attr_regwen_0]: V(False)
2159 prim_subreg #(
2160 .DW (1),
2161 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2162 .RESVAL (1'h1),
2163 .Mubi (1'b0)
2164 ) u_manual_pad_attr_regwen_0 (
2165 .clk_i (clk_i),
2166 .rst_ni (rst_ni),
2167
2168 // from register interface
2169 .we (manual_pad_attr_regwen_0_we),
2170 .wd (manual_pad_attr_regwen_0_wd),
2171
2172 // from internal hardware
2173 .de (1'b0),
2174 .d ('0),
2175
2176 // to internal hardware
2177 .qe (),
2178 .q (),
2179 .ds (),
2180
2181 // to register interface (read)
2182 .qs (manual_pad_attr_regwen_0_qs)
2183 );
2184
2185
2186 // Subregister 1 of Multireg manual_pad_attr_regwen
2187 // R[manual_pad_attr_regwen_1]: V(False)
2188 prim_subreg #(
2189 .DW (1),
2190 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2191 .RESVAL (1'h1),
2192 .Mubi (1'b0)
2193 ) u_manual_pad_attr_regwen_1 (
2194 .clk_i (clk_i),
2195 .rst_ni (rst_ni),
2196
2197 // from register interface
2198 .we (manual_pad_attr_regwen_1_we),
2199 .wd (manual_pad_attr_regwen_1_wd),
2200
2201 // from internal hardware
2202 .de (1'b0),
2203 .d ('0),
2204
2205 // to internal hardware
2206 .qe (),
2207 .q (),
2208 .ds (),
2209
2210 // to register interface (read)
2211 .qs (manual_pad_attr_regwen_1_qs)
2212 );
2213
2214
2215 // Subregister 2 of Multireg manual_pad_attr_regwen
2216 // R[manual_pad_attr_regwen_2]: V(False)
2217 prim_subreg #(
2218 .DW (1),
2219 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2220 .RESVAL (1'h1),
2221 .Mubi (1'b0)
2222 ) u_manual_pad_attr_regwen_2 (
2223 .clk_i (clk_i),
2224 .rst_ni (rst_ni),
2225
2226 // from register interface
2227 .we (manual_pad_attr_regwen_2_we),
2228 .wd (manual_pad_attr_regwen_2_wd),
2229
2230 // from internal hardware
2231 .de (1'b0),
2232 .d ('0),
2233
2234 // to internal hardware
2235 .qe (),
2236 .q (),
2237 .ds (),
2238
2239 // to register interface (read)
2240 .qs (manual_pad_attr_regwen_2_qs)
2241 );
2242
2243
2244 // Subregister 3 of Multireg manual_pad_attr_regwen
2245 // R[manual_pad_attr_regwen_3]: V(False)
2246 prim_subreg #(
2247 .DW (1),
2248 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2249 .RESVAL (1'h1),
2250 .Mubi (1'b0)
2251 ) u_manual_pad_attr_regwen_3 (
2252 .clk_i (clk_i),
2253 .rst_ni (rst_ni),
2254
2255 // from register interface
2256 .we (manual_pad_attr_regwen_3_we),
2257 .wd (manual_pad_attr_regwen_3_wd),
2258
2259 // from internal hardware
2260 .de (1'b0),
2261 .d ('0),
2262
2263 // to internal hardware
2264 .qe (),
2265 .q (),
2266 .ds (),
2267
2268 // to register interface (read)
2269 .qs (manual_pad_attr_regwen_3_qs)
2270 );
2271
2272
2273 // Subregister 0 of Multireg manual_pad_attr
2274 // R[manual_pad_attr_0]: V(True)
2275 logic manual_pad_attr_0_qe;
2276 logic [2:0] manual_pad_attr_0_flds_we;
2277 1/1 assign manual_pad_attr_0_qe = &manual_pad_attr_0_flds_we;
Tests: T23 T24 T25
2278 // Create REGWEN-gated WE signal
2279 logic manual_pad_attr_0_gated_we;
2280 1/1 assign manual_pad_attr_0_gated_we = manual_pad_attr_0_we & manual_pad_attr_regwen_0_qs;
Tests: T23 T24 T25
2281 // F[pull_en_0]: 2:2
2282 prim_subreg_ext #(
2283 .DW (1)
2284 ) u_manual_pad_attr_0_pull_en_0 (
2285 .re (manual_pad_attr_0_re),
2286 .we (manual_pad_attr_0_gated_we),
2287 .wd (manual_pad_attr_0_pull_en_0_wd),
2288 .d (hw2reg.manual_pad_attr[0].pull_en.d),
2289 .qre (),
2290 .qe (manual_pad_attr_0_flds_we[0]),
2291 .q (reg2hw.manual_pad_attr[0].pull_en.q),
2292 .ds (),
2293 .qs (manual_pad_attr_0_pull_en_0_qs)
2294 );
2295 1/1 assign reg2hw.manual_pad_attr[0].pull_en.qe = manual_pad_attr_0_qe;
Tests: T23 T24 T25
2296
2297 // F[pull_select_0]: 3:3
2298 prim_subreg_ext #(
2299 .DW (1)
2300 ) u_manual_pad_attr_0_pull_select_0 (
2301 .re (manual_pad_attr_0_re),
2302 .we (manual_pad_attr_0_gated_we),
2303 .wd (manual_pad_attr_0_pull_select_0_wd),
2304 .d (hw2reg.manual_pad_attr[0].pull_select.d),
2305 .qre (),
2306 .qe (manual_pad_attr_0_flds_we[1]),
2307 .q (reg2hw.manual_pad_attr[0].pull_select.q),
2308 .ds (),
2309 .qs (manual_pad_attr_0_pull_select_0_qs)
2310 );
2311 1/1 assign reg2hw.manual_pad_attr[0].pull_select.qe = manual_pad_attr_0_qe;
Tests: T23 T24 T25
2312
2313 // F[input_disable_0]: 7:7
2314 prim_subreg_ext #(
2315 .DW (1)
2316 ) u_manual_pad_attr_0_input_disable_0 (
2317 .re (manual_pad_attr_0_re),
2318 .we (manual_pad_attr_0_gated_we),
2319 .wd (manual_pad_attr_0_input_disable_0_wd),
2320 .d (hw2reg.manual_pad_attr[0].input_disable.d),
2321 .qre (),
2322 .qe (manual_pad_attr_0_flds_we[2]),
2323 .q (reg2hw.manual_pad_attr[0].input_disable.q),
2324 .ds (),
2325 .qs (manual_pad_attr_0_input_disable_0_qs)
2326 );
2327 1/1 assign reg2hw.manual_pad_attr[0].input_disable.qe = manual_pad_attr_0_qe;
Tests: T23 T24 T25
2328
2329
2330 // Subregister 1 of Multireg manual_pad_attr
2331 // R[manual_pad_attr_1]: V(True)
2332 logic manual_pad_attr_1_qe;
2333 logic [2:0] manual_pad_attr_1_flds_we;
2334 1/1 assign manual_pad_attr_1_qe = &manual_pad_attr_1_flds_we;
Tests: T23 T24 T25
2335 // Create REGWEN-gated WE signal
2336 logic manual_pad_attr_1_gated_we;
2337 1/1 assign manual_pad_attr_1_gated_we = manual_pad_attr_1_we & manual_pad_attr_regwen_1_qs;
Tests: T23 T24 T25
2338 // F[pull_en_1]: 2:2
2339 prim_subreg_ext #(
2340 .DW (1)
2341 ) u_manual_pad_attr_1_pull_en_1 (
2342 .re (manual_pad_attr_1_re),
2343 .we (manual_pad_attr_1_gated_we),
2344 .wd (manual_pad_attr_1_pull_en_1_wd),
2345 .d (hw2reg.manual_pad_attr[1].pull_en.d),
2346 .qre (),
2347 .qe (manual_pad_attr_1_flds_we[0]),
2348 .q (reg2hw.manual_pad_attr[1].pull_en.q),
2349 .ds (),
2350 .qs (manual_pad_attr_1_pull_en_1_qs)
2351 );
2352 1/1 assign reg2hw.manual_pad_attr[1].pull_en.qe = manual_pad_attr_1_qe;
Tests: T23 T24 T25
2353
2354 // F[pull_select_1]: 3:3
2355 prim_subreg_ext #(
2356 .DW (1)
2357 ) u_manual_pad_attr_1_pull_select_1 (
2358 .re (manual_pad_attr_1_re),
2359 .we (manual_pad_attr_1_gated_we),
2360 .wd (manual_pad_attr_1_pull_select_1_wd),
2361 .d (hw2reg.manual_pad_attr[1].pull_select.d),
2362 .qre (),
2363 .qe (manual_pad_attr_1_flds_we[1]),
2364 .q (reg2hw.manual_pad_attr[1].pull_select.q),
2365 .ds (),
2366 .qs (manual_pad_attr_1_pull_select_1_qs)
2367 );
2368 1/1 assign reg2hw.manual_pad_attr[1].pull_select.qe = manual_pad_attr_1_qe;
Tests: T23 T24 T25
2369
2370 // F[input_disable_1]: 7:7
2371 prim_subreg_ext #(
2372 .DW (1)
2373 ) u_manual_pad_attr_1_input_disable_1 (
2374 .re (manual_pad_attr_1_re),
2375 .we (manual_pad_attr_1_gated_we),
2376 .wd (manual_pad_attr_1_input_disable_1_wd),
2377 .d (hw2reg.manual_pad_attr[1].input_disable.d),
2378 .qre (),
2379 .qe (manual_pad_attr_1_flds_we[2]),
2380 .q (reg2hw.manual_pad_attr[1].input_disable.q),
2381 .ds (),
2382 .qs (manual_pad_attr_1_input_disable_1_qs)
2383 );
2384 1/1 assign reg2hw.manual_pad_attr[1].input_disable.qe = manual_pad_attr_1_qe;
Tests: T23 T24 T25
2385
2386
2387 // Subregister 2 of Multireg manual_pad_attr
2388 // R[manual_pad_attr_2]: V(True)
2389 logic manual_pad_attr_2_qe;
2390 logic [2:0] manual_pad_attr_2_flds_we;
2391 1/1 assign manual_pad_attr_2_qe = &manual_pad_attr_2_flds_we;
Tests: T23 T24 T25
2392 // Create REGWEN-gated WE signal
2393 logic manual_pad_attr_2_gated_we;
2394 1/1 assign manual_pad_attr_2_gated_we = manual_pad_attr_2_we & manual_pad_attr_regwen_2_qs;
Tests: T23 T24 T25
2395 // F[pull_en_2]: 2:2
2396 prim_subreg_ext #(
2397 .DW (1)
2398 ) u_manual_pad_attr_2_pull_en_2 (
2399 .re (manual_pad_attr_2_re),
2400 .we (manual_pad_attr_2_gated_we),
2401 .wd (manual_pad_attr_2_pull_en_2_wd),
2402 .d (hw2reg.manual_pad_attr[2].pull_en.d),
2403 .qre (),
2404 .qe (manual_pad_attr_2_flds_we[0]),
2405 .q (reg2hw.manual_pad_attr[2].pull_en.q),
2406 .ds (),
2407 .qs (manual_pad_attr_2_pull_en_2_qs)
2408 );
2409 1/1 assign reg2hw.manual_pad_attr[2].pull_en.qe = manual_pad_attr_2_qe;
Tests: T23 T24 T25
2410
2411 // F[pull_select_2]: 3:3
2412 prim_subreg_ext #(
2413 .DW (1)
2414 ) u_manual_pad_attr_2_pull_select_2 (
2415 .re (manual_pad_attr_2_re),
2416 .we (manual_pad_attr_2_gated_we),
2417 .wd (manual_pad_attr_2_pull_select_2_wd),
2418 .d (hw2reg.manual_pad_attr[2].pull_select.d),
2419 .qre (),
2420 .qe (manual_pad_attr_2_flds_we[1]),
2421 .q (reg2hw.manual_pad_attr[2].pull_select.q),
2422 .ds (),
2423 .qs (manual_pad_attr_2_pull_select_2_qs)
2424 );
2425 1/1 assign reg2hw.manual_pad_attr[2].pull_select.qe = manual_pad_attr_2_qe;
Tests: T23 T24 T25
2426
2427 // F[input_disable_2]: 7:7
2428 prim_subreg_ext #(
2429 .DW (1)
2430 ) u_manual_pad_attr_2_input_disable_2 (
2431 .re (manual_pad_attr_2_re),
2432 .we (manual_pad_attr_2_gated_we),
2433 .wd (manual_pad_attr_2_input_disable_2_wd),
2434 .d (hw2reg.manual_pad_attr[2].input_disable.d),
2435 .qre (),
2436 .qe (manual_pad_attr_2_flds_we[2]),
2437 .q (reg2hw.manual_pad_attr[2].input_disable.q),
2438 .ds (),
2439 .qs (manual_pad_attr_2_input_disable_2_qs)
2440 );
2441 1/1 assign reg2hw.manual_pad_attr[2].input_disable.qe = manual_pad_attr_2_qe;
Tests: T23 T24 T25
2442
2443
2444 // Subregister 3 of Multireg manual_pad_attr
2445 // R[manual_pad_attr_3]: V(True)
2446 logic manual_pad_attr_3_qe;
2447 logic [2:0] manual_pad_attr_3_flds_we;
2448 1/1 assign manual_pad_attr_3_qe = &manual_pad_attr_3_flds_we;
Tests: T23 T24 T25
2449 // Create REGWEN-gated WE signal
2450 logic manual_pad_attr_3_gated_we;
2451 1/1 assign manual_pad_attr_3_gated_we = manual_pad_attr_3_we & manual_pad_attr_regwen_3_qs;
Tests: T23 T24 T25
2452 // F[pull_en_3]: 2:2
2453 prim_subreg_ext #(
2454 .DW (1)
2455 ) u_manual_pad_attr_3_pull_en_3 (
2456 .re (manual_pad_attr_3_re),
2457 .we (manual_pad_attr_3_gated_we),
2458 .wd (manual_pad_attr_3_pull_en_3_wd),
2459 .d (hw2reg.manual_pad_attr[3].pull_en.d),
2460 .qre (),
2461 .qe (manual_pad_attr_3_flds_we[0]),
2462 .q (reg2hw.manual_pad_attr[3].pull_en.q),
2463 .ds (),
2464 .qs (manual_pad_attr_3_pull_en_3_qs)
2465 );
2466 1/1 assign reg2hw.manual_pad_attr[3].pull_en.qe = manual_pad_attr_3_qe;
Tests: T23 T24 T25
2467
2468 // F[pull_select_3]: 3:3
2469 prim_subreg_ext #(
2470 .DW (1)
2471 ) u_manual_pad_attr_3_pull_select_3 (
2472 .re (manual_pad_attr_3_re),
2473 .we (manual_pad_attr_3_gated_we),
2474 .wd (manual_pad_attr_3_pull_select_3_wd),
2475 .d (hw2reg.manual_pad_attr[3].pull_select.d),
2476 .qre (),
2477 .qe (manual_pad_attr_3_flds_we[1]),
2478 .q (reg2hw.manual_pad_attr[3].pull_select.q),
2479 .ds (),
2480 .qs (manual_pad_attr_3_pull_select_3_qs)
2481 );
2482 1/1 assign reg2hw.manual_pad_attr[3].pull_select.qe = manual_pad_attr_3_qe;
Tests: T23 T24 T25
2483
2484 // F[input_disable_3]: 7:7
2485 prim_subreg_ext #(
2486 .DW (1)
2487 ) u_manual_pad_attr_3_input_disable_3 (
2488 .re (manual_pad_attr_3_re),
2489 .we (manual_pad_attr_3_gated_we),
2490 .wd (manual_pad_attr_3_input_disable_3_wd),
2491 .d (hw2reg.manual_pad_attr[3].input_disable.d),
2492 .qre (),
2493 .qe (manual_pad_attr_3_flds_we[2]),
2494 .q (reg2hw.manual_pad_attr[3].input_disable.q),
2495 .ds (),
2496 .qs (manual_pad_attr_3_input_disable_3_qs)
2497 );
2498 1/1 assign reg2hw.manual_pad_attr[3].input_disable.qe = manual_pad_attr_3_qe;
Tests: T23 T24 T25
2499
2500
2501
2502 logic [28:0] addr_hit;
2503 always_comb begin
2504 1/1 addr_hit = '0;
Tests: T1 T2 T3
2505 1/1 addr_hit[ 0] = (reg_addr == SENSOR_CTRL_INTR_STATE_OFFSET);
Tests: T1 T2 T3
2506 1/1 addr_hit[ 1] = (reg_addr == SENSOR_CTRL_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
2507 1/1 addr_hit[ 2] = (reg_addr == SENSOR_CTRL_INTR_TEST_OFFSET);
Tests: T1 T2 T3
2508 1/1 addr_hit[ 3] = (reg_addr == SENSOR_CTRL_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
2509 1/1 addr_hit[ 4] = (reg_addr == SENSOR_CTRL_CFG_REGWEN_OFFSET);
Tests: T1 T2 T3
2510 1/1 addr_hit[ 5] = (reg_addr == SENSOR_CTRL_ALERT_TRIG_OFFSET);
Tests: T1 T2 T3
2511 1/1 addr_hit[ 6] = (reg_addr == SENSOR_CTRL_ALERT_EN_0_OFFSET);
Tests: T1 T2 T3
2512 1/1 addr_hit[ 7] = (reg_addr == SENSOR_CTRL_ALERT_EN_1_OFFSET);
Tests: T1 T2 T3
2513 1/1 addr_hit[ 8] = (reg_addr == SENSOR_CTRL_ALERT_EN_2_OFFSET);
Tests: T1 T2 T3
2514 1/1 addr_hit[ 9] = (reg_addr == SENSOR_CTRL_ALERT_EN_3_OFFSET);
Tests: T1 T2 T3
2515 1/1 addr_hit[10] = (reg_addr == SENSOR_CTRL_ALERT_EN_4_OFFSET);
Tests: T1 T2 T3
2516 1/1 addr_hit[11] = (reg_addr == SENSOR_CTRL_ALERT_EN_5_OFFSET);
Tests: T1 T2 T3
2517 1/1 addr_hit[12] = (reg_addr == SENSOR_CTRL_ALERT_EN_6_OFFSET);
Tests: T1 T2 T3
2518 1/1 addr_hit[13] = (reg_addr == SENSOR_CTRL_ALERT_EN_7_OFFSET);
Tests: T1 T2 T3
2519 1/1 addr_hit[14] = (reg_addr == SENSOR_CTRL_ALERT_EN_8_OFFSET);
Tests: T1 T2 T3
2520 1/1 addr_hit[15] = (reg_addr == SENSOR_CTRL_ALERT_EN_9_OFFSET);
Tests: T1 T2 T3
2521 1/1 addr_hit[16] = (reg_addr == SENSOR_CTRL_ALERT_EN_10_OFFSET);
Tests: T1 T2 T3
2522 1/1 addr_hit[17] = (reg_addr == SENSOR_CTRL_FATAL_ALERT_EN_OFFSET);
Tests: T1 T2 T3
2523 1/1 addr_hit[18] = (reg_addr == SENSOR_CTRL_RECOV_ALERT_OFFSET);
Tests: T1 T2 T3
2524 1/1 addr_hit[19] = (reg_addr == SENSOR_CTRL_FATAL_ALERT_OFFSET);
Tests: T1 T2 T3
2525 1/1 addr_hit[20] = (reg_addr == SENSOR_CTRL_STATUS_OFFSET);
Tests: T1 T2 T3
2526 1/1 addr_hit[21] = (reg_addr == SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_0_OFFSET);
Tests: T1 T2 T3
2527 1/1 addr_hit[22] = (reg_addr == SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_1_OFFSET);
Tests: T1 T2 T3
2528 1/1 addr_hit[23] = (reg_addr == SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_2_OFFSET);
Tests: T1 T2 T3
2529 1/1 addr_hit[24] = (reg_addr == SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_3_OFFSET);
Tests: T1 T2 T3
2530 1/1 addr_hit[25] = (reg_addr == SENSOR_CTRL_MANUAL_PAD_ATTR_0_OFFSET);
Tests: T1 T2 T3
2531 1/1 addr_hit[26] = (reg_addr == SENSOR_CTRL_MANUAL_PAD_ATTR_1_OFFSET);
Tests: T1 T2 T3
2532 1/1 addr_hit[27] = (reg_addr == SENSOR_CTRL_MANUAL_PAD_ATTR_2_OFFSET);
Tests: T1 T2 T3
2533 1/1 addr_hit[28] = (reg_addr == SENSOR_CTRL_MANUAL_PAD_ATTR_3_OFFSET);
Tests: T1 T2 T3
2534 end
2535
2536 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
2537
2538 // Check sub-word write is permitted
2539 always_comb begin
2540 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
2541 ((addr_hit[ 0] & (|(SENSOR_CTRL_PERMIT[ 0] & ~reg_be))) |
2542 (addr_hit[ 1] & (|(SENSOR_CTRL_PERMIT[ 1] & ~reg_be))) |
2543 (addr_hit[ 2] & (|(SENSOR_CTRL_PERMIT[ 2] & ~reg_be))) |
2544 (addr_hit[ 3] & (|(SENSOR_CTRL_PERMIT[ 3] & ~reg_be))) |
2545 (addr_hit[ 4] & (|(SENSOR_CTRL_PERMIT[ 4] & ~reg_be))) |
2546 (addr_hit[ 5] & (|(SENSOR_CTRL_PERMIT[ 5] & ~reg_be))) |
2547 (addr_hit[ 6] & (|(SENSOR_CTRL_PERMIT[ 6] & ~reg_be))) |
2548 (addr_hit[ 7] & (|(SENSOR_CTRL_PERMIT[ 7] & ~reg_be))) |
2549 (addr_hit[ 8] & (|(SENSOR_CTRL_PERMIT[ 8] & ~reg_be))) |
2550 (addr_hit[ 9] & (|(SENSOR_CTRL_PERMIT[ 9] & ~reg_be))) |
2551 (addr_hit[10] & (|(SENSOR_CTRL_PERMIT[10] & ~reg_be))) |
2552 (addr_hit[11] & (|(SENSOR_CTRL_PERMIT[11] & ~reg_be))) |
2553 (addr_hit[12] & (|(SENSOR_CTRL_PERMIT[12] & ~reg_be))) |
2554 (addr_hit[13] & (|(SENSOR_CTRL_PERMIT[13] & ~reg_be))) |
2555 (addr_hit[14] & (|(SENSOR_CTRL_PERMIT[14] & ~reg_be))) |
2556 (addr_hit[15] & (|(SENSOR_CTRL_PERMIT[15] & ~reg_be))) |
2557 (addr_hit[16] & (|(SENSOR_CTRL_PERMIT[16] & ~reg_be))) |
2558 (addr_hit[17] & (|(SENSOR_CTRL_PERMIT[17] & ~reg_be))) |
2559 (addr_hit[18] & (|(SENSOR_CTRL_PERMIT[18] & ~reg_be))) |
2560 (addr_hit[19] & (|(SENSOR_CTRL_PERMIT[19] & ~reg_be))) |
2561 (addr_hit[20] & (|(SENSOR_CTRL_PERMIT[20] & ~reg_be))) |
2562 (addr_hit[21] & (|(SENSOR_CTRL_PERMIT[21] & ~reg_be))) |
2563 (addr_hit[22] & (|(SENSOR_CTRL_PERMIT[22] & ~reg_be))) |
2564 (addr_hit[23] & (|(SENSOR_CTRL_PERMIT[23] & ~reg_be))) |
2565 (addr_hit[24] & (|(SENSOR_CTRL_PERMIT[24] & ~reg_be))) |
2566 (addr_hit[25] & (|(SENSOR_CTRL_PERMIT[25] & ~reg_be))) |
2567 (addr_hit[26] & (|(SENSOR_CTRL_PERMIT[26] & ~reg_be))) |
2568 (addr_hit[27] & (|(SENSOR_CTRL_PERMIT[27] & ~reg_be))) |
2569 (addr_hit[28] & (|(SENSOR_CTRL_PERMIT[28] & ~reg_be)))));
2570 end
2571
2572 // Generate write-enables
2573 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
2574
2575 1/1 assign intr_state_io_status_change_wd = reg_wdata[0];
Tests: T1 T2 T3
2576
2577 1/1 assign intr_state_init_status_change_wd = reg_wdata[1];
Tests: T1 T2 T3
2578 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
2579
2580 1/1 assign intr_enable_io_status_change_wd = reg_wdata[0];
Tests: T1 T2 T3
2581
2582 1/1 assign intr_enable_init_status_change_wd = reg_wdata[1];
Tests: T1 T2 T3
2583 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
2584
2585 1/1 assign intr_test_io_status_change_wd = reg_wdata[0];
Tests: T1 T2 T3
2586
2587 1/1 assign intr_test_init_status_change_wd = reg_wdata[1];
Tests: T1 T2 T3
2588 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
2589
2590 1/1 assign alert_test_recov_alert_wd = reg_wdata[0];
Tests: T1 T2 T3
2591
2592 1/1 assign alert_test_fatal_alert_wd = reg_wdata[1];
Tests: T1 T2 T3
2593 1/1 assign cfg_regwen_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
2594
2595 1/1 assign cfg_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
2596 1/1 assign alert_trig_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
2597
2598 1/1 assign alert_trig_val_0_wd = reg_wdata[0];
Tests: T1 T2 T3
2599
2600 1/1 assign alert_trig_val_1_wd = reg_wdata[1];
Tests: T1 T2 T3
2601
2602 1/1 assign alert_trig_val_2_wd = reg_wdata[2];
Tests: T1 T2 T3
2603
2604 1/1 assign alert_trig_val_3_wd = reg_wdata[3];
Tests: T1 T2 T3
2605
2606 1/1 assign alert_trig_val_4_wd = reg_wdata[4];
Tests: T1 T2 T3
2607
2608 1/1 assign alert_trig_val_5_wd = reg_wdata[5];
Tests: T1 T2 T3
2609
2610 1/1 assign alert_trig_val_6_wd = reg_wdata[6];
Tests: T1 T2 T3
2611
2612 1/1 assign alert_trig_val_7_wd = reg_wdata[7];
Tests: T1 T2 T3
2613
2614 1/1 assign alert_trig_val_8_wd = reg_wdata[8];
Tests: T1 T2 T3
2615
2616 1/1 assign alert_trig_val_9_wd = reg_wdata[9];
Tests: T1 T2 T3
2617
2618 1/1 assign alert_trig_val_10_wd = reg_wdata[10];
Tests: T1 T2 T3
2619 1/1 assign alert_en_0_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
2620
2621 1/1 assign alert_en_0_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2622 1/1 assign alert_en_1_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
2623
2624 1/1 assign alert_en_1_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2625 1/1 assign alert_en_2_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
2626
2627 1/1 assign alert_en_2_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2628 1/1 assign alert_en_3_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
2629
2630 1/1 assign alert_en_3_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2631 1/1 assign alert_en_4_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
2632
2633 1/1 assign alert_en_4_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2634 1/1 assign alert_en_5_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
2635
2636 1/1 assign alert_en_5_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2637 1/1 assign alert_en_6_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
2638
2639 1/1 assign alert_en_6_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2640 1/1 assign alert_en_7_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
2641
2642 1/1 assign alert_en_7_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2643 1/1 assign alert_en_8_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
2644
2645 1/1 assign alert_en_8_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2646 1/1 assign alert_en_9_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
2647
2648 1/1 assign alert_en_9_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2649 1/1 assign alert_en_10_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
2650
2651 1/1 assign alert_en_10_wd = reg_wdata[3:0];
Tests: T1 T2 T3
2652 1/1 assign fatal_alert_en_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
2653
2654 1/1 assign fatal_alert_en_val_0_wd = reg_wdata[0];
Tests: T1 T2 T3
2655
2656 1/1 assign fatal_alert_en_val_1_wd = reg_wdata[1];
Tests: T1 T2 T3
2657
2658 1/1 assign fatal_alert_en_val_2_wd = reg_wdata[2];
Tests: T1 T2 T3
2659
2660 1/1 assign fatal_alert_en_val_3_wd = reg_wdata[3];
Tests: T1 T2 T3
2661
2662 1/1 assign fatal_alert_en_val_4_wd = reg_wdata[4];
Tests: T1 T2 T3
2663
2664 1/1 assign fatal_alert_en_val_5_wd = reg_wdata[5];
Tests: T1 T2 T3
2665
2666 1/1 assign fatal_alert_en_val_6_wd = reg_wdata[6];
Tests: T1 T2 T3
2667
2668 1/1 assign fatal_alert_en_val_7_wd = reg_wdata[7];
Tests: T1 T2 T3
2669
2670 1/1 assign fatal_alert_en_val_8_wd = reg_wdata[8];
Tests: T1 T2 T3
2671
2672 1/1 assign fatal_alert_en_val_9_wd = reg_wdata[9];
Tests: T1 T2 T3
2673
2674 1/1 assign fatal_alert_en_val_10_wd = reg_wdata[10];
Tests: T1 T2 T3
2675 1/1 assign recov_alert_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
2676
2677 1/1 assign recov_alert_val_0_wd = reg_wdata[0];
Tests: T1 T2 T3
2678
2679 1/1 assign recov_alert_val_1_wd = reg_wdata[1];
Tests: T1 T2 T3
2680
2681 1/1 assign recov_alert_val_2_wd = reg_wdata[2];
Tests: T1 T2 T3
2682
2683 1/1 assign recov_alert_val_3_wd = reg_wdata[3];
Tests: T1 T2 T3
2684
2685 1/1 assign recov_alert_val_4_wd = reg_wdata[4];
Tests: T1 T2 T3
2686
2687 1/1 assign recov_alert_val_5_wd = reg_wdata[5];
Tests: T1 T2 T3
2688
2689 1/1 assign recov_alert_val_6_wd = reg_wdata[6];
Tests: T1 T2 T3
2690
2691 1/1 assign recov_alert_val_7_wd = reg_wdata[7];
Tests: T1 T2 T3
2692
2693 1/1 assign recov_alert_val_8_wd = reg_wdata[8];
Tests: T1 T2 T3
2694
2695 1/1 assign recov_alert_val_9_wd = reg_wdata[9];
Tests: T1 T2 T3
2696
2697 1/1 assign recov_alert_val_10_wd = reg_wdata[10];
Tests: T1 T2 T3
2698 1/1 assign manual_pad_attr_regwen_0_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
2699
2700 1/1 assign manual_pad_attr_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
2701 1/1 assign manual_pad_attr_regwen_1_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
2702
2703 1/1 assign manual_pad_attr_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
2704 1/1 assign manual_pad_attr_regwen_2_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
2705
2706 1/1 assign manual_pad_attr_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
2707 1/1 assign manual_pad_attr_regwen_3_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
2708
2709 1/1 assign manual_pad_attr_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
2710 1/1 assign manual_pad_attr_0_re = addr_hit[25] & reg_re & !reg_error;
Tests: T1 T2 T3
2711 1/1 assign manual_pad_attr_0_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
2712
2713 1/1 assign manual_pad_attr_0_pull_en_0_wd = reg_wdata[2];
Tests: T1 T2 T3
2714
2715 1/1 assign manual_pad_attr_0_pull_select_0_wd = reg_wdata[3];
Tests: T1 T2 T3
2716
2717 1/1 assign manual_pad_attr_0_input_disable_0_wd = reg_wdata[7];
Tests: T1 T2 T3
2718 1/1 assign manual_pad_attr_1_re = addr_hit[26] & reg_re & !reg_error;
Tests: T1 T2 T3
2719 1/1 assign manual_pad_attr_1_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
2720
2721 1/1 assign manual_pad_attr_1_pull_en_1_wd = reg_wdata[2];
Tests: T1 T2 T3
2722
2723 1/1 assign manual_pad_attr_1_pull_select_1_wd = reg_wdata[3];
Tests: T1 T2 T3
2724
2725 1/1 assign manual_pad_attr_1_input_disable_1_wd = reg_wdata[7];
Tests: T1 T2 T3
2726 1/1 assign manual_pad_attr_2_re = addr_hit[27] & reg_re & !reg_error;
Tests: T1 T2 T3
2727 1/1 assign manual_pad_attr_2_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
2728
2729 1/1 assign manual_pad_attr_2_pull_en_2_wd = reg_wdata[2];
Tests: T1 T2 T3
2730
2731 1/1 assign manual_pad_attr_2_pull_select_2_wd = reg_wdata[3];
Tests: T1 T2 T3
2732
2733 1/1 assign manual_pad_attr_2_input_disable_2_wd = reg_wdata[7];
Tests: T1 T2 T3
2734 1/1 assign manual_pad_attr_3_re = addr_hit[28] & reg_re & !reg_error;
Tests: T1 T2 T3
2735 1/1 assign manual_pad_attr_3_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
2736
2737 1/1 assign manual_pad_attr_3_pull_en_3_wd = reg_wdata[2];
Tests: T1 T2 T3
2738
2739 1/1 assign manual_pad_attr_3_pull_select_3_wd = reg_wdata[3];
Tests: T1 T2 T3
2740
2741 1/1 assign manual_pad_attr_3_input_disable_3_wd = reg_wdata[7];
Tests: T1 T2 T3
2742
2743 // Assign write-enables to checker logic vector.
2744 always_comb begin
2745 1/1 reg_we_check = '0;
Tests: T78 T171 T157
2746 1/1 reg_we_check[0] = intr_state_we;
Tests: T78 T171 T157
2747 1/1 reg_we_check[1] = intr_enable_we;
Tests: T78 T171 T157
2748 1/1 reg_we_check[2] = intr_test_we;
Tests: T78 T171 T157
2749 1/1 reg_we_check[3] = alert_test_we;
Tests: T78 T171 T157
2750 1/1 reg_we_check[4] = cfg_regwen_we;
Tests: T78 T171 T157
2751 1/1 reg_we_check[5] = alert_trig_we;
Tests: T78 T171 T157
2752 1/1 reg_we_check[6] = alert_en_0_gated_we;
Tests: T78 T171 T157
2753 1/1 reg_we_check[7] = alert_en_1_gated_we;
Tests: T78 T171 T157
2754 1/1 reg_we_check[8] = alert_en_2_gated_we;
Tests: T78 T171 T157
2755 1/1 reg_we_check[9] = alert_en_3_gated_we;
Tests: T78 T171 T157
2756 1/1 reg_we_check[10] = alert_en_4_gated_we;
Tests: T78 T171 T157
2757 1/1 reg_we_check[11] = alert_en_5_gated_we;
Tests: T78 T171 T157
2758 1/1 reg_we_check[12] = alert_en_6_gated_we;
Tests: T78 T171 T157
2759 1/1 reg_we_check[13] = alert_en_7_gated_we;
Tests: T78 T171 T157
2760 1/1 reg_we_check[14] = alert_en_8_gated_we;
Tests: T78 T171 T157
2761 1/1 reg_we_check[15] = alert_en_9_gated_we;
Tests: T78 T171 T157
2762 1/1 reg_we_check[16] = alert_en_10_gated_we;
Tests: T78 T171 T157
2763 1/1 reg_we_check[17] = fatal_alert_en_gated_we;
Tests: T78 T171 T157
2764 1/1 reg_we_check[18] = recov_alert_we;
Tests: T78 T171 T157
2765 1/1 reg_we_check[19] = 1'b0;
Tests: T78 T171 T157
2766 1/1 reg_we_check[20] = 1'b0;
Tests: T78 T171 T157
2767 1/1 reg_we_check[21] = manual_pad_attr_regwen_0_we;
Tests: T78 T171 T157
2768 1/1 reg_we_check[22] = manual_pad_attr_regwen_1_we;
Tests: T78 T171 T157
2769 1/1 reg_we_check[23] = manual_pad_attr_regwen_2_we;
Tests: T78 T171 T157
2770 1/1 reg_we_check[24] = manual_pad_attr_regwen_3_we;
Tests: T78 T171 T157
2771 1/1 reg_we_check[25] = manual_pad_attr_0_gated_we;
Tests: T78 T171 T157
2772 1/1 reg_we_check[26] = manual_pad_attr_1_gated_we;
Tests: T78 T171 T157
2773 1/1 reg_we_check[27] = manual_pad_attr_2_gated_we;
Tests: T78 T171 T157
2774 1/1 reg_we_check[28] = manual_pad_attr_3_gated_we;
Tests: T78 T171 T157
2775 end
2776
2777 // Read data return
2778 always_comb begin
2779 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
2780 1/1 unique case (1'b1)
Tests: T1 T2 T3
2781 addr_hit[0]: begin
2782 1/1 reg_rdata_next[0] = intr_state_io_status_change_qs;
Tests: T1 T2 T3
2783 1/1 reg_rdata_next[1] = intr_state_init_status_change_qs;
Tests: T1 T2 T3
2784 end
2785
2786 addr_hit[1]: begin
2787 1/1 reg_rdata_next[0] = intr_enable_io_status_change_qs;
Tests: T1 T2 T3
2788 1/1 reg_rdata_next[1] = intr_enable_init_status_change_qs;
Tests: T1 T2 T3
2789 end
2790
2791 addr_hit[2]: begin
2792 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
2793 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
2794 end
2795
2796 addr_hit[3]: begin
2797 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
2798 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
2799 end
2800
2801 addr_hit[4]: begin
2802 1/1 reg_rdata_next[0] = cfg_regwen_qs;
Tests: T1 T2 T3
2803 end
2804
2805 addr_hit[5]: begin
2806 1/1 reg_rdata_next[0] = alert_trig_val_0_qs;
Tests: T1 T2 T3
2807 1/1 reg_rdata_next[1] = alert_trig_val_1_qs;
Tests: T1 T2 T3
2808 1/1 reg_rdata_next[2] = alert_trig_val_2_qs;
Tests: T1 T2 T3
2809 1/1 reg_rdata_next[3] = alert_trig_val_3_qs;
Tests: T1 T2 T3
2810 1/1 reg_rdata_next[4] = alert_trig_val_4_qs;
Tests: T1 T2 T3
2811 1/1 reg_rdata_next[5] = alert_trig_val_5_qs;
Tests: T1 T2 T3
2812 1/1 reg_rdata_next[6] = alert_trig_val_6_qs;
Tests: T1 T2 T3
2813 1/1 reg_rdata_next[7] = alert_trig_val_7_qs;
Tests: T1 T2 T3
2814 1/1 reg_rdata_next[8] = alert_trig_val_8_qs;
Tests: T1 T2 T3
2815 1/1 reg_rdata_next[9] = alert_trig_val_9_qs;
Tests: T1 T2 T3
2816 1/1 reg_rdata_next[10] = alert_trig_val_10_qs;
Tests: T1 T2 T3
2817 end
2818
2819 addr_hit[6]: begin
2820 1/1 reg_rdata_next[3:0] = alert_en_0_qs;
Tests: T1 T2 T3
2821 end
2822
2823 addr_hit[7]: begin
2824 1/1 reg_rdata_next[3:0] = alert_en_1_qs;
Tests: T1 T2 T3
2825 end
2826
2827 addr_hit[8]: begin
2828 1/1 reg_rdata_next[3:0] = alert_en_2_qs;
Tests: T1 T2 T3
2829 end
2830
2831 addr_hit[9]: begin
2832 1/1 reg_rdata_next[3:0] = alert_en_3_qs;
Tests: T1 T2 T3
2833 end
2834
2835 addr_hit[10]: begin
2836 1/1 reg_rdata_next[3:0] = alert_en_4_qs;
Tests: T1 T2 T3
2837 end
2838
2839 addr_hit[11]: begin
2840 1/1 reg_rdata_next[3:0] = alert_en_5_qs;
Tests: T1 T2 T3
2841 end
2842
2843 addr_hit[12]: begin
2844 1/1 reg_rdata_next[3:0] = alert_en_6_qs;
Tests: T1 T2 T3
2845 end
2846
2847 addr_hit[13]: begin
2848 1/1 reg_rdata_next[3:0] = alert_en_7_qs;
Tests: T1 T2 T3
2849 end
2850
2851 addr_hit[14]: begin
2852 1/1 reg_rdata_next[3:0] = alert_en_8_qs;
Tests: T1 T2 T3
2853 end
2854
2855 addr_hit[15]: begin
2856 1/1 reg_rdata_next[3:0] = alert_en_9_qs;
Tests: T1 T2 T3
2857 end
2858
2859 addr_hit[16]: begin
2860 1/1 reg_rdata_next[3:0] = alert_en_10_qs;
Tests: T1 T2 T3
2861 end
2862
2863 addr_hit[17]: begin
2864 1/1 reg_rdata_next[0] = fatal_alert_en_val_0_qs;
Tests: T1 T2 T3
2865 1/1 reg_rdata_next[1] = fatal_alert_en_val_1_qs;
Tests: T1 T2 T3
2866 1/1 reg_rdata_next[2] = fatal_alert_en_val_2_qs;
Tests: T1 T2 T3
2867 1/1 reg_rdata_next[3] = fatal_alert_en_val_3_qs;
Tests: T1 T2 T3
2868 1/1 reg_rdata_next[4] = fatal_alert_en_val_4_qs;
Tests: T1 T2 T3
2869 1/1 reg_rdata_next[5] = fatal_alert_en_val_5_qs;
Tests: T1 T2 T3
2870 1/1 reg_rdata_next[6] = fatal_alert_en_val_6_qs;
Tests: T1 T2 T3
2871 1/1 reg_rdata_next[7] = fatal_alert_en_val_7_qs;
Tests: T1 T2 T3
2872 1/1 reg_rdata_next[8] = fatal_alert_en_val_8_qs;
Tests: T1 T2 T3
2873 1/1 reg_rdata_next[9] = fatal_alert_en_val_9_qs;
Tests: T1 T2 T3
2874 1/1 reg_rdata_next[10] = fatal_alert_en_val_10_qs;
Tests: T1 T2 T3
2875 end
2876
2877 addr_hit[18]: begin
2878 1/1 reg_rdata_next[0] = recov_alert_val_0_qs;
Tests: T1 T2 T3
2879 1/1 reg_rdata_next[1] = recov_alert_val_1_qs;
Tests: T1 T2 T3
2880 1/1 reg_rdata_next[2] = recov_alert_val_2_qs;
Tests: T1 T2 T3
2881 1/1 reg_rdata_next[3] = recov_alert_val_3_qs;
Tests: T1 T2 T3
2882 1/1 reg_rdata_next[4] = recov_alert_val_4_qs;
Tests: T1 T2 T3
2883 1/1 reg_rdata_next[5] = recov_alert_val_5_qs;
Tests: T1 T2 T3
2884 1/1 reg_rdata_next[6] = recov_alert_val_6_qs;
Tests: T1 T2 T3
2885 1/1 reg_rdata_next[7] = recov_alert_val_7_qs;
Tests: T1 T2 T3
2886 1/1 reg_rdata_next[8] = recov_alert_val_8_qs;
Tests: T1 T2 T3
2887 1/1 reg_rdata_next[9] = recov_alert_val_9_qs;
Tests: T1 T2 T3
2888 1/1 reg_rdata_next[10] = recov_alert_val_10_qs;
Tests: T1 T2 T3
2889 end
2890
2891 addr_hit[19]: begin
2892 1/1 reg_rdata_next[0] = fatal_alert_val_0_qs;
Tests: T1 T2 T3
2893 1/1 reg_rdata_next[1] = fatal_alert_val_1_qs;
Tests: T1 T2 T3
2894 1/1 reg_rdata_next[2] = fatal_alert_val_2_qs;
Tests: T1 T2 T3
2895 1/1 reg_rdata_next[3] = fatal_alert_val_3_qs;
Tests: T1 T2 T3
2896 1/1 reg_rdata_next[4] = fatal_alert_val_4_qs;
Tests: T1 T2 T3
2897 1/1 reg_rdata_next[5] = fatal_alert_val_5_qs;
Tests: T1 T2 T3
2898 1/1 reg_rdata_next[6] = fatal_alert_val_6_qs;
Tests: T1 T2 T3
2899 1/1 reg_rdata_next[7] = fatal_alert_val_7_qs;
Tests: T1 T2 T3
2900 1/1 reg_rdata_next[8] = fatal_alert_val_8_qs;
Tests: T1 T2 T3
2901 1/1 reg_rdata_next[9] = fatal_alert_val_9_qs;
Tests: T1 T2 T3
2902 1/1 reg_rdata_next[10] = fatal_alert_val_10_qs;
Tests: T1 T2 T3
2903 1/1 reg_rdata_next[11] = fatal_alert_val_11_qs;
Tests: T1 T2 T3
2904 end
2905
2906 addr_hit[20]: begin
2907 1/1 reg_rdata_next[0] = status_ast_init_done_qs;
Tests: T1 T2 T3
2908 1/1 reg_rdata_next[2:1] = status_io_pok_qs;
Tests: T1 T2 T3
2909 end
2910
2911 addr_hit[21]: begin
2912 1/1 reg_rdata_next[0] = manual_pad_attr_regwen_0_qs;
Tests: T1 T2 T3
2913 end
2914
2915 addr_hit[22]: begin
2916 1/1 reg_rdata_next[0] = manual_pad_attr_regwen_1_qs;
Tests: T1 T2 T3
2917 end
2918
2919 addr_hit[23]: begin
2920 1/1 reg_rdata_next[0] = manual_pad_attr_regwen_2_qs;
Tests: T1 T2 T3
2921 end
2922
2923 addr_hit[24]: begin
2924 1/1 reg_rdata_next[0] = manual_pad_attr_regwen_3_qs;
Tests: T1 T2 T3
2925 end
2926
2927 addr_hit[25]: begin
2928 1/1 reg_rdata_next[2] = manual_pad_attr_0_pull_en_0_qs;
Tests: T1 T2 T3
2929 1/1 reg_rdata_next[3] = manual_pad_attr_0_pull_select_0_qs;
Tests: T1 T2 T3
2930 1/1 reg_rdata_next[7] = manual_pad_attr_0_input_disable_0_qs;
Tests: T1 T2 T3
2931 end
2932
2933 addr_hit[26]: begin
2934 1/1 reg_rdata_next[2] = manual_pad_attr_1_pull_en_1_qs;
Tests: T1 T2 T3
2935 1/1 reg_rdata_next[3] = manual_pad_attr_1_pull_select_1_qs;
Tests: T1 T2 T3
2936 1/1 reg_rdata_next[7] = manual_pad_attr_1_input_disable_1_qs;
Tests: T1 T2 T3
2937 end
2938
2939 addr_hit[27]: begin
2940 1/1 reg_rdata_next[2] = manual_pad_attr_2_pull_en_2_qs;
Tests: T1 T2 T3
2941 1/1 reg_rdata_next[3] = manual_pad_attr_2_pull_select_2_qs;
Tests: T1 T2 T3
2942 1/1 reg_rdata_next[7] = manual_pad_attr_2_input_disable_2_qs;
Tests: T1 T2 T3
2943 end
2944
2945 addr_hit[28]: begin
2946 1/1 reg_rdata_next[2] = manual_pad_attr_3_pull_en_3_qs;
Tests: T1 T2 T3
2947 1/1 reg_rdata_next[3] = manual_pad_attr_3_pull_select_3_qs;
Tests: T1 T2 T3
2948 1/1 reg_rdata_next[7] = manual_pad_attr_3_input_disable_3_qs;
Tests: T1 T2 T3
2949 end
2950
2951 default: begin
2952 reg_rdata_next = '1;
2953 end
2954 endcase
2955 end
2956
2957 // shadow busy
2958 logic shadow_busy;
2959 assign shadow_busy = 1'b0;
2960
2961 // register busy
2962 unreachable assign reg_busy = shadow_busy;
2963
2964 // Unused signal tieoff
2965
2966 // wdata / byte enable are not always fully used
2967 // add a blanket unused statement to handle lint waivers
2968 logic unused_wdata;
2969 logic unused_be;
2970 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
2971 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3