Unified Coverage Report :: Cond split page

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 LINE       32800
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_11_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32801
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_12_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       32802
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_13_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T103,T322

 LINE       32803
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_14_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T103,T322

 LINE       32804
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_15_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T103,T322

 LINE       32805
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_16_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32806
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_17_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T324

 LINE       32807
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_18_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32808
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_19_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32809
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_20_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32810
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_21_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32811
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_22_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32812
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_23_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32813
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_24_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T324

 LINE       32814
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_25_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32815
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_26_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32816
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_27_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32817
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_28_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32818
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_29_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32819
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_30_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T322,T104

 LINE       32820
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_31_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T322,T324,T307

 LINE       32821
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_32_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T322,T104,T100

 LINE       32822
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_33_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T322,T104,T100

 LINE       32823
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_34_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T322,T104,T100

 LINE       32824
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_35_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T322,T104,T100

 LINE       32825
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_36_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T322,T104,T100

 LINE       32826
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_37_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T322,T104,T100

 LINE       32827
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_38_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T321,T378

 LINE       32828
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_39_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T321,T378

 LINE       32829
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_40_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T378,T100,T451

 LINE       32830
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_41_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T378,T363,T100

 LINE       32831
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_42_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T98,T230

 LINE       32832
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_43_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T321,T378

 LINE       32833
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_44_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T321,T378

 LINE       32834
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_45_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T321,T378

 LINE       32835
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_46_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T321,T378

 LINE       32836
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32837
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32838
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       32839
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       32840
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       32841
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T44,T11

 LINE       32842
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T78,T103

 LINE       32843
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T69,T155

 LINE       32844
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T69,T452

 LINE       32845
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T69,T434

 LINE       32846
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T18,T78

 LINE       32847
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T18,T78

 LINE       32848
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T78,T103

 LINE       32849
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T78,T103

 LINE       32850
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T44,T267

 LINE       32851
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T44,T267

 LINE       32852
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32853
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_1_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32854
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_2_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T44,T11

 LINE       32855
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_3_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       32856
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_4_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       32857
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_5_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       32858
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_6_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T452,T434

 LINE       32859
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_7_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T437,T453

 LINE       32860
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_8_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T267,T100,T56

 LINE       32861
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_9_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T267,T100,T56

 LINE       32862
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_10_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T267,T100

 LINE       32863
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_11_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T267,T100

 LINE       32864
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_12_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T267,T100,T56

 LINE       32865
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_13_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T56,T454

 LINE       32866
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_14_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T100,T56

 LINE       32867
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_15_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T100,T47

 LINE       32868
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T29,T100

 LINE       32869
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T45,T84,T186

 LINE       32870
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T45

 LINE       32871
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T100

 LINE       32872
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T100

 LINE       32873
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T100

 LINE       32874
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T45

 LINE       32875
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T45

 LINE       32876
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T45

 LINE       32877
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T5,T29

 LINE       32878
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T45,T84

 LINE       32879
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T45,T84

 LINE       32880
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T45,T84

 LINE       32881
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T100

 LINE       32882
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T45,T84

 LINE       32883
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32884
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32885
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32886
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32887
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32888
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32889
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32890
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32891
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32892
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32893
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32894
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32895
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32896
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32897
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32898
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32899
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32900
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32901
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32902
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32903
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32904
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32905
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32906
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32907
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32908
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32909
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T146,T20

 LINE       32910
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T20,T21

 LINE       32911
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T20,T21

 LINE       32912
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T20,T21

 LINE       32913
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T20,T21

 LINE       32914
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T20,T21

 LINE       32915
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T20,T21

 LINE       32916
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T20,T21

 LINE       32917
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T75

 LINE       32918
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T75

 LINE       32919
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T75

 LINE       32920
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T75

 LINE       32921
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T202

 LINE       32922
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T202

 LINE       32923
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T29,T202

 LINE       32924
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T5,T29

 LINE       32925
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32926
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32927
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32928
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32929
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32930
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32931
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32932
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32933
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20

 LINE       32934
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T202,T20