Go back

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T84
1	0	1	Covered	T44,T45,T84
1	1	0	Covered	T437,T556,T485
1	1	1	Covered	T378,T74,T126

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T84
1	0	1	Covered	T44,T45,T284
1	1	0	Covered	T437,T542,T434
1	1	1	Covered	T69,T437,T453

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T69,T437,T434
1	1	0	Covered	T633,T634,T635
1	1	1	Covered	T4,T10,T13

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T69,T404,T545
1	1	0	Covered	T636
1	1	1	Covered	T4,T10,T13

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T10,T13
1	0	1	Covered	T69,T98,T434
1	1	0	Covered	T637
1	1	1	Covered	T2,T3,T4