Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T72 T309 T315 | T72 T309 T315 | T72 T309 T316 | T72 T309 T316 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T72 T309 T315 | T128 T309 T129 | T128 T309 T129 | T128 T309 T129 | T128 T309 T129 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T128 T309 T129 | T65 T66 T309 | T65 T66 T309 | T65 T66 T309 | T65 T66 T309 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T65 T66 T309 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T39 T67 T68 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T11 T124 T220 | T124 T184 T185 | T124 T184 T185 | T124 T184 T185 | T124 T184 T185 | T14 T124 T51 | T124 T184 T185 | T124 T184 T185 | T60 T302 T135 | T60 T302 T135 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T59 T60 T302 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T61 T302 T62 | T61 T302 T62 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T61 T302 T62 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T63 T302 T64 | T63 T302 T64 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T63 T302 T64 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T4 T124 T132 | T124 T132 T184 | T124 T184 T185 | T124 T184 T185 | T124 T184 T185 | T321 T323 T232 | T44 T324 T267 | T302 T284 T319 | T45 T84 T186 | T124 T184 T185 | T124 T184 T185 | T124 T184 T185 | T124 T184 T185 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T5 T29 T322 | T70 T309 T228 | T136 T302 T325 | T279 T259 T302 | T258 T259 T232 | T171 T124 T326 | T124 T184 T185 | T6 T310 T143 | T6 T310 T143 | T310 T143 T302 | T310 T143 T302 | T6 T310 T143 | T302 T319 T320 | T311 T312 T302 | T302 T319 T320 | T302 T319 T320 | T124 T184 T185 | T124 T184 T185 | T124 T184 T185 | T313 T124 T176 | T124 T184 T185 | T302 T319 T320 | T302 T327 T328 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T327 T328 | T302 T319 T320 | T302 T327 T328 | T302 T319 T320
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T269 T270 T308 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T14 T30 T11 | T14 T269 T124 | T14 T269 T124 | T14 T11 T12 | T14 T11 T12 | T14 T269 T124 | T269 T124 T309 | T269 T124 T309 | T60 T269 T124 | T60 T269 T124 | T269 T124 T309 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T269 T124 T309 | T59 T60 T269 | T59 T269 T124 | T269 T124 T309 | T59 T269 T124 | T59 T269 T124 | T59 T269 T124 | T61 T269 T124 | T61 T269 T124 | T269 T124 T309 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T269 T124 T309 | T61 T269 T124 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T63 T269 T124 | T63 T269 T124 | T269 T124 T309 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T269 T124 T309 | T63 T269 T124 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T4 T269 T124 | T4 T269 T124 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T44 T45 T84 | T44 T45 T84 | T44 T45 T84 | T44 T45 T84 | T11 T12 T269 | T11 T12 T269 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T5 T29 T279 | T70 T269 T124 | T136 T269 T124 | T44 T45 T84 | T44 T45 T258 | T171 T269 T124 | T269 T124 T309 | T6 T310 T143 | T6 T310 T143 | T6 T310 T143 | T6 T310 T143 | T6 T310 T143 | T269 T124 T309 | T311 T312 T269 | T311 T312 T269 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T313 T269 T124 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T4 T5 T6 | T4 T72 T14 | T72 T128 T30 | T4 T14 T30 | T5 T6 T44 | T72 T128 T65 | T30 T39 T67 | T14 T30 T61 | T4 T61 T63 | T5 T44 T29 | T6 T310 T143 | T72 T128 T269 | T128 T65 T39 | T30 T39 T67 | T30 T269 T124 | T14 T30 T11 | T61 T59 T60 | T61 T63 T269 | T4 T63 T321 | T44 T45 T84 | T5 T29 T258 | T6 T310 T143 | T269 T124 T309 | T72 T269 T124 | T72 T128 T269 | T128 T65 T66 | T65 T39 T66 | T30 T39 T67 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T11 T269 | T14 T11 T12 | T59 T60 T269 | T61 T269 T124 | T61 T269 T124 | T63 T269 T124 | T63 T269 T124 | T4 T321 T323 | T44 T45 T11 | T269 T124 T309 | T269 T124 T309 | T5 T44 T29 | T6 T310 T143 | T313 T269 T124 | T269 T124 T309 | T72 T269 T124 | T72 T269 T124 | T72 T128 T269 | T128 T269 T124 | T128 T65 T66 | T65 T66 T269 | T65 T66 T269 | T39 T67 T68 | T39 T67 T68 | T30 T39 T67 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T14 T30 T11 | T14 T11 T12 | T60 T269 T124 | T60 T269 T124 | T59 T60 T269 | T59 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T4 T269 T124 | T321 T323 T232 | T44 T45 T84 | T11 T12 T269 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T5 T29 T136 | T44 T45 T258 | T6 T310 T143 | T6 T310 T143 | T269 T124 T309 | T313 T269 T124 | T269 T124 T309 | T269 T124 T309 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T65 T66 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T30 T39 T67 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T14 T30 T11 | T14 T269 T124 | T14 T11 T12 | T14 T269 T124 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T59 T60 T269 | T59 T269 T124 | T59 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T269 T124 T309 | T269 T124 T309 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T269 T124 T309 | T269 T124 T309 | T4 T269 T124 | T269 T124 T309 | T44 T45 T84 | T44 T45 T84 | T44 T45 T11 | T11 T12 T269 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T5 T29 T279 | T136 T70 T269 | T44 T45 T258 | T171 T269 T124 | T6 T310 T143 | T6 T310 T143 | T6 T310 T143 | T311 T312 T269 | T269 T124 T309 | T269 T124 T309 | T313 T269 T124 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T4 T5 T6 | T4 T72 T14 | T5 T6 T44 | T72 T128 T30 | T4 T14 T30 | T5 T6 T44 | T72 T128 T65 | T30 T39 T67 | T14 T30 T61 | T4 T61 T63 | T5 T44 T29 | T6 T310 T143 | T72 T128 T309 | T128 T65 T39 | T30 T39 T67 | T30 T302 T42 | T14 T30 T11 | T61 T59 T60 | T61 T63 T302 | T4 T63 T321 | T44 T45 T84 | T5 T29 T258 | T6 T310 T143 | T302 T327 T328 | T72 T309 T316 | T72 T128 T309 | T128 T65 T66 | T65 T39 T66 | T30 T39 T67 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T11 T124 | T14 T60 T124 | T59 T60 T302 | T61 T302 T62 | T61 T302 T62 | T63 T302 T64 | T63 T302 T64 | T4 T321 T323 | T44 T45 T84 | T309 T317 T318 | T309 T317 T318 | T5 T29 T258 | T6 T310 T143 | T313 T124 T302 | T302 T327 T328 | T302 T327 T328 | T72 T309 T316 | T72 T309 T316 | T72 T128 T309 | T128 T309 T129 | T128 T65 T66 | T65 T66 T309 | T65 T66 T309 | T39 T67 T68 | T309 T317 T318 | T30 T39 T67 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T11 T124 | T14 T124 T51 | T60 T124 T302 | T302 T319 T320 | T59 T60 T302 | T302 T319 T320 | T61 T302 T62 | T302 T319 T320 | T61 T302 T62 | T63 T302 T64 | T63 T302 T64 | T302 T319 T320 | T63 T302 T64 | T4 T124 T302 | T321 T323 T232 | T44 T45 T84 | T124 T309 T184 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T5 T29 T136 | T258 T279 T259 | T6 T310 T143 | T6 T310 T143 | T124 T302 T184 | T313 T124 T302 | T302 T319 T320 | T302 T327 T328 | T302 T327 T328 | T72 T309 T315 | T72 T309 T316 | T72 T309 T316 | T309 T317 T318 | T72 T309 T315 | T128 T309 T129 | T128 T309 T129 | T309 T317 T318 | T309 T317 T318 | T128 T65 T66 | T65 T66 T309 | T65 T66 T309 | T309 T317 T318 | T65 T66 T309 | T39 T67 T68 | T39 T67 T68 | T309 T317 T318 | T309 T317 T318 | T30 T39 T67 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T11 T124 | T124 T184 T185 | T124 T184 T185 | T14 T124 T51 | T60 T124 T302 | T60 T302 T135 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T59 T60 T302 | T302 T319 T320 | T302 T319 T320 | T61 T302 T62 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T61 T302 T62 | T302 T319 T320 | T302 T319 T320 | T63 T302 T64 | T63 T302 T64 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T63 T302 T64 | T302 T319 T320 | T302 T319 T320 | T4 T124 T132 | T124 T184 T185 | T321 T323 T232 | T44 T324 T267 | T45 T84 T186 | T124 T184 T185 | T124 T309 T184 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T5 T29 T322 | T136 T70 T309 | T258 T279 T259 | T171 T124 T326 | T6 T310 T143 | T310 T143 T302 | T6 T310 T143 | T311 T312 T302 | T124 T302 T184 | T124 T184 T185 | T313 T124 T176 | T302 T327 T328 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T327 T328 | T302 T327 T328
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T4 T5 T6 | T4 T72 T14 | T5 T6 T29 | T72 T128 T30 | T4 T14 T30 | T5 T6 T29 | T72 T128 T65 | T30 T39 T67 | T14 T30 T61 | T4 T61 T63 | T5 T29 T45 | T6 T310 T143 | T72 T128 T309 | T128 T65 T39 | T30 T39 T67 | T30 T302 T42 | T14 T30 T11 | T61 T59 T60 | T61 T63 T302 | T4 T63 T321 | T45 T84 T186 | T5 T29 T258 | T6 T310 T143 | T302 T327 T328 | T72 T309 T316 | T72 T128 T309 | T128 T65 T66 | T65 T39 T66 | T30 T39 T67 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T11 T124 | T14 T60 T124 | T59 T60 T302 | T61 T302 T62 | T61 T302 T62 | T63 T302 T64 | T63 T302 T64 | T4 T321 T323 | T45 T84 T186 | T309 T317 T318 | T309 T317 T318 | T5 T29 T258 | T6 T310 T143 | T313 T124 T302 | T302 T327 T328 | T302 T319 T320 | T72 T309 T316 | T309 T317 T318 | T72 T128 T309 | T128 T309 T129 | T128 T65 T66 | T65 T66 T309 | T65 T66 T309 | T39 T67 T68 | T309 T317 T318 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T11 T124 T220 | T14 T124 T51 | T60 T302 T135 | T302 T319 T320 | T59 T60 T302 | T302 T319 T320 | T61 T302 T62 | T302 T319 T320 | T61 T302 T62 | T63 T302 T64 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T4 T124 T302 | T321 T323 T232 | T45 T84 T186 | T124 T309 T184 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T5 T29 T136 | T258 T259 T171 | T6 T310 T143 | T311 T312 T302 | T124 T184 T185 | T124 T302 T327 | T302 T319 T320 | T302 T327 T328 | T302 T319 T320 | T72 T309 T315 | T72 T309 T316 | T309 T317 T318 | T309 T317 T318 | T72 T309 T315 | T128 T309 T129 | T128 T309 T129 | T309 T317 T318 | T309 T317 T318 | T65 T66 T309 | T65 T66 T309 | T309 T317 T318 | T309 T317 T318 | T65 T66 T309 | T39 T67 T68 | T39 T67 T68 | T309 T317 T318 | T309 T317 T318 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T30 T302 T42 | T11 T124 T220 | T124 T184 T185 | T124 T184 T185 | T124 T184 T185 | T60 T302 T135 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T61 T302 T62 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T61 T302 T62 | T302 T319 T320 | T302 T319 T320 | T63 T302 T64 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T124 T132 T184 | T124 T184 T185 | T321 T323 T232 | T302 T284 T319 | T124 T184 T185 | T124 T184 T185 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T309 T317 T318 | T5 T29 T322 | T136 T302 T325 | T258 T259 T232 | T124 T184 T185 | T6 T310 T143 | T310 T143 T302 | T302 T319 T320 | T302 T319 T320 | T124 T184 T185 | T124 T184 T185 | T124 T184 T185 | T302 T327 T328 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320 | T302 T319 T320
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T4 T5 T6 | T4 T72 T14 | T5 T6 T44 | T72 T128 T30 | T4 T14 T30 | T5 T6 T44 | T72 T128 T65 | T30 T39 T67 | T14 T30 T61 | T4 T61 T63 | T5 T44 T29 | T6 T310 T143 | T72 T128 T269 | T128 T65 T39 | T30 T39 T67 | T30 T269 T124 | T14 T30 T11 | T61 T59 T60 | T61 T63 T269 | T4 T63 T321 | T44 T45 T84 | T5 T29 T258 | T6 T310 T143 | T269 T124 T309 | T72 T269 T124 | T72 T128 T269 | T128 T65 T66 | T65 T39 T66 | T30 T39 T67 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T11 T269 | T14 T11 T12 | T59 T60 T269 | T61 T269 T124 | T61 T269 T124 | T63 T269 T124 | T63 T269 T124 | T4 T321 T323 | T44 T45 T11 | T269 T124 T309 | T269 T124 T309 | T5 T44 T29 | T6 T310 T143 | T313 T269 T124 | T269 T124 T309 | T269 T124 T309 | T72 T269 T124 | T72 T269 T124 | T72 T128 T269 | T128 T269 T124 | T128 T65 T66 | T65 T66 T269 | T65 T66 T269 | T39 T67 T68 | T39 T67 T68 | T30 T39 T67 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T14 T30 T11 | T14 T11 T12 | T60 T269 T124 | T60 T269 T124 | T59 T60 T269 | T59 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T4 T269 T124 | T321 T323 T232 | T44 T45 T84 | T11 T12 T269 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T5 T29 T136 | T44 T45 T258 | T6 T310 T143 | T6 T310 T143 | T269 T124 T309 | T313 T269 T124 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T72 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T269 T124 | T128 T65 T66 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T65 T66 T269 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T39 T67 T68 | T30 T39 T67 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T30 T269 T124 | T14 T30 T11 | T14 T269 T124 | T14 T11 T12 | T14 T269 T124 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T60 T269 T124 | T59 T60 T269 | T59 T269 T124 | T59 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T61 T269 T124 | T269 T124 T309 | T269 T124 T309 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T63 T269 T124 | T269 T124 T309 | T269 T124 T309 | T4 T269 T124 | T269 T124 T309 | T44 T45 T84 | T44 T45 T84 | T44 T45 T11 | T11 T12 T269 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T5 T29 T279 | T136 T70 T269 | T44 T45 T258 | T171 T269 T124 | T6 T310 T143 | T6 T310 T143 | T6 T310 T143 | T311 T312 T269 | T269 T124 T309 | T269 T124 T309 | T313 T269 T124 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309 | T269 T124 T309
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T4 T5 T6
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T4 T5 T6
101 1/1 assign max_value_o = max_tree[0];
Tests: T4 T5 T6
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);