| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| falling | 7559 | 1 | T462 | 1 | T565 | 2 | T566 | 2 | ||||
| rising | 7602 | 1 | T462 | 1 | T565 | 2 | T566 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 182557 | 1 | T92 | 5 | T93 | 3 | T97 | 46 | ||||
| auto[1] | 14947 | 1 | T462 | 1 | T565 | 2 | T566 | 2 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |