Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.97	95.43	93.69	95.30		94.46	97.35	99.55

Total tests in report: 2925

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.06	40.06	45.08	45.08	46.58	46.58	27.60	27.60			63.09	63.09	57.87	57.87	0.14	0.14	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1781572244
47.55	7.49	49.20	4.13	55.03	8.44	27.86	0.26			69.37	6.28	83.04	25.17	0.80	0.66	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.512150406
52.73	5.18	60.37	11.16	62.39	7.37	30.30	2.45			79.49	10.12	83.04	0.00	0.80	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3887826325
57.03	4.30	69.61	9.24	63.65	1.25	38.08	7.78			79.71	0.22	83.04	0.00	8.08	7.28	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3247871316
60.54	3.52	69.61	0.00	63.65	0.00	38.08	0.00			79.71	0.00	83.04	0.00	29.17	21.09	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2260427374
63.96	3.42	76.22	6.61	67.72	4.07	42.71	4.63			81.92	2.22	86.01	2.97	29.17	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.583267982
66.97	3.01	81.07	4.85	71.42	3.70	46.14	3.43			83.62	1.70	90.38	4.37	29.17	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1283026468
69.55	2.58	81.07	0.00	71.43	0.01	46.14	0.00			83.62	0.00	90.38	0.00	44.66	15.49	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.4112176769
71.99	2.44	82.53	1.46	73.97	2.54	52.11	5.97			85.27	1.66	90.73	0.35	47.34	2.68	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.3687488481
74.30	2.30	82.53	0.00	75.78	1.81	52.11	0.00			85.54	0.27	90.73	0.00	59.09	11.75	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4173762030
76.44	2.15	82.53	0.00	75.78	0.00	64.81	12.70			85.54	0.00	90.91	0.17	59.09	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.164421787
78.08	1.64	82.53	0.00	75.78	0.00	64.81	0.00			85.54	0.00	90.91	0.00	68.90	9.81	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.695053339
79.56	1.48	84.94	2.41	77.91	2.13	66.56	1.76			88.12	2.58	90.91	0.00	68.90	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2200271642
81.02	1.47	84.94	0.00	77.91	0.00	66.56	0.00			88.12	0.00	90.91	0.00	77.70	8.80	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.29869044
82.38	1.36	85.08	0.14	78.00	0.10	74.11	7.54			88.30	0.18	91.08	0.17	77.70	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.691726643
83.49	1.11	86.99	1.91	79.00	1.00	76.43	2.32			89.02	0.72	91.78	0.70	77.70	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.1797383309
84.38	0.89	87.20	0.21	83.47	4.46	76.43	0.00			89.14	0.11	91.78	0.00	78.26	0.56	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2097245910
85.22	0.84	87.93	0.73	83.70	0.23	76.44	0.01			89.36	0.23	95.63	3.85	78.26	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1017472773
86.06	0.84	89.19	1.26	84.48	0.78	78.36	1.92			90.44	1.08	95.63	0.00	78.26	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4226277865
86.90	0.84	89.19	0.00	84.48	0.00	83.39	5.03			90.44	0.00	95.63	0.00	78.26	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1491956849
87.68	0.78	89.19	0.00	84.48	0.00	83.39	0.00			90.44	0.00	95.63	0.00	82.95	4.69	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1748706919
88.38	0.70	89.19	0.00	84.48	0.00	83.39	0.00			90.44	0.00	95.63	0.00	87.13	4.18	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.3781620137
88.93	0.55	90.08	0.89	85.95	1.47	83.84	0.45			90.94	0.49	95.63	0.00	87.13	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1366195712
89.44	0.51	90.93	0.85	86.78	0.84	84.13	0.29			91.86	0.92	95.80	0.17	87.13	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3775146263
89.93	0.49	90.93	0.00	87.00	0.22	84.14	0.01			91.86	0.00	95.80	0.00	89.82	2.69	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2188544417
90.37	0.44	91.04	0.11	87.05	0.05	86.61	2.48			91.89	0.02	95.80	0.00	89.82	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.3810777602
90.71	0.34	91.46	0.42	87.11	0.06	88.13	1.51			91.94	0.05	95.80	0.00	89.82	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.1546053946
91.03	0.32	91.46	0.00	87.11	0.00	88.13	0.00			91.94	0.00	95.80	0.00	91.73	1.90	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.424449473
91.34	0.32	92.08	0.62	87.38	0.27	88.80	0.67			92.09	0.15	95.98	0.17	91.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.920048987
91.64	0.30	92.58	0.50	87.88	0.51	89.10	0.31			92.58	0.49	95.98	0.00	91.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.4209716478
91.94	0.30	92.58	0.00	87.88	0.00	89.10	0.00			92.58	0.00	95.98	0.00	93.50	1.77	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.879232803
92.21	0.27	92.58	0.00	87.88	0.00	90.71	1.61			92.58	0.00	95.98	0.00	93.50	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1956561234
92.47	0.26	92.58	0.00	87.90	0.02	90.72	0.01			92.58	0.00	95.98	0.00	95.04	1.54	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1263850415
92.70	0.23	92.58	0.00	87.90	0.01	90.72	0.00			92.58	0.00	95.98	0.00	96.42	1.37	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.2362526763
92.92	0.23	93.25	0.66	88.18	0.28	90.98	0.26			92.74	0.16	95.98	0.00	96.42	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.497137990
93.10	0.17	93.55	0.31	88.42	0.24	91.20	0.22			93.01	0.28	95.98	0.00	96.42	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2085873565
93.27	0.17	93.55	0.00	89.44	1.02	91.20	0.00			93.01	0.00	95.98	0.00	96.42	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.880467334
93.44	0.17	93.55	0.01	89.44	0.00	92.04	0.84			93.01	0.00	96.15	0.17	96.42	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3931975711
93.57	0.13	93.56	0.01	89.80	0.36	92.07	0.03			93.42	0.41	96.15	0.00	96.42	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.40590997
93.70	0.13	93.65	0.09	90.50	0.70	92.07	0.01			93.42	0.00	96.15	0.00	96.42	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.666332940
93.82	0.12	93.86	0.21	90.82	0.32	92.27	0.20			93.42	0.00	96.15	0.00	96.42	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3951982559
93.94	0.11	93.86	0.00	90.82	0.00	92.27	0.00			93.42	0.00	96.15	0.00	97.10	0.68	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1050503855
94.04	0.10	94.02	0.16	90.93	0.11	92.48	0.21			93.54	0.12	96.15	0.00	97.10	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3850556010
94.13	0.09	94.07	0.06	91.03	0.10	92.65	0.18			93.61	0.06	96.33	0.17	97.10	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1252870796
94.22	0.09	94.08	0.01	91.28	0.25	92.65	0.00			93.88	0.28	96.33	0.00	97.10	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1973258759
94.30	0.08	94.19	0.12	91.33	0.05	92.93	0.28			93.90	0.02	96.33	0.00	97.10	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.2331805300
94.37	0.07	94.19	0.00	91.33	0.00	92.93	0.00			93.90	0.00	96.33	0.00	97.54	0.45	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.128718841
94.44	0.07	94.19	0.00	91.33	0.00	93.35	0.42			93.90	0.00	96.33	0.00	97.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2378996421
94.51	0.07	94.20	0.01	91.36	0.03	93.35	0.00			93.91	0.01	96.33	0.00	97.90	0.35	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3689397848
94.57	0.06	94.20	0.00	91.71	0.35	93.35	0.00			93.91	0.00	96.33	0.00	97.91	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.929698112
94.62	0.05	94.23	0.03	91.74	0.02	93.42	0.07			93.93	0.02	96.50	0.17	97.91	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.622577658
94.67	0.05	94.24	0.01	91.81	0.08	93.55	0.13			94.01	0.08	96.50	0.00	97.91	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1356024981
94.72	0.05	94.25	0.01	91.90	0.08	93.56	0.01			94.02	0.01	96.68	0.17	97.91	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1551862841
94.76	0.04	94.25	0.00	91.90	0.00	93.56	0.00			94.02	0.00	96.68	0.00	98.17	0.26	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1726367602
94.80	0.04	94.26	0.01	91.91	0.01	93.56	0.00			94.04	0.02	96.85	0.17	98.18	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.3553695702
94.84	0.04	94.33	0.07	91.92	0.01	93.71	0.15			94.05	0.01	96.85	0.00	98.18	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2334469498
94.88	0.04	94.33	0.00	91.92	0.00	93.94	0.23			94.05	0.00	96.85	0.00	98.18	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.4093263664
94.91	0.04	94.33	0.01	91.93	0.01	93.95	0.01			94.06	0.01	97.03	0.17	98.19	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4152327838
94.95	0.04	94.34	0.01	91.94	0.01	93.96	0.01			94.07	0.01	97.20	0.17	98.20	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2440816116
94.99	0.04	94.34	0.01	91.95	0.01	93.96	0.00			94.08	0.01	97.38	0.17	98.21	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.437025010
95.02	0.03	94.42	0.08	92.02	0.07	93.98	0.02			94.11	0.03	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.2832388437
95.05	0.03	94.45	0.03	92.05	0.04	94.08	0.09			94.14	0.03	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.3258667480
95.08	0.03	94.45	0.00	92.23	0.18	94.08	0.00			94.14	0.00	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2629828455
95.11	0.03	94.45	0.00	92.23	0.00	94.24	0.17			94.14	0.00	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.4149775989
95.14	0.03	94.45	0.00	92.26	0.03	94.38	0.14			94.14	0.00	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2675738373
95.16	0.03	94.45	0.00	92.42	0.16	94.38	0.00			94.14	0.00	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.3051492675
95.19	0.03	94.53	0.09	92.46	0.03	94.39	0.01			94.17	0.02	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3106691904
95.22	0.03	94.60	0.07	92.48	0.03	94.40	0.01			94.22	0.05	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.1600988141
95.24	0.02	94.67	0.07	92.53	0.05	94.40	0.00			94.25	0.03	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3159432943
95.26	0.02	94.69	0.02	92.62	0.09	94.43	0.04			94.25	0.00	97.38	0.00	98.21	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.3148179812
95.29	0.02	94.69	0.00	92.70	0.07	94.43	0.00			94.26	0.02	97.38	0.00	98.26	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2449390502
95.31	0.02	94.70	0.01	92.73	0.03	94.51	0.08			94.26	0.00	97.38	0.00	98.26	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.3400509104
95.33	0.02	94.70	0.00	92.78	0.06	94.51	0.00			94.30	0.03	97.38	0.00	98.28	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1856563102
95.34	0.02	94.70	0.00	92.86	0.08	94.51	0.00			94.30	0.00	97.38	0.00	98.31	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.955689773
95.36	0.01	94.70	0.00	92.87	0.01	94.51	0.00			94.30	0.00	97.38	0.00	98.39	0.08	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3141507886
95.37	0.01	94.70	0.00	92.87	0.00	94.60	0.08			94.30	0.00	97.38	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.140309784
95.38	0.01	94.70	0.01	92.89	0.02	94.65	0.06			94.30	0.00	97.38	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.2546885324
95.40	0.01	94.70	0.00	92.97	0.08	94.65	0.00			94.30	0.00	97.38	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.1649822716
95.41	0.01	94.70	0.00	92.97	0.00	94.73	0.08			94.30	0.00	97.38	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.2836972864
95.42	0.01	94.70	0.01	92.99	0.02	94.78	0.05			94.30	0.00	97.38	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2068355745
95.43	0.01	94.72	0.02	93.00	0.01	94.82	0.04			94.30	0.00	97.38	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.117737461
95.44	0.01	94.72	0.00	93.00	0.01	94.82	0.00			94.30	0.00	97.38	0.00	98.45	0.06	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.4044148889
95.45	0.01	94.73	0.01	93.04	0.04	94.82	0.00			94.31	0.02	97.38	0.00	98.45	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.639173730
95.46	0.01	94.73	0.00	93.06	0.02	94.82	0.00			94.33	0.02	97.38	0.00	98.47	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2566653238
95.47	0.01	94.73	0.00	93.09	0.03	94.82	0.00			94.36	0.03	97.38	0.00	98.47	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.1831724536
95.48	0.01	94.73	0.00	93.10	0.01	94.86	0.04			94.36	0.00	97.38	0.00	98.48	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.1066043934
95.49	0.01	94.74	0.02	93.10	0.01	94.87	0.02			94.38	0.02	97.38	0.00	98.48	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2372175547
95.50	0.01	94.74	0.00	93.10	0.00	94.93	0.05			94.38	0.00	97.38	0.00	98.48	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.3150557288
95.51	0.01	94.77	0.02	93.11	0.01	94.93	0.01			94.39	0.02	97.38	0.00	98.48	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.2760209069
95.52	0.01	94.79	0.02	93.12	0.01	94.93	0.01			94.41	0.02	97.38	0.00	98.48	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1724398764
95.53	0.01	94.82	0.02	93.12	0.01	94.93	0.01			94.43	0.02	97.38	0.00	98.48	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3861208558
95.54	0.01	94.82	0.00	93.17	0.05	94.93	0.00			94.43	0.00	97.38	0.00	98.48	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1007947801
95.54	0.01	94.82	0.00	93.17	0.00	94.93	0.00			94.43	0.00	97.38	0.00	98.53	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4249544489
95.55	0.01	94.82	0.00	93.17	0.00	94.96	0.02			94.43	0.00	97.38	0.00	98.55	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1686967284
95.56	0.01	94.82	0.00	93.21	0.04	94.96	0.01			94.43	0.00	97.38	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1735785335
95.57	0.01	94.82	0.00	93.25	0.04	94.96	0.00			94.43	0.00	97.38	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.704966496
95.57	0.01	94.82	0.00	93.26	0.01	94.96	0.00			94.43	0.00	97.38	0.00	98.59	0.04	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2445516166
95.58	0.01	94.82	0.01	93.28	0.02	94.98	0.02			94.43	0.00	97.38	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.733909781
95.58	0.01	94.83	0.01	93.30	0.02	94.98	0.01			94.43	0.01	97.38	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.4233323085
95.59	0.01	94.83	0.00	93.30	0.00	94.98	0.00			94.43	0.00	97.38	0.00	98.63	0.04	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3926988701
95.60	0.01	94.83	0.00	93.30	0.00	94.98	0.00			94.43	0.00	97.38	0.00	98.66	0.04	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1723678973
95.60	0.01	94.83	0.00	93.30	0.00	95.02	0.04			94.43	0.00	97.38	0.00	98.66	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1717380180
95.61	0.01	94.83	0.00	93.30	0.01	95.03	0.01			94.44	0.01	97.38	0.00	98.67	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1788662970
95.61	0.01	94.83	0.00	93.32	0.02	95.03	0.00			94.44	0.00	97.38	0.00	98.68	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3654927014
95.62	0.01	94.83	0.00	93.35	0.03	95.03	0.00			94.44	0.00	97.38	0.00	98.68	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4208263606
95.62	0.01	94.83	0.01	93.36	0.01	95.04	0.01			94.44	0.00	97.38	0.00	98.68	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2058325194
95.63	0.01	94.83	0.00	93.36	0.00	95.07	0.03			94.44	0.00	97.38	0.00	98.68	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2660405604
95.63	0.01	94.83	0.00	93.36	0.00	95.10	0.03			94.44	0.00	97.38	0.00	98.68	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.1952745881
95.64	0.01	94.83	0.00	93.36	0.00	95.13	0.03			94.44	0.00	97.38	0.00	98.68	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1280845617
95.64	0.01	94.84	0.01	93.36	0.00	95.14	0.02			94.44	0.00	97.38	0.00	98.68	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3369025492
95.65	0.01	94.84	0.00	93.39	0.02	95.14	0.00			94.44	0.00	97.38	0.00	98.68	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.1149061699
95.65	0.01	94.84	0.00	93.41	0.02	95.14	0.00			94.44	0.00	97.38	0.00	98.68	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.3396415709
95.65	0.01	94.84	0.00	93.41	0.00	95.14	0.00			94.44	0.00	97.38	0.00	98.71	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2561375197
95.66	0.01	94.84	0.00	93.41	0.00	95.14	0.00			94.44	0.00	97.38	0.00	98.73	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2351277407
95.66	0.01	94.84	0.00	93.42	0.01	95.14	0.00			94.44	0.00	97.38	0.00	98.74	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2369673881
95.66	0.01	94.84	0.00	93.44	0.02	95.14	0.00			94.44	0.00	97.38	0.00	98.74	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3747499830
95.67	0.01	94.84	0.00	93.46	0.02	95.14	0.00			94.44	0.00	97.38	0.00	98.74	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1260343403
95.67	0.01	94.84	0.00	93.47	0.01	95.14	0.00			94.44	0.00	97.38	0.00	98.75	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.680139011
95.67	0.01	94.84	0.00	93.49	0.02	95.14	0.00			94.44	0.00	97.38	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1799548606
95.68	0.01	94.84	0.00	93.49	0.00	95.15	0.01			94.44	0.00	97.38	0.00	98.77	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.3753905300
95.68	0.01	94.84	0.00	93.49	0.00	95.17	0.02			94.44	0.00	97.38	0.00	98.77	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3415095298
95.68	0.01	94.84	0.01	93.49	0.01	95.18	0.01			94.44	0.00	97.38	0.00	98.77	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.1339604676
95.69	0.01	94.84	0.00	93.51	0.01	95.18	0.00			94.44	0.00	97.38	0.00	98.77	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.3357088831
95.69	0.01	94.84	0.00	93.52	0.01	95.18	0.00			94.44	0.00	97.38	0.00	98.77	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.741671745
95.69	0.01	94.84	0.00	93.54	0.01	95.18	0.00			94.44	0.00	97.38	0.00	98.77	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1681984924
95.69	0.01	94.84	0.00	93.54	0.00	95.18	0.01			94.44	0.00	97.38	0.00	98.78	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2999316973
95.69	0.01	94.84	0.00	93.54	0.00	95.19	0.01			94.44	0.00	97.38	0.00	98.78	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.3765844284
95.70	0.01	94.84	0.00	93.55	0.01	95.19	0.01			94.44	0.00	97.38	0.00	98.78	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.3604519540
95.70	0.01	94.84	0.00	93.55	0.01	95.20	0.01			94.44	0.00	97.38	0.00	98.78	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.1978118875
95.70	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.79	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2811358523
95.70	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.80	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.167127232
95.70	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.81	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2675723930
95.71	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.83	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.4216625995
95.71	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.84	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.462223641
95.71	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.85	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3327705739
95.71	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.86	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.922593685
95.71	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.87	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2489027387
95.72	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.88	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1728362932
95.72	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.90	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832213610
95.72	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.91	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.520865886
95.72	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.92	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133402158
95.72	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.93	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476482001
95.73	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.94	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.56529458
95.73	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.95	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.1896237557
95.73	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.97	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.2293938442
95.73	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.98	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3513829292
95.73	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	98.99	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3585173679
95.74	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.00	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.4164338258
95.74	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.01	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.1069337514
95.74	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.02	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2724548515
95.74	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.04	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443442800
95.74	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.05	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2463402370
95.75	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.06	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.1320057176
95.75	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.07	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113514899
95.75	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.08	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.3904897670
95.75	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.10	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1845337622
95.75	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.11	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4041041649
95.76	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.12	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.3251925478
95.76	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.13	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441832429
95.76	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.14	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.209345015
95.76	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.15	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2425189958
95.76	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.17	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.2800423324
95.77	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.18	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1397607545
95.77	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.19	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1757210850
95.77	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.20	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497184241
95.77	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.21	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161849105
95.77	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.22	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3896125447
95.78	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.24	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.1544554598
95.78	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.25	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2546134937
95.78	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.26	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.620236670
95.78	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.27	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.324818015
95.78	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.28	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.1429375099
95.79	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.30	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3452509024
95.79	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.31	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1067347306
95.79	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.32	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.3617563057
95.79	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.33	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076164104
95.79	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.34	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2874225320
95.79	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.35	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.549313516
95.80	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.37	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.4137651289
95.80	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.38	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2022085074
95.80	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.39	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.924099141
95.80	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.40	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1807689539
95.80	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.41	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.696970500
95.81	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.42	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.2855525424
95.81	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.44	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1777683648
95.81	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.45	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.2132244047
95.81	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.46	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.499977552
95.81	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.47	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828864339
95.82	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.48	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.4034021463
95.82	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.49	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.1012464093
95.82	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.51	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.551114867
95.82	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.52	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.23676054
95.82	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.53	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.4277443543
95.83	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.54	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.123915410
95.83	0.01	94.84	0.00	93.55	0.00	95.20	0.00			94.44	0.00	97.38	0.00	99.55	0.01	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.655879464
95.83	0.01	94.84	0.00	93.56	0.01	95.20	0.00			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2762156751
95.83	0.01	94.84	0.00	93.57	0.01	95.20	0.00			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.3958940365
95.83	0.01	94.84	0.00	93.58	0.01	95.20	0.00			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2140032579
95.84	0.01	94.84	0.00	93.59	0.01	95.20	0.00			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.34524032
95.84	0.01	94.84	0.00	93.60	0.01	95.20	0.00			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.2507177584
95.84	0.01	94.84	0.00	93.60	0.00	95.21	0.01			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.363986270
95.84	0.01	94.85	0.01	93.60	0.00	95.21	0.00			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.2267766370
95.84	0.01	94.85	0.00	93.60	0.00	95.22	0.01			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.955705497
95.84	0.01	94.85	0.00	93.60	0.00	95.23	0.01			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.4197078143
95.85	0.01	94.85	0.00	93.60	0.00	95.24	0.01			94.44	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2463244782
95.85	0.01	94.85	0.00	93.60	0.00	95.24	0.00			94.45	0.01	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1175197442
95.85	0.01	94.85	0.00	93.60	0.00	95.24	0.00			94.46	0.01	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.1164833815
95.85	0.01	94.85	0.00	93.61	0.01	95.24	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.468336393
95.85	0.01	94.85	0.00	93.62	0.01	95.24	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.203421769
95.85	0.01	94.85	0.00	93.63	0.01	95.24	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.881839661
95.85	0.01	94.85	0.00	93.63	0.01	95.24	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4145003596
95.85	0.01	94.85	0.00	93.64	0.01	95.24	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.1757258686
95.85	0.01	94.85	0.00	93.65	0.01	95.24	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1180510082
95.86	0.01	94.85	0.00	93.65	0.01	95.24	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.1042494664
95.86	0.01	94.85	0.00	93.65	0.00	95.25	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.98435813
95.86	0.01	94.85	0.00	93.65	0.00	95.26	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2738882758
95.86	0.01	94.85	0.01	93.65	0.00	95.26	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.105629256
95.86	0.01	94.85	0.00	93.65	0.00	95.26	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3997115854
95.86	0.01	94.85	0.00	93.65	0.00	95.27	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1903380166
95.86	0.01	94.85	0.00	93.65	0.00	95.27	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1360765799
95.86	0.01	94.85	0.00	93.65	0.00	95.28	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.176115295
95.86	0.01	94.85	0.00	93.66	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1019435153
95.86	0.01	94.85	0.00	93.66	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.396336852
95.86	0.01	94.85	0.00	93.66	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.3707767684
95.86	0.01	94.85	0.00	93.67	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.235913836
95.87	0.01	94.85	0.00	93.67	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2158070961
95.87	0.01	94.85	0.00	93.67	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1795014023
95.87	0.01	94.85	0.00	93.68	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2970744709
95.87	0.01	94.85	0.00	93.68	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1512868846
95.87	0.01	94.85	0.00	93.69	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1478315372
95.87	0.01	94.85	0.00	93.69	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.661083154
95.87	0.01	94.85	0.00	93.69	0.01	95.28	0.00			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.3041929882
95.87	0.01	94.85	0.00	93.69	0.00	95.28	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.3622885831
95.87	0.01	94.85	0.00	93.69	0.00	95.28	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1475939848
95.87	0.01	94.85	0.00	93.69	0.00	95.29	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2323069731
95.87	0.01	94.85	0.00	93.69	0.00	95.29	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2067386146
95.87	0.01	94.85	0.00	93.69	0.00	95.29	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2652306238
95.87	0.01	94.85	0.00	93.69	0.00	95.29	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.659449291
95.87	0.01	94.85	0.00	93.69	0.00	95.30	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2057867018
95.87	0.01	94.85	0.00	93.69	0.00	95.30	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4246452276
95.87	0.01	94.85	0.00	93.69	0.00	95.30	0.01			94.46	0.00	97.38	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2572217527

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1689368035
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.3120621479
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3874627985
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.3204405540
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.92868450
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.84376732
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2420399445
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3248200472
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.215486393
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3725597504
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2930070906
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1530334569
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1989833712
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4218343831
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2062610681
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2877156621
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3277233634
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.1221066444
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2584609761
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1632727928
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.302508255
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1455526238
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.2667672222
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.484454880
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3323904717
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.86312635
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2884597962
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.3676249871
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.1478793014
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3477633976
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3756185822
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1278738303
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.801944869
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.899700811
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.496342011
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.2339072587
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3157739261
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2425942695
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1157407946
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.301718475
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3104250841
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.643444813
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2685778436
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.3439009430
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.4271277644
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3724813326
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.2607680191
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2583176847
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2851436033
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.224449765
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/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1878718164

Total test records in report: 2925

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2227862543	Sep 11 09:28:28 PM UTC 24	Sep 11 09:30:09 PM UTC 24	2332560550 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.1635786819	Sep 11 09:30:13 PM UTC 24	Sep 11 09:32:58 PM UTC 24	2525866184 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.3490549301	Sep 11 09:30:05 PM UTC 24	Sep 11 09:33:09 PM UTC 24	3054394762 ps
T4	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.583267982	Sep 11 09:30:04 PM UTC 24	Sep 11 09:33:26 PM UTC 24	3390323544 ps
T104	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.12963375	Sep 11 09:30:09 PM UTC 24	Sep 11 09:33:33 PM UTC 24	2688270772 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1781572244	Sep 11 09:30:06 PM UTC 24	Sep 11 09:34:51 PM UTC 24	2652782683 ps
T105	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.1593400015	Sep 11 09:31:32 PM UTC 24	Sep 11 09:35:05 PM UTC 24	2420617570 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.1876998369	Sep 11 09:32:17 PM UTC 24	Sep 11 09:35:49 PM UTC 24	2688958892 ps
T33	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.115977236	Sep 11 09:31:48 PM UTC 24	Sep 11 09:36:03 PM UTC 24	3073696618 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.140309784	Sep 11 09:31:10 PM UTC 24	Sep 11 09:36:14 PM UTC 24	3534996497 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2463244782	Sep 11 09:34:35 PM UTC 24	Sep 11 09:36:22 PM UTC 24	2905981357 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.2832388437	Sep 11 09:31:15 PM UTC 24	Sep 11 09:36:30 PM UTC 24	3152673496 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.2331805300	Sep 11 09:32:23 PM UTC 24	Sep 11 09:36:34 PM UTC 24	2509775060 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1356024981	Sep 11 09:32:24 PM UTC 24	Sep 11 09:36:45 PM UTC 24	3188862329 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.1228623099	Sep 11 09:32:40 PM UTC 24	Sep 11 09:37:05 PM UTC 24	2315534638 ps
T441	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.2968080354	Sep 11 09:32:20 PM UTC 24	Sep 11 09:37:07 PM UTC 24	3364888754 ps
T235	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2072915528	Sep 11 09:31:37 PM UTC 24	Sep 11 09:38:16 PM UTC 24	3834111114 ps
T180	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2230116578	Sep 11 09:32:43 PM UTC 24	Sep 11 09:38:24 PM UTC 24	3339903902 ps
T37	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.164421787	Sep 11 09:32:16 PM UTC 24	Sep 11 09:38:37 PM UTC 24	4073050748 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2058325194	Sep 11 09:29:41 PM UTC 24	Sep 11 09:38:43 PM UTC 24	4926981998 ps
T31	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.900151163	Sep 11 09:36:21 PM UTC 24	Sep 11 09:38:44 PM UTC 24	3478169088 ps
T130	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3747499830	Sep 11 09:30:13 PM UTC 24	Sep 11 09:39:36 PM UTC 24	4330072864 ps
T32	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3931975711	Sep 11 09:35:51 PM UTC 24	Sep 11 09:39:42 PM UTC 24	3367620270 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.4233323085	Sep 11 09:31:47 PM UTC 24	Sep 11 09:39:42 PM UTC 24	3512607976 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.117968398	Sep 11 09:37:27 PM UTC 24	Sep 11 09:40:28 PM UTC 24	3336240750 ps
T181	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2179033171	Sep 11 09:35:50 PM UTC 24	Sep 11 09:40:40 PM UTC 24	3170775334 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.1757258686	Sep 11 09:31:39 PM UTC 24	Sep 11 09:40:48 PM UTC 24	4236252402 ps
T131	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.3400509104	Sep 11 09:31:40 PM UTC 24	Sep 11 09:40:53 PM UTC 24	3904215232 ps
T189	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3897266313	Sep 11 09:38:32 PM UTC 24	Sep 11 09:40:54 PM UTC 24	2331664156 ps
T45	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.3753905300	Sep 11 09:31:34 PM UTC 24	Sep 11 09:41:10 PM UTC 24	5289414050 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.3258667480	Sep 11 09:32:21 PM UTC 24	Sep 11 09:41:23 PM UTC 24	3761094736 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.3346106088	Sep 11 09:32:40 PM UTC 24	Sep 11 09:41:25 PM UTC 24	4681108573 ps
T321	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2759729272	Sep 11 09:31:13 PM UTC 24	Sep 11 09:41:31 PM UTC 24	4478734600 ps
T190	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.787395302	Sep 11 09:39:19 PM UTC 24	Sep 11 09:41:34 PM UTC 24	2441607575 ps
T201	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2541709963	Sep 11 09:36:58 PM UTC 24	Sep 11 09:41:35 PM UTC 24	2848709181 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.497137990	Sep 11 09:32:37 PM UTC 24	Sep 11 09:41:38 PM UTC 24	4165690796 ps
T39	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3982670363	Sep 11 09:32:17 PM UTC 24	Sep 11 09:41:57 PM UTC 24	4071592862 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.75284153	Sep 11 09:32:37 PM UTC 24	Sep 11 09:42:02 PM UTC 24	6150887848 ps
T78	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1252870796	Sep 11 09:32:11 PM UTC 24	Sep 11 09:42:27 PM UTC 24	6330063830 ps
T145	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2386360312	Sep 11 09:31:50 PM UTC 24	Sep 11 09:42:41 PM UTC 24	4714138428 ps
T268	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.1150811196	Sep 11 09:39:10 PM UTC 24	Sep 11 09:42:59 PM UTC 24	2904865400 ps
T79	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4113914447	Sep 11 09:31:00 PM UTC 24	Sep 11 09:43:12 PM UTC 24	5835929336 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.1458923589	Sep 11 09:32:24 PM UTC 24	Sep 11 09:43:24 PM UTC 24	4808236354 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2970744709	Sep 11 09:32:39 PM UTC 24	Sep 11 09:43:35 PM UTC 24	5013391026 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1180510082	Sep 11 09:30:49 PM UTC 24	Sep 11 09:43:41 PM UTC 24	5052185592 ps
T195	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.4197078143	Sep 11 09:35:51 PM UTC 24	Sep 11 09:44:18 PM UTC 24	7939431826 ps
T157	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2876403169	Sep 11 09:39:46 PM UTC 24	Sep 11 09:44:39 PM UTC 24	6505928390 ps
T269	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.1269741253	Sep 11 09:38:45 PM UTC 24	Sep 11 09:45:12 PM UTC 24	4355296360 ps
T333	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1058759190	Sep 11 09:42:22 PM UTC 24	Sep 11 09:45:19 PM UTC 24	2418176178 ps
T184	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4226277865	Sep 11 09:34:34 PM UTC 24	Sep 11 09:45:30 PM UTC 24	5485624528 ps
T294	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2120899591	Sep 11 09:34:13 PM UTC 24	Sep 11 09:45:54 PM UTC 24	4519210726 ps
T124	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.2485652586	Sep 11 09:43:20 PM UTC 24	Sep 11 09:46:38 PM UTC 24	2601502306 ps
T146	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2045491695	Sep 11 09:32:23 PM UTC 24	Sep 11 09:46:54 PM UTC 24	6122529518 ps
T202	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2738882758	Sep 11 09:39:44 PM UTC 24	Sep 11 09:47:02 PM UTC 24	4397551750 ps
T147	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3775173428	Sep 11 09:32:11 PM UTC 24	Sep 11 09:47:40 PM UTC 24	4952156384 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2068355745	Sep 11 09:31:38 PM UTC 24	Sep 11 09:47:59 PM UTC 24	8489702027 ps
T413	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.1578889577	Sep 11 09:32:08 PM UTC 24	Sep 11 09:48:55 PM UTC 24	5908152120 ps
T30	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.209868842	Sep 11 09:43:31 PM UTC 24	Sep 11 09:49:00 PM UTC 24	2890821278 ps
T246	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2419911445	Sep 11 09:43:46 PM UTC 24	Sep 11 09:49:35 PM UTC 24	3795310566 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4280221088	Sep 11 09:44:55 PM UTC 24	Sep 11 09:50:03 PM UTC 24	2993149860 ps
T34	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.1548353930	Sep 11 09:28:51 PM UTC 24	Sep 11 09:50:12 PM UTC 24	8886680696 ps
T200	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3915980857	Sep 11 09:34:35 PM UTC 24	Sep 11 09:50:29 PM UTC 24	8134894718 ps
T414	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.4183039003	Sep 11 09:46:31 PM UTC 24	Sep 11 09:50:30 PM UTC 24	3040141600 ps
T415	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3066096655	Sep 11 09:46:10 PM UTC 24	Sep 11 09:50:53 PM UTC 24	2727349456 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.117737461	Sep 11 09:43:20 PM UTC 24	Sep 11 09:51:13 PM UTC 24	5950193050 ps
T233	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.622577658	Sep 11 09:38:59 PM UTC 24	Sep 11 09:51:18 PM UTC 24	5023831076 ps
T236	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.1403062711	Sep 11 09:44:43 PM UTC 24	Sep 11 09:51:18 PM UTC 24	3539795248 ps
T258	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.1223273745	Sep 11 09:46:16 PM UTC 24	Sep 11 09:51:27 PM UTC 24	2901301558 ps
T67	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1593555869	Sep 11 09:40:36 PM UTC 24	Sep 11 09:51:28 PM UTC 24	8031964776 ps
T259	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.2767259329	Sep 11 09:46:53 PM UTC 24	Sep 11 09:51:36 PM UTC 24	3448069080 ps
T260	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.295208390	Sep 11 09:45:21 PM UTC 24	Sep 11 09:52:35 PM UTC 24	7753841946 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.3687488481	Sep 11 09:47:17 PM UTC 24	Sep 11 09:52:38 PM UTC 24	3193557294 ps
T192	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.691726643	Sep 11 09:38:46 PM UTC 24	Sep 11 09:52:42 PM UTC 24	7892454532 ps
T210	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.763168718	Sep 11 09:45:23 PM UTC 24	Sep 11 09:53:23 PM UTC 24	3534758304 ps
T139	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1717380180	Sep 11 09:45:27 PM UTC 24	Sep 11 09:53:35 PM UTC 24	19255068168 ps
T194	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1052876661	Sep 11 09:34:26 PM UTC 24	Sep 11 09:53:42 PM UTC 24	9043111534 ps
T237	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2891653696	Sep 11 09:45:30 PM UTC 24	Sep 11 09:54:02 PM UTC 24	3818349832 ps
T136	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2730463811	Sep 11 09:43:54 PM UTC 24	Sep 11 09:54:26 PM UTC 24	7153992524 ps
T295	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1231917382	Sep 11 09:34:30 PM UTC 24	Sep 11 09:54:37 PM UTC 24	9593478264 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3976031324	Sep 11 09:31:14 PM UTC 24	Sep 11 09:54:37 PM UTC 24	7558287812 ps
T383	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.645213761	Sep 11 09:50:50 PM UTC 24	Sep 11 09:54:49 PM UTC 24	2965614200 ps
T234	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1658561161	Sep 11 09:45:53 PM UTC 24	Sep 11 09:55:09 PM UTC 24	5707294920 ps
T897	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1982535835	Sep 11 09:45:26 PM UTC 24	Sep 11 09:55:16 PM UTC 24	7077163368 ps
T676	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.582686723	Sep 11 09:39:46 PM UTC 24	Sep 11 09:55:41 PM UTC 24	7998813273 ps
T156	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.1493586549	Sep 11 09:51:17 PM UTC 24	Sep 11 09:55:57 PM UTC 24	3066159600 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3850556010	Sep 11 09:45:58 PM UTC 24	Sep 11 09:56:11 PM UTC 24	4220185546 ps
T100	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4152327838	Sep 11 09:49:48 PM UTC 24	Sep 11 09:56:15 PM UTC 24	4316535964 ps
T111	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.2719532536	Sep 11 09:47:43 PM UTC 24	Sep 11 09:56:26 PM UTC 24	4961516400 ps
T101	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.4282458726	Sep 11 09:50:47 PM UTC 24	Sep 11 09:56:37 PM UTC 24	2825493984 ps
T19	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.3785882176	Sep 11 09:31:22 PM UTC 24	Sep 11 09:56:46 PM UTC 24	7864935800 ps
T112	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.3830606751	Sep 11 09:47:43 PM UTC 24	Sep 11 09:56:50 PM UTC 24	5522790616 ps
T113	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3184492796	Sep 11 09:45:27 PM UTC 24	Sep 11 09:57:31 PM UTC 24	6783208250 ps
T114	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.4201865981	Sep 11 09:53:36 PM UTC 24	Sep 11 09:57:33 PM UTC 24	2576324056 ps
T115	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.2703488514	Sep 11 09:31:25 PM UTC 24	Sep 11 09:58:06 PM UTC 24	21855015048 ps
T116	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1478315372	Sep 11 09:46:11 PM UTC 24	Sep 11 09:58:46 PM UTC 24	4948522416 ps
T117	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.3717385372	Sep 11 09:52:44 PM UTC 24	Sep 11 09:59:00 PM UTC 24	3195140944 ps
T322	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.769952520	Sep 11 09:54:27 PM UTC 24	Sep 11 09:59:19 PM UTC 24	2836167760 ps
T323	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.1273018372	Sep 11 09:54:37 PM UTC 24	Sep 11 09:59:20 PM UTC 24	2633094607 ps
T677	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.1263951643	Sep 11 09:54:53 PM UTC 24	Sep 11 09:59:29 PM UTC 24	2754252592 ps
T898	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.4222135033	Sep 11 09:55:12 PM UTC 24	Sep 11 09:59:29 PM UTC 24	3172808400 ps
T153	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2652306238	Sep 11 09:51:31 PM UTC 24	Sep 11 10:00:03 PM UTC 24	2853597880 ps
T324	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.326831725	Sep 11 09:45:34 PM UTC 24	Sep 11 10:00:23 PM UTC 24	5422098694 ps
T456	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.4253884747	Sep 11 09:57:41 PM UTC 24	Sep 11 10:00:30 PM UTC 24	2465617852 ps
T232	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3039326133	Sep 11 09:40:35 PM UTC 24	Sep 11 10:00:42 PM UTC 24	11704430723 ps
T457	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.1844502595	Sep 11 09:56:32 PM UTC 24	Sep 11 10:00:55 PM UTC 24	3242213616 ps
T211	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3688946541	Sep 11 09:52:47 PM UTC 24	Sep 11 10:01:34 PM UTC 24	4945232160 ps
T244	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.199859888	Sep 11 09:46:12 PM UTC 24	Sep 11 10:02:03 PM UTC 24	5350099856 ps
T349	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.659449291	Sep 11 09:39:49 PM UTC 24	Sep 11 10:02:19 PM UTC 24	10012157358 ps
T899	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.3996330642	Sep 11 09:57:24 PM UTC 24	Sep 11 10:02:54 PM UTC 24	3261647896 ps
T418	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.324372462	Sep 11 09:57:34 PM UTC 24	Sep 11 10:02:57 PM UTC 24	2736207176 ps
T154	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1487573471	Sep 11 09:52:46 PM UTC 24	Sep 11 10:03:04 PM UTC 24	3190647012 ps
T900	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2750695874	Sep 11 09:57:35 PM UTC 24	Sep 11 10:03:29 PM UTC 24	2528075346 ps
T155	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2378996421	Sep 11 09:52:50 PM UTC 24	Sep 11 10:04:44 PM UTC 24	5658077896 ps
T172	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.1978118875	Sep 11 10:00:27 PM UTC 24	Sep 11 10:04:57 PM UTC 24	3317682414 ps
T250	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.2267766370	Sep 11 10:01:35 PM UTC 24	Sep 11 10:05:44 PM UTC 24	2773327768 ps
T186	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3106691904	Sep 11 09:39:27 PM UTC 24	Sep 11 10:06:13 PM UTC 24	11968744280 ps
T262	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3048809716	Sep 11 09:57:42 PM UTC 24	Sep 11 10:06:15 PM UTC 24	9534407089 ps
T901	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.403701411	Sep 11 09:40:35 PM UTC 24	Sep 11 10:06:19 PM UTC 24	15479547431 ps
T148	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2675738373	Sep 11 09:58:19 PM UTC 24	Sep 11 10:07:05 PM UTC 24	5214367617 ps
T902	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1933619242	Sep 11 10:02:11 PM UTC 24	Sep 11 10:07:09 PM UTC 24	3480191336 ps
T205	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1436340141	Sep 11 09:59:35 PM UTC 24	Sep 11 10:07:27 PM UTC 24	6637200992 ps
T102	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.920048987	Sep 11 09:49:49 PM UTC 24	Sep 11 10:08:25 PM UTC 24	10267843560 ps
T158	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3951982559	Sep 11 10:00:26 PM UTC 24	Sep 11 10:08:41 PM UTC 24	5373198360 ps
T206	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.3765844284	Sep 11 09:58:19 PM UTC 24	Sep 11 10:09:20 PM UTC 24	6965862643 ps
T203	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1108180983	Sep 11 09:57:42 PM UTC 24	Sep 11 10:09:24 PM UTC 24	5283921456 ps
T289	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.98435813	Sep 11 10:02:43 PM UTC 24	Sep 11 10:09:36 PM UTC 24	4692921888 ps
T290	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.589153807	Sep 11 09:48:18 PM UTC 24	Sep 11 10:10:13 PM UTC 24	8098084186 ps
T245	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.3810777602	Sep 11 09:53:37 PM UTC 24	Sep 11 10:10:15 PM UTC 24	6097916820 ps
T291	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.867490472	Sep 11 10:02:58 PM UTC 24	Sep 11 10:10:20 PM UTC 24	4491931432 ps
T125	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.4209716478	Sep 11 10:01:33 PM UTC 24	Sep 11 10:10:43 PM UTC 24	4188817762 ps
T292	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.2964766766	Sep 11 10:07:55 PM UTC 24	Sep 11 10:10:44 PM UTC 24	2464365094 ps
T193	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2983939706	Sep 11 09:38:55 PM UTC 24	Sep 11 10:10:46 PM UTC 24	24429140290 ps
T293	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.58163634	Sep 11 09:58:42 PM UTC 24	Sep 11 10:11:10 PM UTC 24	7054720472 ps
T317	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1903380166	Sep 11 09:50:13 PM UTC 24	Sep 11 10:11:43 PM UTC 24	6501942504 ps
T36	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.3622885831	Sep 11 10:07:49 PM UTC 24	Sep 11 10:12:30 PM UTC 24	4115321080 ps
T903	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1266395921	Sep 11 10:03:54 PM UTC 24	Sep 11 10:12:44 PM UTC 24	4478124026 ps
T694	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.3938168957	Sep 11 10:07:11 PM UTC 24	Sep 11 10:12:56 PM UTC 24	3477698600 ps
T143	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.444095741	Sep 11 09:56:05 PM UTC 24	Sep 11 10:12:59 PM UTC 24	6823378619 ps
T132	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.2153832450	Sep 11 09:32:23 PM UTC 24	Sep 11 10:13:28 PM UTC 24	13721940000 ps
T149	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.4137014811	Sep 11 09:54:26 PM UTC 24	Sep 11 10:13:40 PM UTC 24	6356953873 ps
T904	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4011853960	Sep 11 10:07:12 PM UTC 24	Sep 11 10:14:06 PM UTC 24	3285947114 ps
T160	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.2760209069	Sep 11 09:59:39 PM UTC 24	Sep 11 10:14:21 PM UTC 24	5177243096 ps
T150	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2660405604	Sep 11 10:05:33 PM UTC 24	Sep 11 10:14:42 PM UTC 24	4151649704 ps
T151	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2187187595	Sep 11 10:04:04 PM UTC 24	Sep 11 10:14:43 PM UTC 24	4856297728 ps
T320	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3887826325	Sep 11 10:01:34 PM UTC 24	Sep 11 10:14:53 PM UTC 24	5132713280 ps
T152	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4131811050	Sep 11 10:05:36 PM UTC 24	Sep 11 10:15:17 PM UTC 24	4836362408 ps
T335	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.3604519540	Sep 11 09:53:38 PM UTC 24	Sep 11 10:15:17 PM UTC 24	6481665392 ps
T196	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1360765799	Sep 11 10:10:22 PM UTC 24	Sep 11 10:15:48 PM UTC 24	4778481520 ps
T905	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3635456901	Sep 11 10:04:08 PM UTC 24	Sep 11 10:15:59 PM UTC 24	5569851148 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3775146263	Sep 11 10:10:23 PM UTC 24	Sep 11 10:16:12 PM UTC 24	7652745364 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.1792514389	Sep 11 09:43:45 PM UTC 24	Sep 11 10:16:41 PM UTC 24	24247119132 ps
T403	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2057867018	Sep 11 10:14:19 PM UTC 24	Sep 11 10:16:55 PM UTC 24	2231067846 ps
T438	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3836794986	Sep 11 10:07:55 PM UTC 24	Sep 11 10:17:18 PM UTC 24	4606735120 ps
T439	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2524336730	Sep 11 10:06:22 PM UTC 24	Sep 11 10:17:53 PM UTC 24	4776904138 ps
T440	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3974409439	Sep 11 10:07:11 PM UTC 24	Sep 11 10:17:57 PM UTC 24	5628192968 ps
T159	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1374332729	Sep 11 10:11:31 PM UTC 24	Sep 11 10:18:12 PM UTC 24	5111232904 ps
T212	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3321097750	Sep 11 10:03:54 PM UTC 24	Sep 11 10:18:16 PM UTC 24	11827585268 ps
T230	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1370501608	Sep 11 09:50:16 PM UTC 24	Sep 11 10:18:24 PM UTC 24	7200302132 ps
T329	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2200271642	Sep 11 10:00:45 PM UTC 24	Sep 11 10:18:25 PM UTC 24	6136086568 ps
T83	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2334469498	Sep 11 10:13:15 PM UTC 24	Sep 11 10:18:28 PM UTC 24	3862035436 ps
T357	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1512868846	Sep 11 10:10:24 PM UTC 24	Sep 11 10:18:34 PM UTC 24	4521612440 ps
T84	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2468877127	Sep 11 10:12:01 PM UTC 24	Sep 11 10:18:35 PM UTC 24	3886387922 ps
T253	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.4093263664	Sep 11 09:51:16 PM UTC 24	Sep 11 10:18:51 PM UTC 24	6358124110 ps
T207	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3847105099	Sep 11 10:14:44 PM UTC 24	Sep 11 10:18:59 PM UTC 24	2988650647 ps
T119	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2372175547	Sep 11 10:12:01 PM UTC 24	Sep 11 10:19:22 PM UTC 24	4878384048 ps
T281	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.963025943	Sep 11 10:12:59 PM UTC 24	Sep 11 10:19:29 PM UTC 24	4180585461 ps
T282	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2140032579	Sep 11 10:12:00 PM UTC 24	Sep 11 10:20:08 PM UTC 24	5439924312 ps
T208	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1017472773	Sep 11 10:14:16 PM UTC 24	Sep 11 10:20:10 PM UTC 24	3614618380 ps
T283	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.2748171879	Sep 11 09:52:49 PM UTC 24	Sep 11 10:20:20 PM UTC 24	8557231984 ps
T85	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1788662970	Sep 11 10:12:21 PM UTC 24	Sep 11 10:20:21 PM UTC 24	4692044821 ps
T284	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.803970425	Sep 11 10:16:01 PM UTC 24	Sep 11 10:20:27 PM UTC 24	3314042482 ps
T285	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.742978706	Sep 11 10:15:52 PM UTC 24	Sep 11 10:20:28 PM UTC 24	3469184274 ps
T286	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.618641868	Sep 11 10:14:59 PM UTC 24	Sep 11 10:20:41 PM UTC 24	3340443085 ps
T366	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3392163527	Sep 11 10:16:48 PM UTC 24	Sep 11 10:20:55 PM UTC 24	3138446736 ps
T297	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.1766575435	Sep 11 09:55:59 PM UTC 24	Sep 11 10:21:04 PM UTC 24	8141957704 ps
T88	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3619865428	Sep 11 10:13:32 PM UTC 24	Sep 11 10:21:13 PM UTC 24	5285839509 ps
T406	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.896065383	Sep 11 10:16:45 PM UTC 24	Sep 11 10:21:19 PM UTC 24	3474273187 ps
T906	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.1121793507	Sep 11 09:55:35 PM UTC 24	Sep 11 10:21:23 PM UTC 24	7161000368 ps
T678	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1563464137	Sep 11 10:12:00 PM UTC 24	Sep 11 10:21:26 PM UTC 24	6438720198 ps
T20	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.971862307	Sep 11 09:32:01 PM UTC 24	Sep 11 10:21:35 PM UTC 24	11598731990 ps
T907	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2778119197	Sep 11 10:17:35 PM UTC 24	Sep 11 10:22:08 PM UTC 24	3642216906 ps
T423	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.1965254995	Sep 11 10:01:37 PM UTC 24	Sep 11 10:23:24 PM UTC 24	9210262340 ps
T908	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.3845411482	Sep 11 10:16:06 PM UTC 24	Sep 11 10:24:19 PM UTC 24	4769701148 ps
T375	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.427606226	Sep 11 09:39:46 PM UTC 24	Sep 11 10:24:27 PM UTC 24	23594388996 ps
T204	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.648277959	Sep 11 10:17:55 PM UTC 24	Sep 11 10:24:48 PM UTC 24	4036029725 ps
T361	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4145003596	Sep 11 10:16:07 PM UTC 24	Sep 11 10:25:45 PM UTC 24	5334950780 ps
T695	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.323398353	Sep 11 10:09:18 PM UTC 24	Sep 11 10:25:59 PM UTC 24	8320510532 ps
T417	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.3598701466	Sep 11 10:25:13 PM UTC 24	Sep 11 10:28:14 PM UTC 24	2314005380 ps
T127	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.1112719155	Sep 11 10:20:33 PM UTC 24	Sep 11 10:28:39 PM UTC 24	11158663216 ps
T679	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.226996239	Sep 11 10:00:24 PM UTC 24	Sep 11 10:30:03 PM UTC 24	25927309294 ps
T95	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.854832188	Sep 11 10:08:49 PM UTC 24	Sep 11 10:30:57 PM UTC 24	13866782190 ps
T298	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4103050674	Sep 11 10:17:16 PM UTC 24	Sep 11 10:31:00 PM UTC 24	7682223852 ps
T909	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.226723492	Sep 11 10:16:05 PM UTC 24	Sep 11 10:31:40 PM UTC 24	7358949025 ps
T135	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.1670814550	Sep 11 10:22:52 PM UTC 24	Sep 11 10:32:03 PM UTC 24	4693885470 ps
T296	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1491956849	Sep 11 09:56:06 PM UTC 24	Sep 11 10:35:51 PM UTC 24	10818663688 ps
T299	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.306213571	Sep 11 09:56:06 PM UTC 24	Sep 11 10:38:48 PM UTC 24	13260513560 ps
T910	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1312613790	Sep 11 10:22:54 PM UTC 24	Sep 11 10:40:22 PM UTC 24	5918354096 ps
T40	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3369025492	Sep 11 09:44:43 PM UTC 24	Sep 11 10:41:13 PM UTC 24	20177443619 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1175197442	Sep 11 10:11:11 PM UTC 24	Sep 11 10:41:13 PM UTC 24	26534281700 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3336968772	Sep 11 10:11:50 PM UTC 24	Sep 11 10:42:13 PM UTC 24	22969329928 ps
T89	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.1053431474	Sep 11 10:13:32 PM UTC 24	Sep 11 10:43:49 PM UTC 24	18919660831 ps
T911	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1650221692	Sep 11 09:56:01 PM UTC 24	Sep 11 10:44:22 PM UTC 24	13469351540 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.1797383309	Sep 11 10:23:03 PM UTC 24	Sep 11 10:46:11 PM UTC 24	5599802498 ps
T175	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.559291905	Sep 11 09:45:07 PM UTC 24	Sep 11 10:50:04 PM UTC 24	16213940684 ps
T912	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2071666930	Sep 11 09:32:38 PM UTC 24	Sep 11 10:50:45 PM UTC 24	19184420144 ps
T199	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.2836972864	Sep 11 10:18:35 PM UTC 24	Sep 11 10:56:25 PM UTC 24	22067534720 ps
T302	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.955705497	Sep 11 09:56:29 PM UTC 24	Sep 11 11:08:41 PM UTC 24	17329091740 ps
T144	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3415095298	Sep 11 09:45:54 PM UTC 24	Sep 11 10:59:50 PM UTC 24	19876454271 ps
T318	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1956561234	Sep 11 09:31:23 PM UTC 24	Sep 11 11:09:09 PM UTC 24	44099056126 ps
T140	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.363986270	Sep 11 10:21:25 PM UTC 24	Sep 11 11:09:14 PM UTC 24	19174692184 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.1546053946	Sep 11 10:41:53 PM UTC 24	Sep 11 11:09:28 PM UTC 24	11539802186 ps
T261	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.692179747	Sep 11 11:09:20 PM UTC 24	Sep 11 11:11:34 PM UTC 24	2769263241 ps
T913	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.492033755	Sep 11 09:35:49 PM UTC 24	Sep 11 11:15:37 PM UTC 24	26060978490 ps
T177	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.2499992891	Sep 11 11:10:15 PM UTC 24	Sep 11 11:16:08 PM UTC 24	4876783382 ps
T914	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.1933677778	Sep 11 11:12:14 PM UTC 24	Sep 11 11:18:00 PM UTC 24	3289089014 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3827128655	Sep 11 10:41:53 PM UTC 24	Sep 11 11:18:07 PM UTC 24	12334391333 ps
T305	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.4149775989	Sep 11 09:38:42 PM UTC 24	Sep 11 11:18:22 PM UTC 24	49861923456 ps
T308	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2813045534	Sep 11 09:38:12 PM UTC 24	Sep 11 11:18:42 PM UTC 24	46658460863 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.412386110	Sep 11 10:29:43 PM UTC 24	Sep 11 11:19:30 PM UTC 24	10917725185 ps
T412	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.248453074	Sep 11 10:25:13 PM UTC 24	Sep 11 11:19:36 PM UTC 24	10979058138 ps
T915	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.281650451	Sep 11 11:16:17 PM UTC 24	Sep 11 11:19:53 PM UTC 24	2936878424 ps
T306	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.176115295	Sep 11 09:39:10 PM UTC 24	Sep 11 11:20:24 PM UTC 24	49483663586 ps
T916	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.3820879991	Sep 11 11:10:20 PM UTC 24	Sep 11 11:20:25 PM UTC 24	5085102700 ps
T53	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3441369894	Sep 11 10:27:40 PM UTC 24	Sep 11 11:21:20 PM UTC 24	11896178841 ps
T448	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.316848663	Sep 11 10:42:49 PM UTC 24	Sep 11 11:22:11 PM UTC 24	11333787886 ps
T917	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.3253366886	Sep 11 11:16:45 PM UTC 24	Sep 11 11:22:18 PM UTC 24	2419024234 ps
T918	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.2727600437	Sep 11 11:19:00 PM UTC 24	Sep 11 11:23:09 PM UTC 24	2872287748 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.815132847	Sep 11 11:19:03 PM UTC 24	Sep 11 11:24:35 PM UTC 24	3321658875 ps
T919	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.1100209516	Sep 11 11:19:20 PM UTC 24	Sep 11 11:24:57 PM UTC 24	3745241598 ps
T920	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.387803104	Sep 11 11:20:29 PM UTC 24	Sep 11 11:25:04 PM UTC 24	2605871180 ps
T921	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.3434423146	Sep 11 11:20:34 PM UTC 24	Sep 11 11:25:07 PM UTC 24	2699931180 ps
T922	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.3325971630	Sep 11 11:19:00 PM UTC 24	Sep 11 11:26:37 PM UTC 24	3703500832 ps
T326	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.2802201401	Sep 11 11:22:00 PM UTC 24	Sep 11 11:26:38 PM UTC 24	3153001110 ps
T465	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.731813122	Sep 11 10:32:49 PM UTC 24	Sep 11 11:27:25 PM UTC 24	11445090632 ps
T923	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.4176577519	Sep 11 11:23:01 PM UTC 24	Sep 11 11:27:31 PM UTC 24	3428743772 ps
T126	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.4293986238	Sep 11 11:23:00 PM UTC 24	Sep 11 11:27:36 PM UTC 24	3460817206 ps
T924	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2111536114	Sep 11 10:29:16 PM UTC 24	Sep 11 11:28:20 PM UTC 24	11545567000 ps
T925	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.3688369306	Sep 11 11:21:14 PM UTC 24	Sep 11 11:28:28 PM UTC 24	6187907000 ps
T926	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.310049937	Sep 11 11:25:38 PM UTC 24	Sep 11 11:28:31 PM UTC 24	2049808000 ps
T927	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.3926786448	Sep 11 11:23:49 PM UTC 24	Sep 11 11:29:10 PM UTC 24	2402431858 ps
T416	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3780258723	Sep 11 11:21:14 PM UTC 24	Sep 11 11:29:13 PM UTC 24	5827000932 ps
T928	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.4009028309	Sep 11 10:22:29 PM UTC 24	Sep 11 11:29:42 PM UTC 24	14816140300 ps
T929	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.415458603	Sep 11 11:25:50 PM UTC 24	Sep 11 11:29:46 PM UTC 24	3250285576 ps
T930	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.3006579782	Sep 11 11:25:53 PM UTC 24	Sep 11 11:30:08 PM UTC 24	2407418346 ps
T931	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.3614190500	Sep 11 11:25:13 PM UTC 24	Sep 11 11:30:24 PM UTC 24	3306338920 ps
T932	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.179991723	Sep 11 11:27:28 PM UTC 24	Sep 11 11:31:34 PM UTC 24	2976134736 ps
T933	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.324329760	Sep 11 10:44:29 PM UTC 24	Sep 11 11:32:48 PM UTC 24	31979028376 ps
T934	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.2574558063	Sep 11 11:27:28 PM UTC 24	Sep 11 11:32:49 PM UTC 24	2617986552 ps
T382	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1184655202	Sep 11 10:25:46 PM UTC 24	Sep 11 11:33:02 PM UTC 24	15703701400 ps
T935	/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1097272916	Sep 11 10:24:26 PM UTC 24	Sep 11 11:33:26 PM UTC 24	14583847440 ps