Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	167315	1			T92	7		T93	4		T97	38
values[2]	4492	1			T467	2		T462	4		T561	2
values[3]	1919	1			T443	9		T431	1		T817	47
values[4]	1378	1			T443	18		T431	2		T817	74
values[5]	1040	1			T443	12		T431	2		T817	57
values[6]	983	1			T443	28		T431	1		T817	13
values[7]	891	1			T443	57		T431	1		T817	2
values[8]	782	1			T443	91		T431	1		T817	2
values[9]	750	1			T443	110		T431	3		T822	5
values[10]	669	1			T443	67		T431	2		T822	1
values[11]	578	1			T443	53		T431	3		T822	3
values[12]	462	1			T443	37		T431	2		T822	2
values[13]	374	1			T443	24		T431	2		T822	3
values[14]	360	1			T443	6		T431	2		T822	1
values[15]	429	1			T443	1		T431	2		T822	1
values[16]	452	1			T431	2		T822	3		T476	5
values[17]	364	1			T431	1		T822	3		T476	5
values[18]	406	1			T431	3		T822	2		T476	1
values[19]	291	1			T431	3		T822	1		T476	1
values[20]	273	1			T431	7		T822	2		T682	1
values[21]	269	1			T431	2		T822	1		T682	1
values[22]	264	1			T431	2		T822	1		T682	1
values[23]	250	1			T431	1		T822	1		T682	1
values[24]	241	1			T431	2		T822	2		T682	1
values[25]	263	1			T431	3		T822	2		T682	1
values[26]	275	1			T431	5		T822	2		T682	1
values[27]	247	1			T431	2		T822	3		T682	1
values[28]	201	1			T431	1		T822	2		T682	1
values[29]	169	1			T431	2		T822	2		T682	1
values[30]	166	1			T431	6		T822	5		T682	1
values[31]	164	1			T431	3		T822	1		T682	1
values[32]	137	1			T431	6		T822	2		T682	1
values[33]	114	1			T431	2		T822	4		T682	1
values[34]	117	1			T431	1		T822	3		T682	1
values[35]	131	1			T431	2		T822	1		T682	1
values[36]	138	1			T431	1		T822	2		T682	1
values[37]	127	1			T431	1		T822	1		T682	1
values[38]	111	1			T431	4		T822	3		T682	1
values[39]	105	1			T431	2		T822	1		T682	1
values[40]	122	1			T431	7		T822	2		T682	1
values[41]	93	1			T431	4		T822	2		T682	1
values[42]	83	1			T431	5		T822	1		T682	1
values[43]	91	1			T431	7		T822	4		T682	1
values[44]	71	1			T431	2		T822	1		T682	1
values[45]	71	1			T431	2		T822	1		T682	1
values[46]	69	1			T431	1		T822	1		T682	1
values[47]	69	1			T431	1		T822	3		T682	1
values[48]	86	1			T431	3		T822	1		T682	1
values[49]	69	1			T431	1		T822	6		T682	1
values[50]	80	1			T431	2		T822	7		T682	1
values[51]	77	1			T431	3		T822	1		T682	1
values[52]	74	1			T431	5		T822	5		T682	1
values[53]	62	1			T431	2		T822	2		T682	1
values[54]	61	1			T431	2		T822	3		T682	1
values[55]	70	1			T431	1		T822	2		T682	1
values[56]	78	1			T431	4		T822	4		T682	1
values[57]	65	1			T431	2		T822	2		T682	1
values[58]	71	1			T431	1		T822	3		T682	1
values[59]	68	1			T431	4		T822	2		T682	1
values[60]	71	1			T431	1		T822	2		T682	1
values[61]	61	1			T431	2		T822	1		T682	1
values[62]	87	1			T431	3		T822	2		T682	1
values[63]	75	1			T431	3		T822	2		T682	1
values[64]	68	1			T431	1		T822	2		T682	1
values[65]	73	1			T431	5		T822	2		T682	1
values[66]	85	1			T431	1		T822	4		T682	1
values[67]	74	1			T431	3		T822	2		T682	1
values[68]	62	1			T431	3		T822	2		T682	1
values[69]	72	1			T431	2		T822	3		T682	1
values[70]	63	1			T431	3		T822	2		T682	1
values[71]	68	1			T431	2		T822	1		T682	1
values[72]	68	1			T431	2		T822	2		T682	1
values[73]	79	1			T431	2		T822	3		T682	1
values[74]	82	1			T431	4		T822	2		T682	1
values[75]	76	1			T431	1		T822	1		T682	1
values[76]	80	1			T431	3		T822	1		T682	1
values[77]	84	1			T431	2		T822	1		T682	1
values[78]	84	1			T431	5		T822	2		T682	1
values[79]	89	1			T431	5		T822	1		T682	1
values[80]	77	1			T431	4		T822	1		T682	1
values[81]	105	1			T431	8		T822	4		T682	1
values[82]	104	1			T431	6		T822	1		T682	1
values[83]	93	1			T431	5		T822	2		T682	1
values[84]	112	1			T431	3		T822	4		T682	1
values[85]	102	1			T431	1		T822	4		T682	1
values[86]	79	1			T431	2		T822	1		T682	1
values[87]	92	1			T431	2		T822	1		T682	1
values[88]	82	1			T431	1		T822	3		T682	1
values[89]	106	1			T431	3		T822	2		T682	1
values[90]	97	1			T431	1		T822	1		T682	1
values[91]	84	1			T431	4		T822	4		T682	5
values[92]	111	1			T431	5		T822	1		T682	4
values[93]	124	1			T431	7		T822	3		T682	6
values[94]	123	1			T431	6		T822	2		T682	4
values[95]	114	1			T431	1		T822	5		T682	2
values[96]	107	1			T431	3		T822	5		T682	1
values[97]	109	1			T431	1		T822	1		T682	1
values[98]	116	1			T431	3		T822	4		T682	1
values[99]	95	1			T431	2		T822	3		T682	2
values[100]	116	1			T431	4		T822	4		T682	2
values[101]	119	1			T431	1		T822	1		T682	3
values[102]	113	1			T431	13		T822	2		T682	5
values[103]	133	1			T431	4		T822	2		T682	3
values[104]	116	1			T431	10		T822	4		T682	3
values[105]	106	1			T431	5		T822	4		T682	3
values[106]	116	1			T431	1		T822	1		T682	2
values[107]	103	1			T431	1		T822	3		T682	4
values[108]	114	1			T431	3		T822	1		T682	1
values[109]	110	1			T431	2		T822	1		T682	1
values[110]	119	1			T431	6		T822	1		T682	1
values[111]	128	1			T431	6		T822	2		T682	3
values[112]	122	1			T431	8		T822	2		T682	4
values[113]	122	1			T431	6		T822	5		T682	7
values[114]	108	1			T431	3		T822	4		T682	1
values[115]	137	1			T431	9		T822	7		T682	4
values[116]	117	1			T431	2		T822	1		T682	5
values[117]	139	1			T431	4		T822	2		T682	2
values[118]	129	1			T431	5		T822	7		T682	2
values[119]	116	1			T431	3		T822	6		T682	2
values[120]	123	1			T431	1		T822	4		T682	6
values[121]	143	1			T431	2		T822	4		T682	6
values[122]	133	1			T431	3		T822	3		T682	1
values[123]	155	1			T431	8		T822	5		T682	1
values[124]	242	1			T431	10		T822	10		T682	2
values[125]	534	1			T431	30		T822	61		T682	1
values[126]	1109	1			T431	47		T822	119		T682	11
values[127]	3107	1			T431	24		T822	45		T682	96
values[128]	5220	1			T431	3		T822	7		T682	208