Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146847	1			T92	1		T93	6		T97	38
values[2]	10634	1			T93	1		T99	1		T249	1
values[3]	3722	1			T569	8		T492	3		T822	45
values[4]	2246	1			T569	10		T492	6		T822	35
values[5]	1493	1			T569	4		T492	7		T822	32
values[6]	1079	1			T569	7		T492	10		T822	20
values[7]	720	1			T569	11		T492	10		T822	12
values[8]	579	1			T569	10		T492	6		T682	2
values[9]	480	1			T569	8		T492	11		T682	1
values[10]	463	1			T569	6		T492	8		T682	1
values[11]	347	1			T569	4		T492	11		T682	1
values[12]	368	1			T569	4		T492	12		T682	1
values[13]	325	1			T569	8		T492	7		T682	1
values[14]	343	1			T569	10		T492	4		T682	1
values[15]	283	1			T569	6		T492	6		T682	1
values[16]	309	1			T569	9		T492	13		T682	1
values[17]	298	1			T569	2		T492	7		T682	1
values[18]	348	1			T569	9		T492	7		T682	1
values[19]	266	1			T569	3		T492	4		T682	1
values[20]	290	1			T569	6		T492	6		T682	1
values[21]	326	1			T569	13		T492	7		T682	1
values[22]	307	1			T569	11		T492	9		T682	1
values[23]	267	1			T569	6		T492	3		T682	1
values[24]	240	1			T569	3		T492	4		T682	1
values[25]	244	1			T569	8		T492	9		T682	1
values[26]	286	1			T569	5		T492	13		T682	1
values[27]	325	1			T569	19		T492	8		T682	1
values[28]	257	1			T569	11		T492	8		T682	1
values[29]	294	1			T569	7		T492	6		T682	1
values[30]	257	1			T569	7		T492	6		T682	1
values[31]	263	1			T569	15		T492	8		T682	1
values[32]	302	1			T569	9		T492	16		T682	1
values[33]	253	1			T569	7		T492	10		T682	1
values[34]	243	1			T569	4		T492	11		T682	1
values[35]	305	1			T569	7		T492	8		T682	1
values[36]	288	1			T569	5		T492	3		T682	1
values[37]	295	1			T569	7		T492	13		T682	1
values[38]	279	1			T569	6		T492	10		T682	1
values[39]	254	1			T569	4		T492	2		T682	1
values[40]	234	1			T569	7		T492	6		T682	1
values[41]	300	1			T569	6		T492	4		T682	1
values[42]	240	1			T569	9		T492	15		T682	1
values[43]	232	1			T569	12		T492	12		T682	1
values[44]	293	1			T569	5		T492	12		T682	1
values[45]	231	1			T569	4		T492	11		T682	1
values[46]	243	1			T569	9		T492	6		T682	1
values[47]	206	1			T569	7		T492	8		T682	1
values[48]	197	1			T569	9		T492	7		T682	2
values[49]	207	1			T492	5		T682	1		T469	6
values[50]	252	1			T492	5		T682	1		T469	12
values[51]	248	1			T492	8		T682	1		T469	7
values[52]	217	1			T492	10		T682	1		T469	10
values[53]	170	1			T492	7		T682	1		T469	10
values[54]	167	1			T492	5		T682	1		T469	5
values[55]	211	1			T492	9		T682	1		T469	12
values[56]	194	1			T492	9		T682	1		T469	10
values[57]	196	1			T492	6		T682	1		T469	10
values[58]	187	1			T492	6		T682	1		T469	7
values[59]	190	1			T492	12		T682	1		T469	5
values[60]	180	1			T492	6		T682	1		T617	7
values[61]	172	1			T492	7		T682	1		T628	11
values[62]	150	1			T492	6		T682	1		T628	7
values[63]	122	1			T492	5		T682	1		T628	4
values[64]	168	1			T492	7		T682	1		T628	9
values[65]	119	1			T492	4		T682	1		T628	7
values[66]	122	1			T492	7		T682	1		T628	6
values[67]	112	1			T492	5		T682	1		T628	11
values[68]	125	1			T682	1		T628	11		T834	1
values[69]	88	1			T682	1		T628	18		T834	1
values[70]	92	1			T682	1		T628	6		T834	1
values[71]	86	1			T682	1		T628	11		T834	1
values[72]	84	1			T682	1		T628	5		T834	1
values[73]	86	1			T682	1		T628	8		T834	1
values[74]	81	1			T682	1		T628	14		T834	1
values[75]	85	1			T682	1		T628	11		T834	1
values[76]	73	1			T682	1		T628	15		T834	1
values[77]	108	1			T682	1		T628	29		T834	1
values[78]	90	1			T682	1		T628	17		T834	1
values[79]	91	1			T682	1		T628	24		T834	1
values[80]	106	1			T682	1		T628	20		T834	1
values[81]	81	1			T682	1		T628	13		T834	1
values[82]	71	1			T682	1		T628	7		T834	1
values[83]	98	1			T682	1		T628	5		T834	1
values[84]	110	1			T682	1		T628	7		T834	1
values[85]	93	1			T682	1		T628	4		T834	1
values[86]	84	1			T682	1		T628	4		T834	1
values[87]	81	1			T682	1		T628	3		T834	1
values[88]	120	1			T682	1		T628	5		T834	1
values[89]	83	1			T682	1		T628	6		T834	1
values[90]	74	1			T682	2		T628	4		T834	1
values[91]	80	1			T682	1		T628	8		T834	1
values[92]	77	1			T682	2		T628	3		T834	1
values[93]	98	1			T682	4		T628	4		T834	1
values[94]	103	1			T682	9		T628	2		T834	1
values[95]	112	1			T682	2		T628	5		T834	1
values[96]	98	1			T682	7		T628	11		T834	1
values[97]	89	1			T682	2		T628	5		T834	1
values[98]	95	1			T682	7		T628	6		T834	1
values[99]	78	1			T682	2		T628	5		T834	1
values[100]	87	1			T682	1		T628	4		T834	1
values[101]	90	1			T682	1		T628	5		T834	1
values[102]	95	1			T682	1		T628	2		T834	1
values[103]	80	1			T682	1		T628	2		T834	1
values[104]	120	1			T682	1		T628	12		T834	8
values[105]	99	1			T682	4		T628	5		T834	4
values[106]	77	1			T682	1		T628	3		T834	2
values[107]	91	1			T682	2		T628	1		T834	2
values[108]	93	1			T682	4		T628	5		T834	2
values[109]	97	1			T682	1		T628	5		T834	1
values[110]	89	1			T682	1		T628	4		T834	1
values[111]	77	1			T682	4		T628	1		T834	3
values[112]	85	1			T682	2		T834	2		T849	2
values[113]	63	1			T682	4		T834	1		T849	3
values[114]	80	1			T682	1		T834	1		T849	1
values[115]	86	1			T682	1		T834	2		T849	4
values[116]	72	1			T682	3		T834	2		T849	2
values[117]	75	1			T682	2		T834	1		T849	5
values[118]	74	1			T682	2		T834	2		T849	1
values[119]	67	1			T682	1		T834	1		T849	3
values[120]	79	1			T682	4		T834	1		T849	1
values[121]	66	1			T682	1		T834	1		T849	1
values[122]	90	1			T682	2		T834	2		T849	2
values[123]	79	1			T682	1		T834	2		T849	1
values[124]	80	1			T682	1		T834	1		T849	1
values[125]	72	1			T682	1		T834	2		T849	1
values[126]	125	1			T682	3		T834	3		T849	1
values[127]	911	1			T682	31		T834	49		T849	17
values[128]	7628	1			T682	282		T834	369		T849	277