Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123172 |
1 |
|
|
T92 |
7 |
|
T93 |
6 |
|
T97 |
14 |
| auto[1] |
66504 |
1 |
|
|
T93 |
1 |
|
T97 |
17 |
|
T98 |
17 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47858 |
1 |
|
|
T92 |
2 |
|
T93 |
1 |
|
T97 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
133466 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56210 |
1 |
|
|
T92 |
2 |
|
T93 |
4 |
|
T97 |
6 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14959 |
1 |
|
|
T92 |
1 |
|
T99 |
1 |
|
T399 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125151 |
1 |
|
|
T92 |
4 |
|
T93 |
4 |
|
T97 |
14 |
| auto[1] |
70730 |
1 |
|
|
T93 |
4 |
|
T97 |
18 |
|
T98 |
15 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49441 |
1 |
|
|
T92 |
2 |
|
T93 |
4 |
|
T97 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137965 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57916 |
1 |
|
|
T93 |
2 |
|
T97 |
7 |
|
T98 |
6 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15374 |
1 |
|
|
T93 |
1 |
|
T97 |
1 |
|
T98 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121654 |
1 |
|
|
T92 |
9 |
|
T93 |
4 |
|
T97 |
24 |
| auto[1] |
65967 |
1 |
|
|
T93 |
1 |
|
T97 |
21 |
|
T98 |
6 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48545 |
1 |
|
|
T92 |
3 |
|
T93 |
3 |
|
T97 |
6 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131537 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56084 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T97 |
9 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15135 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T98 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132393 |
1 |
|
|
T92 |
3 |
|
T93 |
8 |
|
T97 |
31 |
| auto[1] |
69277 |
1 |
|
|
T92 |
2 |
|
T93 |
1 |
|
T97 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51056 |
1 |
|
|
T92 |
2 |
|
T93 |
3 |
|
T97 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
142094 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
59576 |
1 |
|
|
T92 |
3 |
|
T93 |
2 |
|
T97 |
11 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15789 |
1 |
|
|
T92 |
2 |
|
T93 |
1 |
|
T97 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126991 |
1 |
|
|
T92 |
4 |
|
T93 |
5 |
|
T94 |
387 |
| auto[1] |
65655 |
1 |
|
|
T92 |
1 |
|
T94 |
12 |
|
T97 |
17 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48513 |
1 |
|
|
T92 |
2 |
|
T93 |
4 |
|
T94 |
134 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135981 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56665 |
1 |
|
|
T92 |
1 |
|
T93 |
4 |
|
T94 |
126 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14983 |
1 |
|
|
T93 |
3 |
|
T94 |
51 |
|
T97 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127586 |
1 |
|
|
T92 |
2 |
|
T97 |
17 |
|
T98 |
20 |
| auto[1] |
68831 |
1 |
|
|
T92 |
5 |
|
T93 |
2 |
|
T97 |
26 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50236 |
1 |
|
|
T92 |
1 |
|
T97 |
7 |
|
T98 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137641 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58776 |
1 |
|
|
T92 |
4 |
|
T97 |
7 |
|
T98 |
8 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15808 |
1 |
|
|
T92 |
1 |
|
T97 |
1 |
|
T98 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133841 |
1 |
|
|
T92 |
10 |
|
T93 |
6 |
|
T97 |
23 |
| auto[1] |
72909 |
1 |
|
|
T92 |
1 |
|
T97 |
20 |
|
T98 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
52710 |
1 |
|
|
T92 |
4 |
|
T93 |
1 |
|
T97 |
6 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
145285 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
61465 |
1 |
|
|
T92 |
4 |
|
T93 |
1 |
|
T97 |
12 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16418 |
1 |
|
|
T97 |
4 |
|
T98 |
2 |
|
T99 |
4 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131736 |
1 |
|
|
T92 |
2 |
|
T93 |
2 |
|
T97 |
17 |
| auto[1] |
66321 |
1 |
|
|
T92 |
5 |
|
T97 |
29 |
|
T98 |
19 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51121 |
1 |
|
|
T92 |
2 |
|
T93 |
1 |
|
T97 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
138877 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
59180 |
1 |
|
|
T97 |
15 |
|
T98 |
6 |
|
T99 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15930 |
1 |
|
|
T97 |
1 |
|
T98 |
2 |
|
T99 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129419 |
1 |
|
|
T92 |
4 |
|
T97 |
14 |
|
T98 |
10 |
| auto[1] |
65319 |
1 |
|
|
T93 |
2 |
|
T97 |
25 |
|
T98 |
13 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50407 |
1 |
|
|
T92 |
1 |
|
T97 |
3 |
|
T98 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136726 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58012 |
1 |
|
|
T92 |
1 |
|
T97 |
8 |
|
T98 |
5 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15709 |
1 |
|
|
T399 |
1 |
|
T249 |
1 |
|
T422 |
10 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129483 |
1 |
|
|
T92 |
3 |
|
T93 |
7 |
|
T97 |
50 |
| auto[1] |
71654 |
1 |
|
|
T97 |
3 |
|
T99 |
4 |
|
T399 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51376 |
1 |
|
|
T92 |
2 |
|
T93 |
3 |
|
T97 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
141074 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
60063 |
1 |
|
|
T93 |
4 |
|
T97 |
11 |
|
T98 |
8 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16117 |
1 |
|
|
T93 |
3 |
|
T97 |
2 |
|
T99 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133736 |
1 |
|
|
T93 |
2 |
|
T97 |
14 |
|
T98 |
12 |
| auto[1] |
65415 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T97 |
22 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51402 |
1 |
|
|
T93 |
2 |
|
T97 |
6 |
|
T98 |
5 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
139476 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
59675 |
1 |
|
|
T93 |
2 |
|
T97 |
7 |
|
T98 |
6 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16211 |
1 |
|
|
T93 |
1 |
|
T97 |
1 |
|
T98 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
992886 |
1 |
|
|
T92 |
54 |
|
T93 |
10 |
|
T94 |
124 |
| auto[1] |
544984 |
1 |
|
|
T92 |
3 |
|
T93 |
12 |
|
T94 |
22 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
394239 |
1 |
|
|
T92 |
19 |
|
T93 |
11 |
|
T94 |
53 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
1070511 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
467359 |
1 |
|
|
T92 |
20 |
|
T93 |
7 |
|
T94 |
38 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
124786 |
1 |
|
|
T92 |
7 |
|
T93 |
5 |
|
T94 |
15 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130911 |
1 |
|
|
T92 |
7 |
|
T93 |
2 |
|
T97 |
13 |
| auto[1] |
72121 |
1 |
|
|
T93 |
2 |
|
T97 |
28 |
|
T98 |
16 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51091 |
1 |
|
|
T92 |
1 |
|
T93 |
2 |
|
T97 |
8 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
142983 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
60049 |
1 |
|
|
T92 |
3 |
|
T97 |
15 |
|
T98 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15754 |
1 |
|
|
T97 |
3 |
|
T99 |
2 |
|
T249 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127845 |
1 |
|
|
T92 |
8 |
|
T93 |
1 |
|
T97 |
7 |
| auto[1] |
67460 |
1 |
|
|
T93 |
2 |
|
T97 |
26 |
|
T98 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49922 |
1 |
|
|
T92 |
6 |
|
T97 |
3 |
|
T98 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137303 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58002 |
1 |
|
|
T92 |
1 |
|
T93 |
2 |
|
T97 |
7 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15484 |
1 |
|
|
T92 |
1 |
|
T99 |
5 |
|
T249 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126148 |
1 |
|
|
T92 |
4 |
|
T93 |
2 |
|
T97 |
29 |
| auto[1] |
67494 |
1 |
|
|
T92 |
1 |
|
T93 |
3 |
|
T97 |
6 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49871 |
1 |
|
|
T92 |
4 |
|
T93 |
2 |
|
T97 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
134850 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58792 |
1 |
|
|
T92 |
3 |
|
T93 |
2 |
|
T97 |
7 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15712 |
1 |
|
|
T92 |
2 |
|
T93 |
1 |
|
T99 |
5 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122583 |
1 |
|
|
T93 |
4 |
|
T97 |
35 |
|
T98 |
18 |
| auto[1] |
71595 |
1 |
|
|
T92 |
3 |
|
T97 |
3 |
|
T98 |
10 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49616 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T97 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136479 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57699 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T97 |
13 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15490 |
1 |
|
|
T92 |
1 |
|
T399 |
1 |
|
T249 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125529 |
1 |
|
|
T92 |
9 |
|
T93 |
1 |
|
T97 |
19 |
| auto[1] |
70798 |
1 |
|
|
T93 |
1 |
|
T97 |
20 |
|
T98 |
13 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50671 |
1 |
|
|
T92 |
3 |
|
T93 |
1 |
|
T97 |
7 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137828 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58499 |
1 |
|
|
T92 |
6 |
|
T93 |
1 |
|
T97 |
9 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15827 |
1 |
|
|
T92 |
3 |
|
T98 |
1 |
|
T99 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131196 |
1 |
|
|
T92 |
6 |
|
T93 |
2 |
|
T97 |
21 |
| auto[1] |
67316 |
1 |
|
|
T93 |
1 |
|
T97 |
18 |
|
T98 |
7 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49885 |
1 |
|
|
T92 |
3 |
|
T97 |
7 |
|
T98 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
139882 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58630 |
1 |
|
|
T92 |
2 |
|
T97 |
11 |
|
T98 |
7 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15520 |
1 |
|
|
T92 |
1 |
|
T97 |
4 |
|
T98 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132331 |
1 |
|
|
T92 |
6 |
|
T93 |
3 |
|
T97 |
26 |
| auto[1] |
73577 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T97 |
12 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51558 |
1 |
|
|
T92 |
2 |
|
T93 |
1 |
|
T97 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
144565 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
61343 |
1 |
|
|
T92 |
2 |
|
T93 |
2 |
|
T97 |
16 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16000 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T97 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130494 |
1 |
|
|
T92 |
4 |
|
T93 |
3 |
|
T97 |
19 |
| auto[1] |
68191 |
1 |
|
|
T97 |
24 |
|
T98 |
11 |
|
T99 |
6 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51852 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T97 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137903 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
60782 |
1 |
|
|
T92 |
1 |
|
T93 |
1 |
|
T97 |
10 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16553 |
1 |
|
|
T92 |
1 |
|
T97 |
2 |
|
T98 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126196 |
1 |
|
|
T92 |
7 |
|
T93 |
1 |
|
T97 |
32 |
| auto[1] |
67021 |
1 |
|
|
T92 |
2 |
|
T93 |
1 |
|
T97 |
14 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48810 |
1 |
|
|
T92 |
6 |
|
T97 |
7 |
|
T98 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135803 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57414 |
1 |
|
|
T92 |
1 |
|
T97 |
14 |
|
T98 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15268 |
1 |
|
|
T92 |
1 |
|
T97 |
2 |
|
T99 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128253 |
1 |
|
|
T92 |
6 |
|
T93 |
3 |
|
T97 |
23 |
| auto[1] |
71098 |
1 |
|
|
T93 |
2 |
|
T97 |
13 |
|
T98 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51114 |
1 |
|
|
T93 |
1 |
|
T97 |
4 |
|
T98 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
138501 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
60850 |
1 |
|
|
T92 |
2 |
|
T93 |
2 |
|
T97 |
12 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16345 |
1 |
|
|
T93 |
1 |
|
T97 |
1 |
|
T99 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125424 |
1 |
|
|
T92 |
6 |
|
T93 |
6 |
|
T97 |
22 |
| auto[1] |
70284 |
1 |
|
|
T92 |
1 |
|
T93 |
3 |
|
T97 |
15 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51293 |
1 |
|
|
T92 |
3 |
|
T93 |
4 |
|
T97 |
6 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135495 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
60213 |
1 |
|
|
T93 |
5 |
|
T97 |
6 |
|
T98 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16290 |
1 |
|
|
T93 |
2 |
|
T99 |
2 |
|
T399 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123736 |
1 |
|
|
T92 |
3 |
|
T93 |
4 |
|
T97 |
44 |
| auto[1] |
67553 |
1 |
|
|
T93 |
2 |
|
T97 |
15 |
|
T98 |
8 |