Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	446	1			T94	1		T467	2		T488	4
all_values[1]	505	1			T467	1		T488	2		T492	3
all_values[2]	489	1			T467	1		T443	1		T698	1
all_values[3]	470	1			T467	1		T560	2		T570	1
all_values[4]	454	1			T443	2		T431	1		T665	1
all_values[5]	476	1			T467	2		T443	1		T566	1
all_values[6]	501	1			T698	1		T569	1		T431	1
all_values[7]	474	1			T467	1		T488	1		T431	1
all_values[8]	480	1			T443	1		T569	1		T571	2
all_values[9]	482	1			T698	1		T560	1		T569	1
all_values[10]	466	1			T467	1		T843	1		T492	1
all_values[11]	469	1			T571	1		T431	1		T681	1
all_values[12]	490	1			T488	3		T431	1		T492	1
all_values[13]	486	1			T467	1		T566	1		T569	1
all_values[14]	498	1			T488	1		T492	3		T817	2
all_values[15]	476	1			T467	3		T566	1		T698	1
all_values[16]	438	1			T571	1		T488	1		T431	2
all_values[17]	467	1			T698	1		T569	1		T488	1
all_values[18]	471	1			T566	1		T698	1		T488	1
all_values[19]	490	1			T443	1		T488	2		T431	1
all_values[20]	435	1			T566	1		T571	1		T431	2
all_values[21]	459	1			T560	1		T569	1		T488	2
all_values[22]	474	1			T443	1		T560	1		T488	3
all_values[23]	480	1			T467	2		T698	1		T560	1
all_values[24]	489	1			T467	1		T560	2		T488	3
all_values[25]	460	1			T467	1		T443	1		T492	3
all_values[26]	477	1			T443	1		T571	1		T488	1
all_values[27]	480	1			T467	2		T443	2		T571	1
all_values[28]	472	1			T467	2		T443	1		T566	1
all_values[29]	463	1			T443	1		T560	1		T569	1
all_values[30]	459	1			T569	1		T488	1		T681	1
all_values[31]	478	1			T467	1		T488	1		T843	1
all_values[32]	477	1			T566	1		T488	1		T665	1
all_values[33]	490	1			T569	1		T488	2		T492	1
all_values[34]	470	1			T488	1		T492	1		T817	3
all_values[35]	480	1			T467	1		T698	1		T560	1
all_values[36]	465	1			T488	1		T431	1		T817	5
all_values[37]	470	1			T467	1		T570	1		T571	1
all_values[38]	503	1			T443	1		T488	2		T431	2
all_values[39]	448	1			T566	1		T570	1		T488	1
all_values[40]	465	1			T467	1		T443	1		T665	1
all_values[41]	499	1			T467	1		T698	1		T571	2
all_values[42]	435	1			T467	1		T566	1		T569	1
all_values[43]	470	1			T566	1		T569	2		T431	1
all_values[44]	430	1			T467	1		T443	2		T488	3
all_values[45]	514	1			T467	2		T569	1		T431	3
all_values[46]	486	1			T467	1		T698	1		T488	2
all_values[47]	475	1			T566	1		T665	1		T817	1
all_values[48]	449	1			T467	3		T566	1		T560	1
all_values[49]	491	1			T94	1		T560	1		T488	2