Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3544	1			T467	7		T464	3		T563	3
all_values[1]	3485	1			T467	3		T464	6		T562	1
all_values[2]	3441	1			T467	3		T464	2		T563	1
all_values[3]	3525	1			T467	2		T464	1		T566	7
all_values[4]	3423	1			T467	4		T464	2		T562	2
all_values[5]	3552	1			T467	7		T464	1		T566	9
all_values[6]	3571	1			T467	4		T464	2		T562	1
all_values[7]	3476	1			T467	4		T464	1		T562	1
all_values[8]	3496	1			T467	4		T464	3		T566	6
all_values[9]	3519	1			T467	5		T464	4		T562	1
all_values[10]	3469	1			T467	7		T464	2		T562	1
all_values[11]	3553	1			T467	7		T464	4		T566	7
all_values[12]	3598	1			T467	4		T464	3		T562	1
all_values[13]	3462	1			T467	6		T464	2		T566	5
all_values[14]	3510	1			T467	5		T464	3		T566	7
all_values[15]	3473	1			T467	7		T464	1		T562	2
all_values[16]	3477	1			T467	5		T464	1		T563	1
all_values[17]	3465	1			T467	8		T464	5		T562	1
all_values[18]	3458	1			T467	5		T464	4		T566	3
all_values[19]	3463	1			T467	3		T464	1		T563	2
all_values[20]	3531	1			T467	5		T464	1		T562	1
all_values[21]	3553	1			T467	7		T464	3		T562	1
all_values[22]	3592	1			T467	3		T464	2		T562	1
all_values[23]	3498	1			T467	2		T464	4		T566	2
all_values[24]	3477	1			T467	7		T464	1		T562	1
all_values[25]	3476	1			T467	5		T464	1		T562	1
all_values[26]	3518	1			T467	3		T464	3		T563	1
all_values[27]	3554	1			T467	2		T464	2		T566	4
all_values[28]	3538	1			T467	4		T464	1		T566	3
all_values[29]	3522	1			T467	2		T464	3		T563	1
all_values[30]	3524	1			T467	1		T464	2		T566	4
all_values[31]	3412	1			T467	3		T464	3		T566	5
all_values[32]	3467	1			T467	8		T464	2		T563	2
all_values[33]	3580	1			T467	7		T464	2		T562	1
all_values[34]	3444	1			T467	2		T464	3		T562	1
all_values[35]	3581	1			T467	4		T464	2		T562	1
all_values[36]	3576	1			T467	3		T464	2		T563	1
all_values[37]	3531	1			T467	1		T464	3		T562	1
all_values[38]	3538	1			T467	2		T464	1		T562	2
all_values[39]	3526	1			T467	5		T563	1		T566	3
all_values[40]	3357	1			T467	5		T464	2		T562	1
all_values[41]	3525	1			T467	10		T464	3		T563	1
all_values[42]	3540	1			T464	1		T562	1		T566	5
all_values[43]	3432	1			T467	6		T464	1		T562	1
all_values[44]	3478	1			T467	5		T464	2		T562	2
all_values[45]	3551	1			T467	3		T464	5		T562	1
all_values[46]	3498	1			T467	4		T562	3		T566	7
all_values[47]	3417	1			T467	6		T464	3		T562	2
all_values[48]	3408	1			T467	6		T464	2		T562	4
all_values[49]	3470	1			T467	3		T464	2		T566	3
all_values[50]	3501	1			T467	5		T464	3		T566	8
all_values[51]	3493	1			T467	6		T464	1		T566	4
all_values[52]	3485	1			T467	5		T464	3		T562	1
all_values[53]	3522	1			T464	2		T566	6		T560	2
all_values[54]	3525	1			T467	3		T464	2		T566	3
all_values[55]	3394	1			T467	7		T464	3		T562	1
all_values[56]	3437	1			T467	4		T562	1		T563	1
all_values[57]	3490	1			T467	4		T464	5		T562	1
all_values[58]	3533	1			T467	3		T464	1		T562	1
all_values[59]	3392	1			T467	5		T464	1		T563	1
all_values[60]	3549	1			T467	8		T464	1		T563	1
all_values[61]	3448	1			T467	6		T464	3		T562	1
all_values[62]	3605	1			T467	5		T562	1		T566	5
all_values[63]	3572	1			T467	3		T562	1		T566	6