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 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T72,T112,T116
1	0	1	Covered	T45,T78,T79
1	1	0	Covered	T407,T488,T409
1	1	1	Covered	T45,T78,T79

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T78,T79
1	0	1	Covered	T45,T78,T79
1	1	0	Covered	T462,T408,T488
1	1	1	Covered	T116,T135,T460

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T78,T79
1	0	1	Covered	T78,T263,T434
1	1	0	Covered	T422,T464,T432
1	1	1	Covered	T562,T463,T565

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T464,T462,T570
1	1	0	Covered	T666,T667
1	1	1	Covered	T3,T4,T6

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T99,T562,T462
1	1	0	Covered	T566,T668,T669
1	1	1	Covered	T3,T4,T6

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T6
1	0	1	Covered	T462,T565,T557
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4