Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T130 T320 T325 | T130 T320 T325 | T130 T320 T326 | T130 T320 T326 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T130 T320 T325 | T131 T132 T320 | T131 T132 T320 | T131 T132 T320 | T131 T132 T320 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T131 T132 T320 | T29 T64 T320 | T29 T64 T320 | T29 T64 T320 | T29 T64 T320 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T29 T64 T320 | T39 T65 T320 | T39 T65 T320 | T39 T65 T320 | T39 T65 T320 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T39 T65 T320 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T11 T125 T219 | T125 T182 T183 | T125 T182 T183 | T125 T182 T183 | T125 T182 T183 | T15 T125 T50 | T125 T182 T183 | T125 T182 T183 | T59 T329 T137 | T59 T329 T137 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T58 T59 T329 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T60 T329 T138 | T60 T329 T138 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T60 T329 T61 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T62 T329 T63 | T62 T329 T63 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T62 T329 T63 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T3 T125 T134 | T3 T125 T134 | T125 T182 T183 | T125 T182 T183 | T125 T182 T183 | T45 T78 T234 | T79 T111 T186 | T184 T329 T263 | T186 T329 T332 | T125 T182 T183 | T125 T182 T183 | T125 T182 T183 | T125 T182 T183 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T4 T25 T14 | T66 T320 T228 | T139 T329 T140 | T333 T236 T329 | T235 T236 T232 | T172 T125 T334 | T125 T182 T183 | T5 T321 T145 | T5 T321 T145 | T321 T145 T329 | T321 T145 T329 | T5 T321 T145 | T329 T330 T331 | T322 T323 T329 | T329 T330 T331 | T329 T330 T331 | T125 T182 T183 | T125 T182 T183 | T125 T182 T183 | T324 T125 T175 | T125 T182 T183 | T329 T330 T331 | T335 T329 T336 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T335 T329 T336 | T329 T330 T331 | T335 T329 T336 | T329 T330 T331
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T250 T251 T319 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T15 T11 T28 | T15 T250 T125 | T15 T250 T125 | T15 T11 T12 | T15 T11 T12 | T15 T250 T125 | T250 T125 T320 | T250 T125 T320 | T59 T250 T125 | T59 T250 T125 | T250 T125 T320 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T250 T125 T320 | T58 T59 T250 | T58 T250 T125 | T250 T125 T320 | T58 T250 T125 | T58 T250 T125 | T58 T250 T125 | T60 T250 T125 | T60 T250 T125 | T250 T125 T320 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T250 T125 T320 | T60 T250 T125 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T62 T250 T125 | T62 T250 T125 | T250 T125 T320 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T250 T125 T320 | T62 T250 T125 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T3 T250 T125 | T3 T250 T125 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T45 T78 T79 | T45 T78 T79 | T45 T78 T79 | T45 T78 T79 | T11 T12 T250 | T11 T12 T250 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T4 T25 T14 | T66 T250 T125 | T139 T250 T125 | T45 T78 T79 | T235 T45 T78 | T172 T250 T125 | T250 T125 T320 | T5 T321 T145 | T5 T321 T145 | T5 T321 T145 | T5 T321 T145 | T5 T321 T145 | T250 T125 T320 | T322 T323 T250 | T322 T323 T250 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T324 T250 T125 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T3 T4 T5 | T3 T15 T29 | T29 T130 T131 | T3 T15 T58 | T4 T5 T25 | T29 T130 T131 | T28 T39 T65 | T15 T58 T11 | T3 T45 T78 | T4 T25 T14 | T5 T321 T145 | T130 T131 T250 | T29 T131 T39 | T28 T39 T65 | T28 T250 T125 | T15 T11 T28 | T58 T59 T60 | T62 T60 T250 | T3 T45 T78 | T45 T78 T79 | T4 T25 T14 | T5 T321 T145 | T250 T125 T320 | T130 T250 T125 | T130 T131 T250 | T29 T131 T64 | T29 T39 T65 | T28 T39 T65 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T11 T28 T250 | T15 T11 T12 | T58 T59 T250 | T60 T250 T125 | T60 T250 T125 | T62 T250 T125 | T62 T250 T125 | T3 T45 T78 | T45 T11 T12 | T250 T125 T320 | T250 T125 T320 | T4 T25 T14 | T5 T321 T145 | T324 T250 T125 | T250 T125 T320 | T130 T250 T125 | T130 T250 T125 | T130 T131 T250 | T131 T250 T125 | T29 T131 T64 | T29 T64 T250 | T29 T64 T250 | T39 T65 T250 | T39 T65 T250 | T28 T39 T65 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T15 T11 T28 | T15 T11 T12 | T59 T250 T125 | T59 T250 T125 | T58 T59 T250 | T58 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T3 T250 T125 | T45 T78 T234 | T45 T78 T79 | T11 T12 T250 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T4 T25 T14 | T235 T45 T78 | T5 T321 T145 | T5 T321 T145 | T250 T125 T320 | T324 T250 T125 | T250 T125 T320 | T250 T125 T320 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T29 T131 T64 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T28 T39 T65 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T15 T11 T28 | T15 T250 T125 | T15 T11 T12 | T15 T250 T125 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T58 T59 T250 | T58 T250 T125 | T58 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T250 T125 T320 | T250 T125 T320 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T250 T125 T320 | T250 T125 T320 | T3 T250 T125 | T250 T125 T320 | T45 T78 T79 | T45 T78 T79 | T45 T11 T12 | T11 T12 T250 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T4 T25 T14 | T139 T66 T250 | T235 T45 T78 | T172 T250 T125 | T5 T321 T145 | T5 T321 T145 | T5 T321 T145 | T322 T323 T250 | T250 T125 T320 | T250 T125 T320 | T324 T250 T125 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T3 T4 T5 | T3 T15 T29 | T4 T5 T25 | T29 T130 T131 | T3 T15 T58 | T4 T5 T25 | T29 T130 T131 | T28 T39 T65 | T15 T58 T11 | T3 T45 T78 | T4 T25 T14 | T5 T321 T145 | T130 T131 T132 | T29 T131 T39 | T28 T39 T65 | T28 T329 T42 | T15 T11 T28 | T58 T59 T60 | T62 T60 T329 | T3 T45 T78 | T79 T184 T111 | T4 T25 T14 | T5 T321 T145 | T335 T329 T336 | T130 T320 T326 | T130 T131 T132 | T29 T131 T64 | T29 T39 T65 | T28 T39 T65 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T11 T28 T125 | T15 T59 T125 | T58 T59 T329 | T60 T329 T138 | T60 T329 T61 | T62 T329 T63 | T62 T329 T63 | T3 T45 T78 | T79 T184 T111 | T320 T327 T328 | T320 T327 T328 | T4 T25 T14 | T5 T321 T145 | T324 T125 T335 | T335 T329 T336 | T335 T329 T336 | T130 T320 T326 | T130 T320 T326 | T130 T131 T132 | T131 T132 T320 | T29 T131 T64 | T29 T64 T320 | T29 T64 T320 | T39 T65 T320 | T320 T327 T328 | T28 T39 T65 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T11 T28 T125 | T15 T125 T50 | T59 T125 T329 | T329 T330 T331 | T58 T59 T329 | T329 T330 T331 | T60 T329 T138 | T329 T330 T331 | T60 T329 T61 | T62 T329 T63 | T62 T329 T63 | T329 T330 T331 | T62 T329 T63 | T3 T125 T329 | T45 T78 T234 | T79 T184 T111 | T125 T320 T182 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T4 T25 T14 | T235 T333 T236 | T5 T321 T145 | T5 T321 T145 | T125 T329 T182 | T324 T125 T335 | T329 T330 T331 | T335 T329 T336 | T335 T329 T336 | T130 T320 T325 | T130 T320 T326 | T130 T320 T326 | T320 T327 T328 | T130 T320 T325 | T131 T132 T320 | T131 T132 T320 | T320 T327 T328 | T320 T327 T328 | T29 T131 T64 | T29 T64 T320 | T29 T64 T320 | T320 T327 T328 | T29 T64 T320 | T39 T65 T320 | T39 T65 T320 | T320 T327 T328 | T320 T327 T328 | T28 T39 T65 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T11 T28 T125 | T125 T182 T183 | T125 T182 T183 | T15 T125 T50 | T59 T125 T329 | T59 T329 T137 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T58 T59 T329 | T329 T330 T331 | T329 T330 T331 | T60 T329 T138 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T60 T329 T61 | T329 T330 T331 | T329 T330 T331 | T62 T329 T63 | T62 T329 T63 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T62 T329 T63 | T329 T330 T331 | T329 T330 T331 | T3 T125 T134 | T125 T182 T183 | T45 T78 T234 | T79 T184 T111 | T186 T125 T329 | T125 T182 T183 | T125 T320 T182 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T4 T25 T14 | T139 T66 T320 | T235 T333 T236 | T172 T125 T334 | T5 T321 T145 | T321 T145 T329 | T5 T321 T145 | T322 T323 T329 | T125 T329 T182 | T125 T182 T183 | T324 T125 T175 | T335 T329 T336 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T335 T329 T336 | T335 T329 T336
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T3 T4 T5 | T3 T15 T29 | T4 T5 T25 | T29 T130 T131 | T3 T15 T58 | T4 T5 T25 | T29 T130 T131 | T28 T39 T65 | T15 T58 T11 | T3 T45 T78 | T4 T25 T14 | T5 T321 T145 | T130 T131 T132 | T29 T131 T39 | T28 T39 T65 | T28 T329 T42 | T15 T11 T28 | T58 T59 T60 | T62 T60 T329 | T3 T45 T78 | T184 T186 T125 | T4 T25 T14 | T5 T321 T145 | T335 T329 T336 | T130 T320 T326 | T130 T131 T132 | T29 T131 T64 | T29 T39 T65 | T28 T39 T65 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T11 T28 T125 | T15 T59 T125 | T58 T59 T329 | T60 T329 T138 | T60 T329 T61 | T62 T329 T63 | T62 T329 T63 | T3 T45 T78 | T184 T186 T125 | T320 T327 T328 | T320 T327 T328 | T4 T25 T14 | T5 T321 T145 | T324 T125 T335 | T335 T329 T336 | T329 T330 T331 | T130 T320 T326 | T320 T327 T328 | T130 T131 T132 | T131 T132 T320 | T29 T131 T64 | T29 T64 T320 | T29 T64 T320 | T39 T65 T320 | T320 T327 T328 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T11 T125 T219 | T15 T125 T50 | T59 T329 T137 | T329 T330 T331 | T58 T59 T329 | T329 T330 T331 | T60 T329 T138 | T329 T330 T331 | T60 T329 T61 | T62 T329 T63 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T3 T125 T329 | T45 T78 T234 | T184 T186 T125 | T125 T320 T182 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T4 T25 T14 | T235 T236 T232 | T5 T321 T145 | T322 T323 T329 | T125 T182 T183 | T125 T335 T329 | T329 T330 T331 | T335 T329 T336 | T329 T330 T331 | T130 T320 T325 | T130 T320 T326 | T320 T327 T328 | T320 T327 T328 | T130 T320 T325 | T131 T132 T320 | T131 T132 T320 | T320 T327 T328 | T320 T327 T328 | T29 T64 T320 | T29 T64 T320 | T320 T327 T328 | T320 T327 T328 | T29 T64 T320 | T39 T65 T320 | T39 T65 T320 | T320 T327 T328 | T320 T327 T328 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T28 T329 T42 | T11 T125 T219 | T125 T182 T183 | T125 T182 T183 | T125 T182 T183 | T59 T329 T137 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T60 T329 T138 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T60 T329 T61 | T329 T330 T331 | T329 T330 T331 | T62 T329 T63 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T3 T125 T134 | T125 T182 T183 | T45 T78 T234 | T184 T329 T263 | T125 T182 T183 | T125 T182 T183 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T320 T327 T328 | T4 T25 T14 | T139 T329 T140 | T235 T236 T232 | T125 T182 T183 | T5 T321 T145 | T321 T145 T329 | T329 T330 T331 | T329 T330 T331 | T125 T182 T183 | T125 T182 T183 | T125 T182 T183 | T335 T329 T336 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T3 T4 T5 | T3 T15 T29 | T4 T5 T25 | T29 T130 T131 | T3 T15 T58 | T4 T5 T25 | T29 T130 T131 | T28 T39 T65 | T15 T58 T11 | T3 T45 T78 | T4 T25 T14 | T5 T321 T145 | T130 T131 T250 | T29 T131 T39 | T28 T39 T65 | T28 T250 T125 | T15 T11 T28 | T58 T59 T60 | T62 T60 T250 | T3 T45 T78 | T45 T78 T79 | T4 T25 T14 | T5 T321 T145 | T250 T125 T320 | T130 T250 T125 | T130 T131 T250 | T29 T131 T64 | T29 T39 T65 | T28 T39 T65 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T11 T28 T250 | T15 T11 T12 | T58 T59 T250 | T60 T250 T125 | T60 T250 T125 | T62 T250 T125 | T62 T250 T125 | T3 T45 T78 | T45 T11 T12 | T250 T125 T320 | T250 T125 T320 | T4 T25 T14 | T5 T321 T145 | T324 T250 T125 | T250 T125 T320 | T250 T125 T320 | T130 T250 T125 | T130 T250 T125 | T130 T131 T250 | T131 T250 T125 | T29 T131 T64 | T29 T64 T250 | T29 T64 T250 | T39 T65 T250 | T39 T65 T250 | T28 T39 T65 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T15 T11 T28 | T15 T11 T12 | T59 T250 T125 | T59 T250 T125 | T58 T59 T250 | T58 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T3 T250 T125 | T45 T78 T234 | T45 T78 T79 | T11 T12 T250 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T4 T25 T14 | T235 T45 T78 | T5 T321 T145 | T5 T321 T145 | T250 T125 T320 | T324 T250 T125 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T130 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T131 T250 T125 | T29 T131 T64 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T29 T64 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T39 T65 T250 | T28 T39 T65 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T28 T250 T125 | T15 T11 T28 | T15 T250 T125 | T15 T11 T12 | T15 T250 T125 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T59 T250 T125 | T58 T59 T250 | T58 T250 T125 | T58 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T60 T250 T125 | T250 T125 T320 | T250 T125 T320 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T62 T250 T125 | T250 T125 T320 | T250 T125 T320 | T3 T250 T125 | T250 T125 T320 | T45 T78 T79 | T45 T78 T79 | T45 T11 T12 | T11 T12 T250 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T4 T25 T14 | T139 T66 T250 | T235 T45 T78 | T172 T250 T125 | T5 T321 T145 | T5 T321 T145 | T5 T321 T145 | T322 T323 T250 | T250 T125 T320 | T250 T125 T320 | T324 T250 T125 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320 | T250 T125 T320
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T3 T4 T5
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T3 T4 T5
101 1/1 assign max_value_o = max_tree[0];
Tests: T3 T4 T5
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);