| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| big_delay | 500 | 1 | T308 | 1 | T555 | 1 | T546 | 1 | ||||
| small_delay | 665 | 1 | T307 | 1 | T309 | 1 | T464 | 1 | ||||
| zero | 635 | 1 | T96 | 1 | T97 | 1 | T98 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |