Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.02	95.41	93.73	95.49		94.54	97.40	99.54

Total tests in report: 2925

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.91	40.91	49.66	49.66	49.53	49.53	22.67	22.67			64.22	64.22	59.28	59.28	0.13	0.13	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2328650227
48.48	7.56	53.94	4.29	58.57	9.05	22.87	0.19			70.43	6.21	84.02	24.74	1.03	0.90	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3410215846
54.02	5.54	65.62	11.68	66.50	7.93	25.91	3.04			81.05	10.62	84.02	0.00	1.03	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.1993677803
58.38	4.36	74.89	9.28	68.50	2.00	32.98	7.07			81.35	0.31	84.02	0.00	8.52	7.48	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3360355390
62.57	4.19	74.89	0.00	68.50	0.01	32.98	0.00			81.35	0.00	84.02	0.00	33.64	25.12	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.362604462
65.70	3.14	74.89	0.00	68.50	0.00	51.53	18.55			81.35	0.00	84.19	0.17	33.74	0.11	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1064877359
68.74	3.04	79.71	4.82	72.25	3.75	55.01	3.48			83.06	1.70	88.66	4.47	33.74	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3796877113
71.16	2.42	79.71	0.00	72.59	0.34	55.01	0.00			83.08	0.02	88.66	0.00	47.89	14.15	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3526256502
73.56	2.41	81.25	1.54	75.33	2.74	60.41	5.40			84.93	1.86	89.00	0.34	50.44	2.55	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.2473819699
75.50	1.94	81.25	0.00	75.33	0.00	60.41	0.00			84.93	0.00	89.00	0.00	62.07	11.63	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3154199184
77.20	1.70	83.36	2.10	76.55	1.22	63.65	3.24			86.14	1.21	91.41	2.41	62.07	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.2188877176
78.70	1.50	83.36	0.01	76.92	0.37	64.14	0.50			86.15	0.01	91.41	0.00	70.20	8.13	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2760701594
80.09	1.39	83.48	0.12	77.02	0.11	71.94	7.80			86.32	0.17	91.58	0.17	70.20	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3059653385
81.48	1.39	83.48	0.00	77.02	0.00	71.94	0.00			86.32	0.00	91.58	0.00	78.53	8.33	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3225328586
82.70	1.22	85.32	1.84	78.08	1.06	74.88	2.94			87.12	0.80	92.27	0.69	78.53	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.4278117806
83.74	1.04	87.24	1.92	79.64	1.56	75.58	0.70			89.17	2.05	92.27	0.00	78.53	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.4215068609
84.76	1.02	87.24	0.00	79.64	0.00	81.69	6.10			89.17	0.00	92.27	0.00	78.53	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.4260852875
85.73	0.98	87.35	0.11	81.77	2.13	81.69	0.00			89.26	0.09	92.27	0.00	82.07	3.54	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2741402623
86.63	0.89	88.50	1.15	82.49	0.71	83.97	2.29			90.30	1.04	92.44	0.17	82.07	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2061482490
87.48	0.86	89.24	0.74	82.79	0.30	83.99	0.01			90.60	0.30	96.22	3.78	82.07	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2829157128
88.32	0.83	89.24	0.00	82.79	0.00	83.99	0.00			90.60	0.00	96.22	0.00	87.08	5.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.4059779901
88.84	0.52	89.24	0.00	83.19	0.40	83.99	0.00			90.65	0.05	96.22	0.00	89.75	2.68	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.316019515
89.35	0.51	90.13	0.89	84.06	0.87	84.31	0.32			91.64	1.00	96.22	0.00	89.75	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.35008612
89.82	0.47	90.22	0.08	86.25	2.19	84.50	0.19			91.70	0.06	96.22	0.00	90.06	0.31	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2633369915
90.20	0.38	91.02	0.81	86.59	0.34	85.20	0.69			91.89	0.19	96.39	0.17	90.11	0.05	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1714408562
90.56	0.36	91.02	0.00	86.61	0.02	85.28	0.09			91.90	0.01	96.39	0.00	92.15	2.04	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2221577054
90.91	0.35	91.73	0.71	87.07	0.46	85.85	0.57			92.28	0.37	96.39	0.00	92.15	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.3083445017
91.26	0.35	91.73	0.00	87.07	0.00	85.85	0.00			92.28	0.00	96.39	0.00	94.24	2.09	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2315697579
91.59	0.33	92.54	0.81	87.45	0.38	86.27	0.41			92.64	0.37	96.39	0.00	94.24	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.4242298256
91.92	0.33	92.55	0.01	87.45	0.01	88.22	1.95			92.64	0.00	96.39	0.00	94.24	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1569104829
92.23	0.32	93.11	0.56	87.94	0.49	88.57	0.35			93.15	0.51	96.39	0.00	94.24	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.697982784
92.54	0.30	93.11	0.00	87.94	0.00	90.37	1.80			93.15	0.00	96.39	0.00	94.24	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2822571353
92.83	0.29	93.50	0.39	89.27	1.32	90.39	0.02			93.18	0.02	96.39	0.00	94.24	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3883873409
93.04	0.21	93.50	0.00	89.27	0.01	90.39	0.00			93.18	0.00	96.39	0.00	95.51	1.27	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3903868221
93.22	0.18	93.55	0.06	89.28	0.01	91.41	1.02			93.18	0.01	96.39	0.00	95.51	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2104423841
93.38	0.16	93.57	0.01	89.30	0.03	92.28	0.87			93.21	0.02	96.39	0.00	95.51	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3982141078
93.53	0.15	93.57	0.00	89.31	0.01	92.28	0.00			93.21	0.00	96.39	0.00	96.43	0.92	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.673488528
93.68	0.15	93.77	0.21	89.63	0.32	92.63	0.35			93.21	0.00	96.39	0.00	96.43	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3520474020
93.82	0.15	93.81	0.03	90.02	0.38	92.65	0.02			93.65	0.44	96.39	0.00	96.43	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3806926868
93.96	0.14	93.81	0.00	90.85	0.84	92.65	0.00			93.65	0.00	96.39	0.00	96.43	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.3912846086
94.08	0.12	93.81	0.00	90.86	0.01	92.65	0.00			93.65	0.00	96.39	0.00	97.13	0.70	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2663238559
94.18	0.10	93.81	0.00	90.86	0.00	93.25	0.60			93.65	0.00	96.39	0.00	97.13	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3180555376
94.27	0.09	93.81	0.00	91.06	0.19	93.25	0.00			93.66	0.02	96.39	0.00	97.45	0.32	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1922578030
94.35	0.08	93.91	0.10	91.27	0.22	93.37	0.12			93.73	0.06	96.39	0.00	97.45	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.3814425141
94.44	0.08	94.05	0.14	91.38	0.11	93.50	0.13			93.85	0.12	96.39	0.00	97.45	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1785707789
94.51	0.07	94.05	0.00	91.58	0.20	93.50	0.00			94.08	0.23	96.39	0.00	97.45	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4198707868
94.57	0.07	94.05	0.00	91.61	0.02	93.50	0.00			94.08	0.00	96.39	0.00	97.83	0.38	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.271784240
94.64	0.06	94.08	0.03	91.63	0.02	93.62	0.12			94.11	0.03	96.56	0.17	97.83	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3346563770
94.70	0.06	94.09	0.01	91.68	0.05	93.73	0.12			94.13	0.02	96.74	0.17	97.83	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1628520521
94.76	0.06	94.20	0.11	91.73	0.04	93.91	0.18			94.13	0.01	96.74	0.00	97.83	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.3405459205
94.81	0.05	94.20	0.00	91.73	0.00	94.24	0.33			94.13	0.00	96.74	0.00	97.83	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.859632199
94.86	0.05	94.20	0.00	92.03	0.31	94.24	0.00			94.13	0.00	96.74	0.00	97.83	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2753080563
94.90	0.04	94.20	0.00	92.09	0.06	94.24	0.00			94.15	0.02	96.74	0.00	98.00	0.18	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.522826337
94.94	0.04	94.24	0.03	92.11	0.02	94.24	0.01			94.16	0.01	96.91	0.17	98.00	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.3958283690
94.98	0.04	94.25	0.01	92.13	0.01	94.24	0.00			94.18	0.02	97.08	0.17	98.01	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137872765
95.02	0.04	94.25	0.01	92.14	0.01	94.25	0.01			94.19	0.01	97.25	0.17	98.03	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.746600883
95.05	0.04	94.26	0.01	92.15	0.01	94.25	0.00			94.20	0.01	97.42	0.17	98.04	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.3162115064
95.09	0.03	94.35	0.09	92.15	0.00	94.36	0.11			94.21	0.01	97.42	0.00	98.04	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2862714310
95.12	0.03	94.35	0.00	92.18	0.03	94.36	0.00			94.22	0.02	97.42	0.00	98.18	0.14	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1955267920
95.15	0.03	94.38	0.03	92.22	0.04	94.43	0.07			94.26	0.04	97.42	0.00	98.18	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2084682112
95.18	0.03	94.38	0.00	92.22	0.00	94.61	0.18			94.26	0.00	97.42	0.00	98.18	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1181887528
95.21	0.03	94.42	0.03	92.35	0.13	94.61	0.00			94.26	0.00	97.42	0.00	98.18	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.4185372178
95.23	0.02	94.48	0.07	92.40	0.05	94.61	0.00			94.30	0.03	97.42	0.00	98.18	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.1657629254
95.25	0.02	94.48	0.00	92.54	0.14	94.61	0.00			94.30	0.00	97.42	0.00	98.18	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3594383750
95.28	0.02	94.48	0.00	92.59	0.05	94.61	0.00			94.30	0.00	97.42	0.00	98.26	0.08	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4246490398
95.30	0.02	94.55	0.07	92.64	0.05	94.62	0.01			94.31	0.02	97.42	0.00	98.26	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.627738562
95.32	0.02	94.58	0.04	92.65	0.01	94.67	0.06			94.33	0.02	97.42	0.00	98.26	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1689009526
95.34	0.02	94.59	0.01	92.70	0.05	94.69	0.02			94.38	0.05	97.42	0.00	98.26	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3484787015
95.36	0.02	94.59	0.00	92.81	0.11	94.69	0.00			94.38	0.00	97.42	0.00	98.27	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2439798266
95.38	0.02	94.59	0.00	92.81	0.00	94.69	0.00			94.38	0.00	97.42	0.00	98.39	0.12	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2213405897
95.40	0.02	94.59	0.01	92.83	0.02	94.76	0.07			94.38	0.00	97.42	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1519037384
95.41	0.02	94.64	0.05	92.85	0.01	94.77	0.01			94.41	0.03	97.42	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.3173974919
95.43	0.02	94.69	0.05	92.86	0.01	94.77	0.01			94.44	0.03	97.42	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3085755318
95.45	0.02	94.69	0.00	92.96	0.10	94.77	0.00			94.44	0.00	97.42	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.556453027
95.46	0.02	94.70	0.01	93.02	0.06	94.77	0.00			94.46	0.02	97.42	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.3437707886
95.47	0.01	94.70	0.00	93.02	0.00	94.77	0.00			94.46	0.00	97.42	0.00	98.47	0.08	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1746191025
95.49	0.01	94.70	0.00	93.03	0.01	94.84	0.07			94.46	0.00	97.42	0.00	98.47	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.722834522
95.50	0.01	94.70	0.00	93.03	0.00	94.92	0.07			94.46	0.00	97.42	0.00	98.47	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.3892966340
95.51	0.01	94.72	0.02	93.03	0.01	94.97	0.05			94.46	0.00	97.42	0.00	98.47	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.322031160
95.52	0.01	94.72	0.00	93.10	0.07	94.97	0.00			94.46	0.00	97.42	0.00	98.47	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1116979277
95.54	0.01	94.72	0.00	93.10	0.00	95.04	0.07			94.46	0.00	97.42	0.00	98.47	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.2214115230
95.55	0.01	94.72	0.00	93.10	0.00	95.04	0.00			94.46	0.00	97.42	0.00	98.53	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3455010078
95.55	0.01	94.75	0.02	93.11	0.01	95.04	0.01			94.47	0.02	97.42	0.00	98.53	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.1239893744
95.56	0.01	94.75	0.00	93.16	0.05	95.04	0.00			94.47	0.00	97.42	0.00	98.53	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.786872123
95.57	0.01	94.75	0.00	93.18	0.02	95.04	0.00			94.47	0.00	97.42	0.00	98.57	0.04	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.881642627
95.58	0.01	94.76	0.02	93.18	0.01	95.05	0.01			94.49	0.02	97.42	0.00	98.57	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2481819676
95.59	0.01	94.76	0.00	93.21	0.02	95.05	0.00			94.49	0.00	97.42	0.00	98.59	0.02	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.4270507977
95.60	0.01	94.76	0.00	93.24	0.03	95.05	0.00			94.51	0.02	97.42	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.231458916
95.60	0.01	94.76	0.00	93.24	0.00	95.10	0.04			94.51	0.00	97.42	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.1552975516
95.61	0.01	94.76	0.00	93.24	0.00	95.14	0.04			94.51	0.00	97.42	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3017612370
95.62	0.01	94.76	0.00	93.28	0.04	95.14	0.00			94.51	0.00	97.42	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1097258341
95.62	0.01	94.76	0.00	93.32	0.04	95.14	0.00			94.51	0.00	97.42	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.1463154239
95.63	0.01	94.76	0.00	93.33	0.01	95.16	0.02			94.52	0.01	97.42	0.00	98.60	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3292943170
95.64	0.01	94.76	0.00	93.36	0.04	95.16	0.00			94.52	0.00	97.42	0.00	98.60	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2276903571
95.64	0.01	94.76	0.00	93.36	0.00	95.16	0.00			94.52	0.00	97.42	0.00	98.64	0.04	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.2218120491
95.65	0.01	94.76	0.00	93.36	0.00	95.19	0.03			94.52	0.00	97.42	0.00	98.64	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.3158586839
95.65	0.01	94.77	0.01	93.37	0.01	95.21	0.02			94.52	0.00	97.42	0.00	98.64	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.61179958
95.66	0.01	94.77	0.00	93.39	0.01	95.21	0.00			94.53	0.02	97.42	0.00	98.64	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.917047111
95.66	0.01	94.77	0.00	93.41	0.02	95.22	0.01			94.53	0.00	97.42	0.00	98.64	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.1964906139
95.67	0.01	94.77	0.00	93.44	0.03	95.22	0.00			94.53	0.00	97.42	0.00	98.64	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.3590658668
95.67	0.01	94.77	0.00	93.44	0.00	95.23	0.02			94.53	0.00	97.42	0.00	98.65	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.1291463310
95.68	0.01	94.77	0.00	93.44	0.00	95.26	0.03			94.53	0.00	97.42	0.00	98.65	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1858304053
95.68	0.01	94.77	0.00	93.44	0.01	95.26	0.00			94.53	0.00	97.42	0.00	98.67	0.02	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2144107812
95.69	0.01	94.77	0.01	93.45	0.01	95.27	0.01			94.53	0.00	97.42	0.00	98.67	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2308914617
95.69	0.01	94.77	0.01	93.46	0.01	95.28	0.01			94.53	0.00	97.42	0.00	98.67	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.3572016030
95.69	0.01	94.77	0.00	93.46	0.00	95.28	0.00			94.53	0.00	97.42	0.00	98.70	0.02	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2463327512
95.70	0.01	94.77	0.00	93.46	0.00	95.28	0.00			94.53	0.00	97.42	0.00	98.72	0.02	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2235984657
95.70	0.01	94.77	0.00	93.46	0.00	95.31	0.02			94.53	0.00	97.42	0.00	98.72	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.2292940579
95.71	0.01	94.78	0.01	93.47	0.01	95.31	0.01			94.53	0.00	97.42	0.00	98.72	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.2808151272
95.71	0.01	94.78	0.00	93.49	0.02	95.31	0.01			94.53	0.00	97.42	0.00	98.72	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.2992054062
95.71	0.01	94.78	0.00	93.50	0.01	95.31	0.00			94.53	0.00	97.42	0.00	98.73	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1964502085
95.72	0.01	94.78	0.00	93.52	0.02	95.31	0.00			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.1989057523
95.72	0.01	94.78	0.00	93.53	0.02	95.31	0.00			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.211723894
95.72	0.01	94.78	0.00	93.55	0.02	95.31	0.00			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.3265465860
95.72	0.01	94.78	0.00	93.55	0.00	95.33	0.02			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.146751954
95.73	0.01	94.79	0.01	93.55	0.00	95.33	0.01			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.2460151531
95.73	0.01	94.79	0.00	93.56	0.01	95.34	0.01			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.2017713468
95.73	0.01	94.79	0.00	93.57	0.01	95.34	0.00			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.1184405651
95.73	0.01	94.79	0.00	93.58	0.01	95.34	0.00			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3535202918
95.74	0.01	94.79	0.00	93.58	0.00	95.36	0.01			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.701455061
95.74	0.01	94.79	0.00	93.58	0.00	95.37	0.01			94.53	0.00	97.42	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.944842574
95.74	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.74	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.697304886
95.74	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.75	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3819502191
95.74	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.77	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.17329104
95.75	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.78	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1379191720
95.75	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.79	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.3541844388
95.75	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.80	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3845750450
95.75	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.81	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.59286699
95.75	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.83	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.1581239652
95.76	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.84	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.1684591915
95.76	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.85	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909588533
95.76	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.86	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.3465525696
95.76	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.87	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2277402590
95.76	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.88	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3660479761
95.77	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.90	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.3421242471
95.77	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.91	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.768018501
95.77	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.92	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.18404547
95.77	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.93	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.254637920
95.77	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.94	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.160324171
95.78	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.95	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1482413288
95.78	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.97	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.2014244340
95.78	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.98	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1829610927
95.78	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	98.99	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.3780075033
95.78	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.00	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3336172109
95.79	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.01	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.779925250
95.79	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.02	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.127971002
95.79	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.04	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455462176
95.79	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.05	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1655259804
95.79	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.06	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.2829138405
95.80	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.07	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3779235341
95.80	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.08	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.1063500475
95.80	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.10	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.147242104
95.80	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.11	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.1415171829
95.80	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.12	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.4052382618
95.80	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.13	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.1549737210
95.81	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.14	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4177130920
95.81	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.15	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2205070145
95.81	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.17	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.4052389872
95.81	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.18	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3716709741
95.81	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.19	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3017403895
95.82	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.20	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.2631069371
95.82	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.21	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309997317
95.82	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.22	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3319114355
95.82	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.24	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.547747212
95.82	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.25	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.4089045780
95.83	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.26	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.437440869
95.83	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.27	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2103571422
95.83	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.28	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1391725901
95.83	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.30	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1843449143
95.83	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.31	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.2375357949
95.84	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.32	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1327929118
95.84	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.33	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.72244244
95.84	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.34	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.60917355
95.84	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.35	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.3059243173
95.84	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.37	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3411578574
95.85	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.38	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4260075988
95.85	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.39	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3510197962
95.85	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.40	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3590957260
95.85	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.41	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.1774626146
95.85	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.42	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2672152933
95.86	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.44	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.2315381631
95.86	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.45	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.2568982711
95.86	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.46	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.3842727071
95.86	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.47	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2757278118
95.86	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.48	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.701766749
95.87	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.49	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.1955136396
95.87	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.51	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3797558499
95.87	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.52	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.3224218568
95.87	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.53	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.1692738402
95.87	0.01	94.79	0.00	93.58	0.00	95.37	0.00			94.53	0.00	97.42	0.00	99.54	0.01	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.1356806993
95.88	0.01	94.79	0.00	93.58	0.00	95.38	0.01			94.53	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3928694370
95.88	0.01	94.79	0.00	93.58	0.00	95.40	0.01			94.53	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2538655894
95.88	0.01	94.79	0.00	93.59	0.01	95.40	0.00			94.54	0.01	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2888054789
95.88	0.01	94.79	0.00	93.60	0.01	95.40	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2652971894
95.88	0.01	94.79	0.00	93.61	0.01	95.40	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2595249476
95.88	0.01	94.79	0.00	93.62	0.01	95.40	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2883003305
95.89	0.01	94.79	0.00	93.63	0.01	95.40	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.3519549448
95.89	0.01	94.79	0.01	93.63	0.00	95.40	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1864661664
95.89	0.01	94.80	0.01	93.63	0.00	95.41	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.1986622484
95.89	0.01	94.80	0.00	93.63	0.00	95.42	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2171812643
95.89	0.01	94.80	0.00	93.63	0.00	95.43	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2746417529
95.89	0.01	94.80	0.00	93.63	0.01	95.43	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.1759397972
95.90	0.01	94.80	0.00	93.64	0.01	95.44	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.2219967164
95.90	0.01	94.80	0.00	93.64	0.01	95.44	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3119612532
95.90	0.01	94.80	0.00	93.65	0.01	95.44	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1677924875
95.90	0.01	94.80	0.00	93.66	0.01	95.44	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2501550219
95.90	0.01	94.80	0.00	93.66	0.01	95.44	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4187720283
95.90	0.01	94.80	0.00	93.67	0.01	95.44	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.1178447222
95.90	0.01	94.80	0.00	93.67	0.00	95.44	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.893645002
95.90	0.01	94.80	0.00	93.67	0.00	95.45	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.201540177
95.90	0.01	94.80	0.01	93.67	0.00	95.45	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.2545301857
95.91	0.01	94.80	0.00	93.67	0.00	95.46	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.1738623069
95.91	0.01	94.80	0.00	93.67	0.00	95.46	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.2327364004
95.91	0.01	94.80	0.00	93.67	0.00	95.47	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3707678017
95.91	0.01	94.80	0.00	93.67	0.00	95.47	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.417886709
95.91	0.01	94.80	0.00	93.67	0.00	95.48	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.4207290329
95.91	0.01	94.80	0.00	93.68	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2856974321
95.91	0.01	94.80	0.00	93.68	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.807501242
95.91	0.01	94.80	0.00	93.68	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.2146421336
95.91	0.01	94.80	0.00	93.69	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1979632356
95.91	0.01	94.80	0.00	93.69	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.1584821263
95.91	0.01	94.80	0.00	93.69	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1768953991
95.91	0.01	94.80	0.00	93.70	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.642604115
95.91	0.01	94.80	0.00	93.70	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3621172139
95.91	0.01	94.80	0.00	93.70	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.1409371688
95.91	0.01	94.80	0.00	93.71	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3144181690
95.92	0.01	94.80	0.00	93.71	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.1783477270
95.92	0.01	94.80	0.00	93.71	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.29688179
95.92	0.01	94.80	0.00	93.72	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.1788743127
95.92	0.01	94.80	0.00	93.72	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.795209027
95.92	0.01	94.80	0.00	93.72	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2120323894
95.92	0.01	94.80	0.00	93.73	0.01	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.3896383993
95.92	0.01	94.80	0.00	93.73	0.00	95.48	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.747321561
95.92	0.01	94.80	0.01	93.73	0.00	95.48	0.00			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.336128244
95.92	0.01	94.80	0.00	93.73	0.00	95.48	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2027710623
95.92	0.01	94.80	0.00	93.73	0.00	95.49	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.1355065858
95.92	0.01	94.80	0.00	93.73	0.00	95.49	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1220187654
95.92	0.01	94.80	0.00	93.73	0.00	95.49	0.01			94.54	0.00	97.42	0.00	99.54	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3986395061

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.172643317
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1672409385
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1773534741
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1389145539
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.222860954
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3556485000
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3801929827
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.1286891524
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.2681253316
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.766408528
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.240360964
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3649575192
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.705633775
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2545221185
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.447068115
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2769884004
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.521723445
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2245789763
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.687618359
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.1500172556
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2797093756
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.1719066387
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1044391473
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3192775804
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.759828536
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2325271433
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.4198630524
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.747949473
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2914699978
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.2045317665
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.282427207
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3010420593
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3322676766
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.832129663
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3540017163
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1744344337
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1185694270
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2568765052
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.4213242154
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.634231603
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.943850691
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3913857694
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2939727281
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.107034254
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.1311489781
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.3141494575
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1864312456
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3125185281
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1218233952
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.3342810581
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2207204205
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.985780514
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2958861984
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3358614452
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1191531788
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/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.1789101718
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/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2700285038
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2750904972
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3221041522
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.278624896
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.701375818
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.745330837
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.2634760030
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/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.387785118
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/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.667196710
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.551533424
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.1039620291
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2722710913
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.2888665079
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1299621421
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/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.103073860
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2852398407
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/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984179345
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.1050639046
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830221852
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.964766053
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3770420707
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/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.681378087
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.3601962661
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1459408739
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.272985058
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.4082065797
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.406684781
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.2652799055
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1545269501
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.332777494
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.387695548
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1862086939
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2022263863
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1800784369
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.206070532
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2770187304

Total test records in report: 2925

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2143116470	Sep 25 01:58:12 AM UTC 24	Sep 25 01:59:50 AM UTC 24	2496730570 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2328650227	Sep 25 01:58:13 AM UTC 24	Sep 25 02:01:53 AM UTC 24	2266405195 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.705388484	Sep 25 02:00:15 AM UTC 24	Sep 25 02:03:21 AM UTC 24	2228327202 ps
T4	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.627738562	Sep 25 02:00:33 AM UTC 24	Sep 25 02:03:31 AM UTC 24	2792662348 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2923273371	Sep 25 01:59:52 AM UTC 24	Sep 25 02:04:18 AM UTC 24	2971245664 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2084682112	Sep 25 01:59:52 AM UTC 24	Sep 25 02:04:40 AM UTC 24	3277389762 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3484787015	Sep 25 02:00:32 AM UTC 24	Sep 25 02:05:11 AM UTC 24	3373138006 ps
T107	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.3999821760	Sep 25 02:02:09 AM UTC 24	Sep 25 02:05:15 AM UTC 24	2719207114 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.2188877176	Sep 25 02:01:10 AM UTC 24	Sep 25 02:06:09 AM UTC 24	3728870376 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.3405459205	Sep 25 02:02:16 AM UTC 24	Sep 25 02:06:10 AM UTC 24	2875064408 ps
T124	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.2417776440	Sep 25 02:01:00 AM UTC 24	Sep 25 02:06:17 AM UTC 24	2826041778 ps
T125	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.572390177	Sep 25 02:02:13 AM UTC 24	Sep 25 02:06:17 AM UTC 24	2753612636 ps
T31	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.2153481020	Sep 25 02:01:58 AM UTC 24	Sep 25 02:06:35 AM UTC 24	3079981880 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.722834522	Sep 25 02:01:20 AM UTC 24	Sep 25 02:06:42 AM UTC 24	2703890503 ps
T26	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.4079957411	Sep 25 01:58:05 AM UTC 24	Sep 25 02:07:07 AM UTC 24	4266215112 ps
T45	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2061482490	Sep 25 01:59:51 AM UTC 24	Sep 25 02:09:00 AM UTC 24	4807875864 ps
T146	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.4165066716	Sep 25 02:03:10 AM UTC 24	Sep 25 02:09:11 AM UTC 24	3854338596 ps
T27	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.3083445017	Sep 25 02:01:47 AM UTC 24	Sep 25 02:09:22 AM UTC 24	4043304834 ps
T39	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1064877359	Sep 25 02:01:57 AM UTC 24	Sep 25 02:09:42 AM UTC 24	5227918309 ps
T194	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.25775525	Sep 25 02:04:18 AM UTC 24	Sep 25 02:09:56 AM UTC 24	2903954468 ps
T235	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.1224098490	Sep 25 02:04:05 AM UTC 24	Sep 25 02:10:24 AM UTC 24	3067247760 ps
T36	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1854021884	Sep 25 02:08:27 AM UTC 24	Sep 25 02:10:42 AM UTC 24	2489053806 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.3916960991	Sep 25 02:00:32 AM UTC 24	Sep 25 02:10:49 AM UTC 24	4278840776 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.543645498	Sep 25 02:08:01 AM UTC 24	Sep 25 02:10:52 AM UTC 24	4095687135 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4187720283	Sep 25 02:00:33 AM UTC 24	Sep 25 02:11:03 AM UTC 24	4465596628 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.2808151272	Sep 25 02:03:04 AM UTC 24	Sep 25 02:11:07 AM UTC 24	3448867112 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3928694370	Sep 25 02:06:00 AM UTC 24	Sep 25 02:11:10 AM UTC 24	3287373292 ps
T30	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4029904095	Sep 25 02:08:00 AM UTC 24	Sep 25 02:11:11 AM UTC 24	2877109158 ps
T153	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4012984902	Sep 25 02:01:21 AM UTC 24	Sep 25 02:11:14 AM UTC 24	3694561619 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.1788743127	Sep 25 02:01:57 AM UTC 24	Sep 25 02:11:26 AM UTC 24	4193644397 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.995636361	Sep 25 02:08:21 AM UTC 24	Sep 25 02:11:35 AM UTC 24	2455162925 ps
T202	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2251351566	Sep 25 02:09:51 AM UTC 24	Sep 25 02:11:50 AM UTC 24	2643803172 ps
T134	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.61179958	Sep 25 02:01:21 AM UTC 24	Sep 25 02:12:07 AM UTC 24	4371056760 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.3137911314	Sep 25 02:01:53 AM UTC 24	Sep 25 02:12:17 AM UTC 24	4077765088 ps
T133	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.1964906139	Sep 25 02:02:15 AM UTC 24	Sep 25 02:12:29 AM UTC 24	4135804614 ps
T68	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2308914617	Sep 25 02:00:53 AM UTC 24	Sep 25 02:12:47 AM UTC 24	5060849420 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3180555376	Sep 25 02:08:03 AM UTC 24	Sep 25 02:12:48 AM UTC 24	4136476637 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.1024546318	Sep 25 02:01:22 AM UTC 24	Sep 25 02:12:52 AM UTC 24	4641784416 ps
T86	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.1291463310	Sep 25 02:01:23 AM UTC 24	Sep 25 02:13:19 AM UTC 24	5952836564 ps
T195	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3673862646	Sep 25 02:08:12 AM UTC 24	Sep 25 02:13:41 AM UTC 24	3513785023 ps
T208	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.4236772596	Sep 25 02:08:05 AM UTC 24	Sep 25 02:14:16 AM UTC 24	4824837274 ps
T87	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.860066687	Sep 25 02:02:28 AM UTC 24	Sep 25 02:14:22 AM UTC 24	6062759152 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3925589223	Sep 25 02:03:09 AM UTC 24	Sep 25 02:14:23 AM UTC 24	5782267271 ps
T337	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.868338110	Sep 25 02:10:29 AM UTC 24	Sep 25 02:14:29 AM UTC 24	3151925236 ps
T253	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2276903571	Sep 25 02:03:34 AM UTC 24	Sep 25 02:14:31 AM UTC 24	4267327460 ps
T198	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3982141078	Sep 25 02:06:00 AM UTC 24	Sep 25 02:14:52 AM UTC 24	5237096256 ps
T275	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1919167738	Sep 25 02:04:21 AM UTC 24	Sep 25 02:15:18 AM UTC 24	4851031944 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2652971894	Sep 25 02:03:29 AM UTC 24	Sep 25 02:16:11 AM UTC 24	4279478208 ps
T212	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.402938595	Sep 25 02:10:16 AM UTC 24	Sep 25 02:17:44 AM UTC 24	3626630620 ps
T269	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3119867538	Sep 25 02:14:33 AM UTC 24	Sep 25 02:18:30 AM UTC 24	2794692008 ps
T213	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.75047454	Sep 25 02:13:28 AM UTC 24	Sep 25 02:18:32 AM UTC 24	4622132912 ps
T130	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.1585915281	Sep 25 02:15:23 AM UTC 24	Sep 25 02:19:16 AM UTC 24	3151931476 ps
T170	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2538655894	Sep 25 02:12:42 AM UTC 24	Sep 25 02:19:41 AM UTC 24	6108514056 ps
T154	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3518304674	Sep 25 02:01:54 AM UTC 24	Sep 25 02:20:07 AM UTC 24	6166776935 ps
T661	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.67932080	Sep 25 02:14:36 AM UTC 24	Sep 25 02:20:15 AM UTC 24	3807611925 ps
T270	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.3823720707	Sep 25 02:15:16 AM UTC 24	Sep 25 02:20:53 AM UTC 24	3869538576 ps
T248	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3346563770	Sep 25 02:12:41 AM UTC 24	Sep 25 02:21:00 AM UTC 24	5154789216 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1519037384	Sep 25 02:01:55 AM UTC 24	Sep 25 02:21:08 AM UTC 24	8979854881 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1366367838	Sep 25 02:16:17 AM UTC 24	Sep 25 02:21:33 AM UTC 24	2661623857 ps
T320	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.3845940202	Sep 25 02:03:05 AM UTC 24	Sep 25 02:22:06 AM UTC 24	5168625208 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.925585527	Sep 25 02:16:10 AM UTC 24	Sep 25 02:22:13 AM UTC 24	3450228960 ps
T161	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3038911845	Sep 25 02:15:32 AM UTC 24	Sep 25 02:22:19 AM UTC 24	6395401038 ps
T155	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2851333783	Sep 25 02:03:36 AM UTC 24	Sep 25 02:22:22 AM UTC 24	5293638513 ps
T321	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3706256669	Sep 25 02:18:17 AM UTC 24	Sep 25 02:22:34 AM UTC 24	2878968180 ps
T216	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.495034402	Sep 25 02:05:16 AM UTC 24	Sep 25 02:23:08 AM UTC 24	6462727760 ps
T322	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.1282899775	Sep 25 02:19:19 AM UTC 24	Sep 25 02:23:15 AM UTC 24	2518450412 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.322031160	Sep 25 02:14:36 AM UTC 24	Sep 25 02:23:34 AM UTC 24	5630085134 ps
T271	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3229995626	Sep 25 02:16:18 AM UTC 24	Sep 25 02:24:18 AM UTC 24	4620169090 ps
T162	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3707678017	Sep 25 02:15:18 AM UTC 24	Sep 25 02:24:27 AM UTC 24	6978675416 ps
T416	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.2078443856	Sep 25 02:19:26 AM UTC 24	Sep 25 02:25:00 AM UTC 24	2990638622 ps
T80	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.2473819699	Sep 25 02:19:28 AM UTC 24	Sep 25 02:25:01 AM UTC 24	2256735784 ps
T382	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.1271629859	Sep 25 02:19:27 AM UTC 24	Sep 25 02:25:10 AM UTC 24	3154046576 ps
T203	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3059653385	Sep 25 02:08:22 AM UTC 24	Sep 25 02:26:08 AM UTC 24	9589995553 ps
T264	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.904818253	Sep 25 02:16:05 AM UTC 24	Sep 25 02:26:08 AM UTC 24	4569332506 ps
T224	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.1355065858	Sep 25 02:16:15 AM UTC 24	Sep 25 02:26:15 AM UTC 24	3219277600 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1785707789	Sep 25 02:15:19 AM UTC 24	Sep 25 02:26:15 AM UTC 24	4914593997 ps
T206	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1453215607	Sep 25 02:05:10 AM UTC 24	Sep 25 02:26:21 AM UTC 24	8178313840 ps
T142	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.163583237	Sep 25 02:13:51 AM UTC 24	Sep 25 02:26:33 AM UTC 24	8494071406 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.1907099633	Sep 25 02:03:05 AM UTC 24	Sep 25 02:26:43 AM UTC 24	10008966400 ps
T104	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.721640937	Sep 25 02:22:08 AM UTC 24	Sep 25 02:27:03 AM UTC 24	2594623969 ps
T166	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.2038949819	Sep 25 02:23:25 AM UTC 24	Sep 25 02:27:18 AM UTC 24	2695634880 ps
T265	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.17329104	Sep 25 02:20:53 AM UTC 24	Sep 25 02:27:28 AM UTC 24	3956094328 ps
T143	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2238944309	Sep 25 02:14:16 AM UTC 24	Sep 25 02:27:39 AM UTC 24	7973599249 ps
T207	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.227225189	Sep 25 02:05:17 AM UTC 24	Sep 25 02:27:41 AM UTC 24	7172693956 ps
T266	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.840892948	Sep 25 02:19:52 AM UTC 24	Sep 25 02:28:13 AM UTC 24	3798544904 ps
T885	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.3797488497	Sep 25 02:23:18 AM UTC 24	Sep 25 02:28:33 AM UTC 24	3034257500 ps
T625	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.526982172	Sep 25 02:25:04 AM UTC 24	Sep 25 02:29:04 AM UTC 24	2087925144 ps
T658	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1689009526	Sep 25 02:12:42 AM UTC 24	Sep 25 02:29:25 AM UTC 24	6939930424 ps
T279	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.2813066418	Sep 25 02:19:51 AM UTC 24	Sep 25 02:29:36 AM UTC 24	5383565560 ps
T145	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2171812643	Sep 25 02:15:59 AM UTC 24	Sep 25 02:29:46 AM UTC 24	20105638322 ps
T135	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.4175689318	Sep 25 02:02:15 AM UTC 24	Sep 25 02:30:32 AM UTC 24	7990903280 ps
T167	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3431520344	Sep 25 02:25:54 AM UTC 24	Sep 25 02:31:03 AM UTC 24	2924762296 ps
T461	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.29688179	Sep 25 02:16:46 AM UTC 24	Sep 25 02:31:42 AM UTC 24	4961704598 ps
T168	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.4284760536	Sep 25 02:16:22 AM UTC 24	Sep 25 02:32:24 AM UTC 24	5354735020 ps
T350	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1218944265	Sep 25 02:14:13 AM UTC 24	Sep 25 02:32:33 AM UTC 24	10600940709 ps
T163	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2027710623	Sep 25 02:23:24 AM UTC 24	Sep 25 02:32:53 AM UTC 24	3315380560 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.944842574	Sep 25 02:01:43 AM UTC 24	Sep 25 02:32:54 AM UTC 24	7728022560 ps
T304	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.785249105	Sep 25 02:16:18 AM UTC 24	Sep 25 02:32:55 AM UTC 24	5746989478 ps
T659	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.893645002	Sep 25 02:27:41 AM UTC 24	Sep 25 02:32:57 AM UTC 24	2768016280 ps
T228	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2793607412	Sep 25 02:25:05 AM UTC 24	Sep 25 02:33:42 AM UTC 24	4578305954 ps
T660	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.38943959	Sep 25 02:28:28 AM UTC 24	Sep 25 02:34:00 AM UTC 24	3318778300 ps
T254	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.2483039280	Sep 25 02:27:55 AM UTC 24	Sep 25 02:34:08 AM UTC 24	2446169172 ps
T422	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.836863239	Sep 25 02:30:07 AM UTC 24	Sep 25 02:34:19 AM UTC 24	2557900520 ps
T458	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.1945001571	Sep 25 02:29:15 AM UTC 24	Sep 25 02:34:20 AM UTC 24	2905589320 ps
T886	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.884404189	Sep 25 02:15:59 AM UTC 24	Sep 25 02:34:39 AM UTC 24	9412030392 ps
T459	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.1078692167	Sep 25 02:29:18 AM UTC 24	Sep 25 02:34:51 AM UTC 24	2825152560 ps
T199	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.1783477270	Sep 25 02:10:33 AM UTC 24	Sep 25 02:35:15 AM UTC 24	12455347158 ps
T887	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.4283148494	Sep 25 02:30:20 AM UTC 24	Sep 25 02:35:20 AM UTC 24	2199024260 ps
T164	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.2974201094	Sep 25 02:23:26 AM UTC 24	Sep 25 02:35:37 AM UTC 24	3290482492 ps
T255	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.1590276166	Sep 25 02:29:08 AM UTC 24	Sep 25 02:35:41 AM UTC 24	3008941512 ps
T888	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2467306530	Sep 25 02:29:38 AM UTC 24	Sep 25 02:35:52 AM UTC 24	3641123817 ps
T165	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1181887528	Sep 25 02:23:52 AM UTC 24	Sep 25 02:36:38 AM UTC 24	7042270640 ps
T246	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2660815493	Sep 25 02:12:49 AM UTC 24	Sep 25 02:36:59 AM UTC 24	11811282187 ps
T249	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.2460151531	Sep 25 02:35:27 AM UTC 24	Sep 25 02:39:25 AM UTC 24	2894575960 ps
T186	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.1058581309	Sep 25 02:33:57 AM UTC 24	Sep 25 02:39:31 AM UTC 24	2716454948 ps
T889	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.989552588	Sep 25 02:13:28 AM UTC 24	Sep 25 02:39:40 AM UTC 24	14574558138 ps
T325	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1499339284	Sep 25 02:30:20 AM UTC 24	Sep 25 02:40:59 AM UTC 24	9413914177 ps
T214	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.368090426	Sep 25 02:03:32 AM UTC 24	Sep 25 02:41:22 AM UTC 24	23047611027 ps
T171	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3520474020	Sep 25 02:33:56 AM UTC 24	Sep 25 02:41:48 AM UTC 24	5477227600 ps
T156	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1628520521	Sep 25 02:31:38 AM UTC 24	Sep 25 02:41:54 AM UTC 24	5332865131 ps
T305	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1569104829	Sep 25 02:23:18 AM UTC 24	Sep 25 02:41:58 AM UTC 24	4162326076 ps
T890	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.928710989	Sep 25 02:35:58 AM UTC 24	Sep 25 02:42:17 AM UTC 24	5054944788 ps
T105	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1714408562	Sep 25 02:21:51 AM UTC 24	Sep 25 02:43:47 AM UTC 24	10247362472 ps
T657	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.382497904	Sep 25 02:20:15 AM UTC 24	Sep 25 02:43:55 AM UTC 24	8109671006 ps
T891	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3678698885	Sep 25 02:35:59 AM UTC 24	Sep 25 02:44:06 AM UTC 24	4162889464 ps
T892	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.4288350920	Sep 25 02:36:32 AM UTC 24	Sep 25 02:45:10 AM UTC 24	6002166318 ps
T217	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.110288016	Sep 25 02:31:08 AM UTC 24	Sep 25 02:45:18 AM UTC 24	5657048072 ps
T245	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3359814742	Sep 25 02:21:52 AM UTC 24	Sep 25 02:46:09 AM UTC 24	7162558638 ps
T893	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2877633911	Sep 25 02:35:30 AM UTC 24	Sep 25 02:46:19 AM UTC 24	4688191804 ps
T131	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.697982784	Sep 25 02:35:31 AM UTC 24	Sep 25 02:46:36 AM UTC 24	4487531730 ps
T894	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.4021901641	Sep 25 02:42:33 AM UTC 24	Sep 25 02:47:14 AM UTC 24	3103825496 ps
T624	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2698681148	Sep 25 02:33:10 AM UTC 24	Sep 25 02:47:33 AM UTC 24	8645892408 ps
T252	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.4215068609	Sep 25 02:35:22 AM UTC 24	Sep 25 02:47:37 AM UTC 24	4562349404 ps
T178	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.3173974919	Sep 25 02:33:57 AM UTC 24	Sep 25 02:48:00 AM UTC 24	5972748820 ps
T220	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.417886709	Sep 25 02:32:16 AM UTC 24	Sep 25 02:48:51 AM UTC 24	7725014275 ps
T158	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1858304053	Sep 25 02:37:32 AM UTC 24	Sep 25 02:49:15 AM UTC 24	4486744628 ps
T159	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3756125575	Sep 25 02:37:12 AM UTC 24	Sep 25 02:49:21 AM UTC 24	4558886020 ps
T247	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2861641531	Sep 25 02:14:43 AM UTC 24	Sep 25 02:49:40 AM UTC 24	19858911622 ps
T160	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1461363770	Sep 25 02:36:32 AM UTC 24	Sep 25 02:49:59 AM UTC 24	4049974238 ps
T348	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2137287058	Sep 25 02:41:58 AM UTC 24	Sep 25 02:50:07 AM UTC 24	3155649060 ps
T219	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1446798761	Sep 25 02:33:10 AM UTC 24	Sep 25 02:50:15 AM UTC 24	7818182424 ps
T157	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3230370846	Sep 25 02:29:05 AM UTC 24	Sep 25 02:50:39 AM UTC 24	6358455813 ps
T298	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.2526863585	Sep 25 02:25:58 AM UTC 24	Sep 25 02:50:50 AM UTC 24	6598722560 ps
T349	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4215861853	Sep 25 02:40:22 AM UTC 24	Sep 25 02:51:02 AM UTC 24	4793989506 ps
T895	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.567646522	Sep 25 02:40:19 AM UTC 24	Sep 25 02:51:13 AM UTC 24	3722536420 ps
T323	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.2471497781	Sep 25 02:41:33 AM UTC 24	Sep 25 02:51:45 AM UTC 24	3644277762 ps
T77	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1084633849	Sep 25 02:44:47 AM UTC 24	Sep 25 02:51:56 AM UTC 24	7352763592 ps
T441	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.107790265	Sep 25 02:40:19 AM UTC 24	Sep 25 02:52:25 AM UTC 24	4766465246 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.975225598	Sep 25 02:14:42 AM UTC 24	Sep 25 02:52:29 AM UTC 24	22213976082 ps
T351	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3535202918	Sep 25 02:45:57 AM UTC 24	Sep 25 02:52:48 AM UTC 24	3772460750 ps
T136	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3741792834	Sep 25 02:02:13 AM UTC 24	Sep 25 02:52:48 AM UTC 24	12569854156 ps
T32	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.1320979238	Sep 25 02:49:20 AM UTC 24	Sep 25 02:52:50 AM UTC 24	2819210088 ps
T442	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1702800439	Sep 25 02:42:33 AM UTC 24	Sep 25 02:53:08 AM UTC 24	5111818144 ps
T443	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.978738293	Sep 25 02:50:51 AM UTC 24	Sep 25 02:53:16 AM UTC 24	1893608234 ps
T444	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.4284698278	Sep 25 02:23:52 AM UTC 24	Sep 25 02:53:16 AM UTC 24	6875394190 ps
T33	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.2326643196	Sep 25 02:50:07 AM UTC 24	Sep 25 02:53:40 AM UTC 24	3279575298 ps
T277	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.4260852875	Sep 25 02:29:12 AM UTC 24	Sep 25 02:53:47 AM UTC 24	8186601040 ps
T204	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.256470271	Sep 25 02:10:16 AM UTC 24	Sep 25 02:53:50 AM UTC 24	25290844220 ps
T34	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.747321561	Sep 25 02:49:48 AM UTC 24	Sep 25 02:53:50 AM UTC 24	3382403794 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.3926874454	Sep 25 02:03:07 AM UTC 24	Sep 25 02:53:53 AM UTC 24	11767659176 ps
T91	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2481819676	Sep 25 02:47:49 AM UTC 24	Sep 25 02:54:42 AM UTC 24	4976943552 ps
T221	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2829157128	Sep 25 02:50:51 AM UTC 24	Sep 25 02:55:07 AM UTC 24	3423578236 ps
T343	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.2664269213	Sep 25 02:28:55 AM UTC 24	Sep 25 02:55:28 AM UTC 24	7452170720 ps
T344	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.153252365	Sep 25 02:21:50 AM UTC 24	Sep 25 02:55:31 AM UTC 24	8205856600 ps
T345	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4193416703	Sep 25 02:51:50 AM UTC 24	Sep 25 02:55:45 AM UTC 24	3118521739 ps
T209	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.2327364004	Sep 25 02:44:43 AM UTC 24	Sep 25 02:55:46 AM UTC 24	5340999256 ps
T185	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2595249476	Sep 25 02:47:10 AM UTC 24	Sep 25 02:56:00 AM UTC 24	6676820600 ps
T229	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2746417529	Sep 25 02:36:32 AM UTC 24	Sep 25 02:56:03 AM UTC 24	13491550500 ps
T222	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4026041221	Sep 25 02:50:55 AM UTC 24	Sep 25 02:56:09 AM UTC 24	3007998625 ps
T172	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4236724162	Sep 25 02:46:56 AM UTC 24	Sep 25 02:56:16 AM UTC 24	7004672854 ps
T261	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.1993677803	Sep 25 02:35:13 AM UTC 24	Sep 25 02:56:24 AM UTC 24	6992614782 ps
T92	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3292943170	Sep 25 02:48:33 AM UTC 24	Sep 25 02:57:06 AM UTC 24	5353154162 ps
T99	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2505732537	Sep 25 02:48:17 AM UTC 24	Sep 25 02:57:34 AM UTC 24	3935152830 ps
T896	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.3819743774	Sep 25 02:51:48 AM UTC 24	Sep 25 02:57:34 AM UTC 24	3593162328 ps
T278	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1845787910	Sep 25 02:28:15 AM UTC 24	Sep 25 02:57:47 AM UTC 24	7369250040 ps
T897	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3309271597	Sep 25 02:53:08 AM UTC 24	Sep 25 02:57:48 AM UTC 24	3207230464 ps
T93	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1511654014	Sep 25 02:48:18 AM UTC 24	Sep 25 02:57:59 AM UTC 24	5541318580 ps
T150	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3888979630	Sep 25 02:29:04 AM UTC 24	Sep 25 02:58:09 AM UTC 24	10352235222 ps
T419	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.2120076574	Sep 25 02:51:23 AM UTC 24	Sep 25 02:58:29 AM UTC 24	2656064772 ps
T898	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3931255833	Sep 25 02:53:49 AM UTC 24	Sep 25 02:58:55 AM UTC 24	3128707588 ps
T273	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.2992054062	Sep 25 02:25:57 AM UTC 24	Sep 25 02:59:11 AM UTC 24	7662482408 ps
T256	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.1634077431	Sep 25 02:35:31 AM UTC 24	Sep 25 02:59:47 AM UTC 24	11487656172 ps
T678	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.1640028976	Sep 25 02:44:43 AM UTC 24	Sep 25 03:00:29 AM UTC 24	6637384820 ps
T371	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3144181690	Sep 25 02:55:13 AM UTC 24	Sep 25 03:00:30 AM UTC 24	3386801502 ps
T421	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.3396772022	Sep 25 02:57:22 AM UTC 24	Sep 25 03:00:58 AM UTC 24	2596101714 ps
T218	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2196112010	Sep 25 02:55:13 AM UTC 24	Sep 25 03:03:22 AM UTC 24	3984722078 ps
T363	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3132489415	Sep 25 02:52:30 AM UTC 24	Sep 25 03:04:50 AM UTC 24	5151895683 ps
T75	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.701455061	Sep 25 02:55:17 AM UTC 24	Sep 25 03:05:38 AM UTC 24	4039051232 ps
T88	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2862714310	Sep 25 02:49:41 AM UTC 24	Sep 25 03:05:50 AM UTC 24	8850754478 ps
T899	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.3929853403	Sep 25 02:51:45 AM UTC 24	Sep 25 03:06:20 AM UTC 24	6187212280 ps
T141	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.2029021233	Sep 25 02:55:50 AM UTC 24	Sep 25 03:08:54 AM UTC 24	11200949430 ps
T78	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1289003448	Sep 25 02:46:56 AM UTC 24	Sep 25 03:09:59 AM UTC 24	24448445082 ps
T900	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4010439213	Sep 25 02:52:33 AM UTC 24	Sep 25 03:10:49 AM UTC 24	7707545072 ps
T901	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.327793907	Sep 25 02:16:04 AM UTC 24	Sep 25 03:11:42 AM UTC 24	28679116152 ps
T902	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.688393053	Sep 25 02:55:41 AM UTC 24	Sep 25 03:14:46 AM UTC 24	5771221676 ps
T79	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.35008612	Sep 25 02:45:57 AM UTC 24	Sep 25 03:16:53 AM UTC 24	23842769612 ps
T280	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.1256687509	Sep 25 02:28:27 AM UTC 24	Sep 25 03:16:58 AM UTC 24	12089160748 ps
T281	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.1195991584	Sep 25 02:29:19 AM UTC 24	Sep 25 03:17:39 AM UTC 24	12660065110 ps
T37	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.4278117806	Sep 25 02:55:51 AM UTC 24	Sep 25 03:19:31 AM UTC 24	5665461530 ps
T151	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2415642746	Sep 25 02:54:00 AM UTC 24	Sep 25 03:23:26 AM UTC 24	9984131207 ps
T38	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.971347079	Sep 25 02:42:37 AM UTC 24	Sep 25 03:25:48 AM UTC 24	23532345635 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.336128244	Sep 25 02:15:07 AM UTC 24	Sep 25 03:26:31 AM UTC 24	21076076926 ps
T903	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3787509459	Sep 25 02:34:16 AM UTC 24	Sep 25 03:27:44 AM UTC 24	24044372708 ps
T420	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2821153798	Sep 25 02:01:16 AM UTC 24	Sep 25 03:28:01 AM UTC 24	18974485762 ps
T152	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4132540265	Sep 25 02:16:13 AM UTC 24	Sep 25 03:35:19 AM UTC 24	18061141585 ps
T190	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.458488270	Sep 25 02:16:09 AM UTC 24	Sep 25 03:38:06 AM UTC 24	17600894392 ps
T215	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.2214115230	Sep 25 02:54:58 AM UTC 24	Sep 25 03:38:38 AM UTC 24	21510603236 ps
T225	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2822571353	Sep 25 02:03:05 AM UTC 24	Sep 25 03:38:53 AM UTC 24	43252924880 ps
T284	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.1738623069	Sep 25 02:29:15 AM UTC 24	Sep 25 03:52:11 AM UTC 24	14572252200 ps
T312	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.1676571121	Sep 25 02:24:12 AM UTC 24	Sep 25 03:52:37 AM UTC 24	18058253116 ps
T324	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.4179303103	Sep 25 03:52:46 AM UTC 24	Sep 25 03:55:31 AM UTC 24	2994924914 ps
T100	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.398805156	Sep 25 03:53:12 AM UTC 24	Sep 25 03:58:21 AM UTC 24	4915926713 ps
T287	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.859632199	Sep 25 02:08:02 AM UTC 24	Sep 25 03:59:08 AM UTC 24	49054933520 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2890539570	Sep 25 03:00:05 AM UTC 24	Sep 25 04:00:04 AM UTC 24	11692448424 ps
T904	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2756139434	Sep 25 02:08:24 AM UTC 24	Sep 25 04:00:49 AM UTC 24	26694821072 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.297963142	Sep 25 03:03:31 AM UTC 24	Sep 25 04:01:16 AM UTC 24	11550018300 ps
T905	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.2463829648	Sep 25 03:59:40 AM UTC 24	Sep 25 04:03:54 AM UTC 24	2831526244 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.931020371	Sep 25 03:02:09 AM UTC 24	Sep 25 04:04:19 AM UTC 24	11444955456 ps
T288	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.3158586839	Sep 25 02:08:22 AM UTC 24	Sep 25 04:04:44 AM UTC 24	51230113208 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2593467575	Sep 25 03:07:00 AM UTC 24	Sep 25 04:05:15 AM UTC 24	11389952856 ps
T906	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.2103813221	Sep 25 04:01:24 AM UTC 24	Sep 25 04:06:09 AM UTC 24	2627083048 ps
T907	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.1960852198	Sep 25 04:01:50 AM UTC 24	Sep 25 04:06:36 AM UTC 24	3004326774 ps
T908	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.3340687171	Sep 25 04:00:41 AM UTC 24	Sep 25 04:06:38 AM UTC 24	2923003170 ps
T42	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.2116750008	Sep 25 04:04:54 AM UTC 24	Sep 25 04:08:43 AM UTC 24	3422219451 ps
T909	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.631594864	Sep 25 03:58:57 AM UTC 24	Sep 25 04:09:37 AM UTC 24	4912034298 ps
T910	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.382316261	Sep 25 04:05:50 AM UTC 24	Sep 25 04:11:02 AM UTC 24	3203685410 ps
T911	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.1251525876	Sep 25 04:07:22 AM UTC 24	Sep 25 04:12:24 AM UTC 24	2402416200 ps
T912	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.1611982422	Sep 25 04:05:19 AM UTC 24	Sep 25 04:12:34 AM UTC 24	3113463960 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.4242298256	Sep 25 02:57:31 AM UTC 24	Sep 25 04:13:06 AM UTC 24	28700490250 ps
T913	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.478866118	Sep 25 04:04:29 AM UTC 24	Sep 25 04:13:20 AM UTC 24	3798007052 ps
T406	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.1629989394	Sep 25 02:58:21 AM UTC 24	Sep 25 04:14:09 AM UTC 24	14164424840 ps
T914	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.448977821	Sep 25 03:15:29 AM UTC 24	Sep 25 04:14:49 AM UTC 24	11046457871 ps
T258	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.3774392117	Sep 25 04:10:11 AM UTC 24	Sep 25 04:15:12 AM UTC 24	2913484228 ps
T915	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.4070177354	Sep 25 04:13:47 AM UTC 24	Sep 25 04:15:44 AM UTC 24	2448036744 ps
T916	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.363625227	Sep 25 04:13:09 AM UTC 24	Sep 25 04:16:42 AM UTC 24	2407030180 ps
T191	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.146751954	Sep 25 02:53:08 AM UTC 24	Sep 25 04:17:06 AM UTC 24	24782889714 ps
T417	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.107300847	Sep 25 04:09:17 AM UTC 24	Sep 25 04:17:06 AM UTC 24	5999664130 ps
T917	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.1547644294	Sep 25 04:07:22 AM UTC 24	Sep 25 04:17:31 AM UTC 24	6239364110 ps
T918	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.129851516	Sep 25 04:13:40 AM UTC 24	Sep 25 04:17:34 AM UTC 24	3107625470 ps
T132	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.1796366591	Sep 25 04:11:37 AM UTC 24	Sep 25 04:17:48 AM UTC 24	2974806108 ps
T919	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.587840255	Sep 25 04:13:09 AM UTC 24	Sep 25 04:17:52 AM UTC 24	3067251496 ps
T920	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.194165285	Sep 25 04:12:44 AM UTC 24	Sep 25 04:18:02 AM UTC 24	3091446792 ps
T381	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.287091543	Sep 25 03:05:29 AM UTC 24	Sep 25 04:18:07 AM UTC 24	14467122134 ps
T921	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1605794709	Sep 25 03:11:28 AM UTC 24	Sep 25 04:18:32 AM UTC 24	15079336116 ps
T294	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2350151364	Sep 25 02:10:15 AM UTC 24	Sep 25 04:18:59 AM UTC 24	47392683112 ps
T922	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.1434990155	Sep 25 02:57:32 AM UTC 24	Sep 25 04:19:20 AM UTC 24	14840466600 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.1812641961	Sep 25 04:19:19 AM UTC 24	Sep 25 04:32:03 AM UTC 24	4233521640 ps
T923	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1743440217	Sep 25 02:59:36 AM UTC 24	Sep 25 04:19:42 AM UTC 24	14980009800 ps
T924	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.1965489231	Sep 25 04:14:41 AM UTC 24	Sep 25 04:19:51 AM UTC 24	3165380680 ps
T925	/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.402350938	Sep 25 04:15:24 AM UTC 24	Sep 25 04:20:13 AM UTC 24	2577164906 ps