Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	487	1			T544	1		T552	2		T856	1
all_values[1]	476	1			T544	1		T552	3		T637	2
all_values[2]	489	1			T544	1		T856	1		T579	5
all_values[3]	489	1			T439	2		T679	1		T544	5
all_values[4]	488	1			T544	1		T552	3		T579	1
all_values[5]	457	1			T466	2		T552	2		T579	2
all_values[6]	467	1			T544	2		T856	1		T788	2
all_values[7]	469	1			T439	1		T679	1		T544	2
all_values[8]	470	1			T544	2		T552	1		T856	1
all_values[9]	509	1			T466	1		T679	1		T544	3
all_values[10]	469	1			T466	1		T439	1		T579	2
all_values[11]	477	1			T552	1		T856	1		T579	5
all_values[12]	443	1			T544	3		T432	1		T788	1
all_values[13]	487	1			T544	4		T579	3		T637	3
all_values[14]	486	1			T439	1		T679	1		T552	1
all_values[15]	472	1			T679	1		T544	1		T552	4
all_values[16]	493	1			T679	1		T544	2		T552	3
all_values[17]	491	1			T552	1		T856	1		T579	2
all_values[18]	497	1			T679	1		T544	4		T552	2
all_values[19]	467	1			T544	2		T552	1		T637	2
all_values[20]	469	1			T544	4		T856	1		T579	3
all_values[21]	446	1			T544	2		T552	2		T856	1
all_values[22]	490	1			T544	1		T552	2		T579	3
all_values[23]	491	1			T544	3		T552	3		T579	3
all_values[24]	490	1			T544	3		T579	4		T637	3
all_values[25]	469	1			T544	1		T552	2		T856	1
all_values[26]	461	1			T544	1		T552	3		T579	2
all_values[27]	471	1			T679	1		T544	4		T552	2
all_values[28]	506	1			T439	1		T544	1		T552	1
all_values[29]	444	1			T544	3		T552	1		T579	1
all_values[30]	426	1			T439	1		T544	1		T552	1
all_values[31]	482	1			T544	3		T788	1		T579	1
all_values[32]	456	1			T544	2		T552	1		T579	1
all_values[33]	483	1			T439	2		T544	2		T788	1
all_values[34]	468	1			T544	2		T579	2		T637	3
all_values[35]	474	1			T439	1		T544	2		T552	1
all_values[36]	478	1			T439	1		T679	1		T544	4
all_values[37]	476	1			T439	1		T552	3		T856	1
all_values[38]	475	1			T439	1		T544	1		T856	2
all_values[39]	462	1			T439	1		T544	5		T552	1
all_values[40]	449	1			T544	2		T552	1		T788	1
all_values[41]	498	1			T544	4		T552	1		T579	2
all_values[42]	449	1			T544	3		T552	1		T432	1
all_values[43]	464	1			T544	5		T856	1		T579	1
all_values[44]	447	1			T544	3		T552	2		T856	1
all_values[45]	537	1			T544	4		T579	3		T637	3
all_values[46]	460	1			T552	1		T856	1		T579	4
all_values[47]	459	1			T439	1		T544	3		T552	2
all_values[48]	460	1			T439	1		T679	1		T544	2
all_values[49]	471	1			T544	1		T552	1		T579	1