Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3552	1			T466	2		T445	3		T544	13
all_values[1]	3605	1			T103	3		T466	1		T544	17
all_values[2]	3428	1			T103	1		T466	3		T445	3
all_values[3]	3540	1			T103	1		T466	3		T445	3
all_values[4]	3407	1			T103	2		T466	1		T445	1
all_values[5]	3532	1			T103	1		T466	1		T445	5
all_values[6]	3444	1			T103	2		T544	15		T552	5
all_values[7]	3525	1			T103	1		T445	2		T544	16
all_values[8]	3473	1			T103	2		T466	1		T445	1
all_values[9]	3432	1			T103	3		T466	2		T445	2
all_values[10]	3556	1			T445	3		T544	18		T552	1
all_values[11]	3566	1			T466	2		T445	3		T544	15
all_values[12]	3579	1			T466	3		T445	3		T544	20
all_values[13]	3613	1			T103	1		T466	1		T445	1
all_values[14]	3365	1			T466	1		T544	11		T552	8
all_values[15]	3708	1			T103	2		T466	1		T445	2
all_values[16]	3574	1			T103	2		T466	2		T445	1
all_values[17]	3546	1			T103	2		T466	3		T445	3
all_values[18]	3623	1			T103	1		T445	3		T544	10
all_values[19]	3523	1			T103	1		T466	3		T445	4
all_values[20]	3465	1			T103	4		T466	1		T445	2
all_values[21]	3530	1			T445	4		T544	19		T552	7
all_values[22]	3407	1			T466	2		T445	3		T544	15
all_values[23]	3603	1			T103	1		T466	1		T544	15
all_values[24]	3557	1			T466	2		T445	1		T544	20
all_values[25]	3516	1			T103	1		T445	1		T544	16
all_values[26]	3514	1			T103	1		T466	2		T445	3
all_values[27]	3538	1			T103	1		T466	1		T445	1
all_values[28]	3594	1			T103	2		T466	3		T445	2
all_values[29]	3509	1			T445	4		T544	14		T552	6
all_values[30]	3568	1			T466	2		T445	4		T544	23
all_values[31]	3402	1			T445	3		T544	10		T552	9
all_values[32]	3535	1			T103	1		T466	1		T445	2
all_values[33]	3534	1			T103	2		T466	3		T445	4
all_values[34]	3480	1			T466	1		T445	2		T544	12
all_values[35]	3480	1			T103	2		T445	2		T544	14
all_values[36]	3629	1			T466	4		T445	1		T544	21
all_values[37]	3591	1			T103	1		T466	1		T445	1
all_values[38]	3503	1			T103	1		T466	1		T445	4
all_values[39]	3499	1			T103	1		T466	2		T445	1
all_values[40]	3541	1			T103	1		T466	1		T445	2
all_values[41]	3510	1			T103	2		T466	2		T445	1
all_values[42]	3529	1			T103	1		T466	3		T445	3
all_values[43]	3530	1			T103	1		T466	1		T445	1
all_values[44]	3475	1			T103	1		T466	3		T544	8
all_values[45]	3528	1			T103	2		T466	2		T445	5
all_values[46]	3573	1			T103	1		T445	2		T544	17
all_values[47]	3522	1			T103	1		T445	5		T544	23
all_values[48]	3560	1			T103	2		T445	2		T544	17
all_values[49]	3430	1			T445	3		T544	17		T552	4
all_values[50]	3621	1			T103	1		T466	3		T445	2
all_values[51]	3441	1			T103	1		T445	4		T544	18
all_values[52]	3485	1			T103	1		T466	1		T445	2
all_values[53]	3497	1			T103	2		T466	1		T445	2
all_values[54]	3508	1			T103	1		T466	1		T445	2
all_values[55]	3547	1			T445	4		T544	14		T552	2
all_values[56]	3472	1			T103	1		T466	2		T445	3
all_values[57]	3611	1			T466	3		T445	1		T544	18
all_values[58]	3466	1			T466	3		T445	1		T544	19
all_values[59]	3481	1			T103	1		T466	3		T445	4
all_values[60]	3582	1			T103	2		T445	1		T544	26
all_values[61]	3436	1			T103	1		T466	3		T445	3
all_values[62]	3590	1			T445	2		T544	20		T552	4
all_values[63]	3566	1			T103	1		T445	2		T544	9