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LINE 12261
EXPRESSION (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T47,T48 |
LINE 12430
EXPRESSION (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T484,T485,T486 |
LINE 12599
EXPRESSION (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T487,T488,T489 |
LINE 12768
EXPRESSION (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T490,T491,T492 |
LINE 12937
EXPRESSION (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T446,T472,T469 |
LINE 13106
EXPRESSION (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T12,T53,T54 |
LINE 13275
EXPRESSION (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T473,T493,T475 |
LINE 13444
EXPRESSION (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T47,T48 |
LINE 13613
EXPRESSION (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
LINE 13782
EXPRESSION (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T439,T494,T495 |
LINE 13951
EXPRESSION (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
LINE 14120
EXPRESSION (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T37,T47 |
LINE 14289
EXPRESSION (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T37,T47 |
LINE 14458
EXPRESSION (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T37,T47 |
LINE 14627
EXPRESSION (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T496,T497,T479 |
LINE 14796
EXPRESSION (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T479,T484,T473 |
LINE 14965
EXPRESSION (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T479,T468,T469 |
LINE 15134
EXPRESSION (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T447,T498,T499 |
LINE 15303
EXPRESSION (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T447,T500,T501 |
LINE 15472
EXPRESSION (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T448,T499,T502 |
LINE 15641
EXPRESSION (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T58,T55,T59 |
LINE 15810
EXPRESSION (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T58,T55,T59 |
LINE 15979
EXPRESSION (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T58,T55,T59 |
LINE 16148
EXPRESSION (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 16317
EXPRESSION (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T470,T482,T503 |
LINE 16486
EXPRESSION (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T504,T487,T482 |
LINE 16655
EXPRESSION (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T169,T469,T473 |
LINE 16824
EXPRESSION (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T505,T506,T507 |
LINE 16993
EXPRESSION (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T447,T479,T508 |
LINE 17162
EXPRESSION (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T469,T502,T509 |
LINE 17331
EXPRESSION (mio_pad_attr_32_we & mio_pad_attr_regwen_32_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T450,T510,T511 |
LINE 17500
EXPRESSION (mio_pad_attr_33_we & mio_pad_attr_regwen_33_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T470,T512,T513 |
LINE 17669
EXPRESSION (mio_pad_attr_34_we & mio_pad_attr_regwen_34_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T472,T514,T468 |
LINE 17838
EXPRESSION (mio_pad_attr_35_we & mio_pad_attr_regwen_35_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T449,T515,T516 |
LINE 18007
EXPRESSION (mio_pad_attr_36_we & mio_pad_attr_regwen_36_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T517,T483,T486 |
LINE 18176
EXPRESSION (mio_pad_attr_37_we & mio_pad_attr_regwen_37_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T479,T518,T519 |
LINE 18345
EXPRESSION (mio_pad_attr_38_we & mio_pad_attr_regwen_38_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T493,T474,T520 |
LINE 18514
EXPRESSION (mio_pad_attr_39_we & mio_pad_attr_regwen_39_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T468,T482,T521 |
LINE 18683
EXPRESSION (mio_pad_attr_40_we & mio_pad_attr_regwen_40_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T432,T472,T522 |
LINE 18852
EXPRESSION (mio_pad_attr_41_we & mio_pad_attr_regwen_41_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T523,T478,T524 |
LINE 19021
EXPRESSION (mio_pad_attr_42_we & mio_pad_attr_regwen_42_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T479,T525,T508 |
LINE 19190
EXPRESSION (mio_pad_attr_43_we & mio_pad_attr_regwen_43_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T468,T487,T484 |
LINE 19359
EXPRESSION (mio_pad_attr_44_we & mio_pad_attr_regwen_44_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T481,T469,T487 |
LINE 19528
EXPRESSION (mio_pad_attr_45_we & mio_pad_attr_regwen_45_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T439,T526,T479 |
LINE 19697
EXPRESSION (mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T501,T487,T473 |
LINE 20330
EXPRESSION (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 20499
EXPRESSION (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 20668
EXPRESSION (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
LINE 20837
EXPRESSION (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
LINE 21006
EXPRESSION (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
LINE 21175
EXPRESSION (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
LINE 21344
EXPRESSION (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T469,T518,T527 |
LINE 21513
EXPRESSION (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T528,T529,T530 |
LINE 21682
EXPRESSION (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T491,T531,T532 |
LINE 21851
EXPRESSION (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T476,T533,T534 |
LINE 22020
EXPRESSION (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T15,T51,T52 |
LINE 22189
EXPRESSION (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T15,T51,T52 |
LINE 22358
EXPRESSION (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T432,T482,T535 |
LINE 22527
EXPRESSION (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T482,T536,T537 |
LINE 22696
EXPRESSION (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T47,T48 |
LINE 22865
EXPRESSION (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T47,T48 |
LINE 25669
EXPRESSION (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T179,T188 |
1 | 1 | Covered | T2,T25,T19 |
LINE 25701
EXPRESSION (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T188,T180,T189 |
1 | 1 | Covered | T2,T25,T19 |
LINE 25733
EXPRESSION (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T188,T189,T538 |
1 | 1 | Covered | T2,T25,T19 |
LINE 25765
EXPRESSION (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T426,T184 |
1 | 1 | Covered | T2,T25,T19 |
LINE 25797
EXPRESSION (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T189,T427 |
1 | 1 | Covered | T2,T25,T19 |
LINE 25829
EXPRESSION (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T428,T538 |
1 | 1 | Covered | T2,T25,T19 |
LINE 25861
EXPRESSION (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T426,T413,T414 |
1 | 1 | Covered | T2,T25,T19 |
LINE 25893
EXPRESSION (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T426,T184,T428 |
1 | 1 | Covered | T2,T6,T25 |
LINE 25925
EXPRESSION (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T427,T184 |
1 | 1 | Covered | T2,T19,T40 |
LINE 25957
EXPRESSION (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T179,T188 |
1 | 1 | Covered | T2,T19,T40 |
LINE 25989
EXPRESSION (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T188,T401 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26021
EXPRESSION (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T180,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26053
EXPRESSION (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T189,T184 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26085
EXPRESSION (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T179,T183 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26117
EXPRESSION (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T189,T426,T427 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26149
EXPRESSION (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T188,T183 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26181
EXPRESSION (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T189,T413,T414 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26213
EXPRESSION (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T401,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26245
EXPRESSION (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T401,T183,T414 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26277
EXPRESSION (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T188,T183,T413 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26309
EXPRESSION (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T179,T427 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26341
EXPRESSION (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T189,T426 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26373
EXPRESSION (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T189,T538 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26405
EXPRESSION (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T401,T426,T414 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26437
EXPRESSION (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T179,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26469
EXPRESSION (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T189,T183,T184 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26501
EXPRESSION (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T188,T180,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26533
EXPRESSION (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T188,T401,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26565
EXPRESSION (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T180,T183 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26597
EXPRESSION (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T188,T401 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26629
EXPRESSION (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T189,T427 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26661
EXPRESSION (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T188,T428 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26693
EXPRESSION (mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T189,T184,T413 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26725
EXPRESSION (mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T189,T428 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26757
EXPRESSION (mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T401,T180,T427 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26789
EXPRESSION (mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T188,T189,T426 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26821
EXPRESSION (mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T180,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26853
EXPRESSION (mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T189,T426 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26885
EXPRESSION (mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T401,T180,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26917
EXPRESSION (mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T179,T180 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26949
EXPRESSION (mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T180,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 26981
EXPRESSION (mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T180,T428 |
1 | 1 | Covered | T2,T19,T40 |
LINE 27013
EXPRESSION (mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T189,T427 |
1 | 1 | Covered | T2,T19,T40 |
LINE 27045
EXPRESSION (mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T177,T179,T401 |
1 | 1 | Covered | T2,T19,T40 |
LINE 27077
EXPRESSION (mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T189,T427,T428 |
1 | 1 | Covered | T2,T19,T40 |
LINE 27109
EXPRESSION (mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T188,T180,T189 |
1 | 1 | Covered | T2,T19,T40 |
LINE 27141
EXPRESSION (mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T189,T413 |
1 | 1 | Covered | T2,T19,T40 |
LINE 27173
EXPRESSION (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T180,T427,T183 |
1 | 1 | Covered | T2,T25,T19 |
LINE 27205
EXPRESSION (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T179,T401,T180 |
1 | 1 | Covered | T2,T25,T19 |
LINE 27237
EXPRESSION (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T189,T429,T430 |
1 | 1 | Covered | T2,T25,T19 |