Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T133 T252 T257 | T133 T252 T257 | T133 T252 T258 | T133 T252 T258 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T133 T252 T257 | T134 T135 T252 | T134 T135 T252 | T134 T135 T252 | T134 T135 T252 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T134 T135 T252 | T68 T252 T69 | T68 T252 T69 | T68 T252 T69 | T68 T252 T69 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T68 T252 T69 | T26 T70 T252 | T26 T70 T252 | T26 T70 T252 | T26 T70 T252 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T26 T70 T252 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T10 T131 T236 | T131 T196 T197 | T131 T196 T197 | T131 T196 T197 | T131 T196 T197 | T12 T131 T53 | T131 T196 T197 | T131 T196 T197 | T62 T261 T63 | T62 T261 T63 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T62 T261 T63 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T65 T261 T144 | T65 T261 T144 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T64 T65 T261 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T66 T261 T67 | T66 T261 T67 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T66 T261 T67 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T5 T131 T196 | T5 T131 T140 | T131 T196 T197 | T131 T196 T197 | T131 T196 T197 | T198 T264 T350 | T86 T87 T266 | T261 T267 T262 | T45 T199 T261 | T131 T196 T197 | T131 T196 T197 | T131 T196 T197 | T131 T196 T197 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T4 T6 T25 | T72 T252 T243 | T145 T261 T268 | T269 T270 T351 | T146 T270 T350 | T186 T131 T272 | T131 T196 T197 | T124 T153 T253 | T124 T153 T253 | T153 T253 T261 | T153 T253 T261 | T124 T153 T253 | T261 T262 T263 | T254 T255 T261 | T261 T262 T263 | T261 T262 T263 | T131 T196 T197 | T131 T196 T197 | T131 T196 T197 | T168 T131 T152 | T131 T196 T197 | T261 T262 T263 | T261 T273 T274 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T273 T274 | T261 T262 T263 | T261 T273 T274 | T261 T262 T263
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T249 T250 T251 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T12 T27 T10 | T12 T249 T131 | T12 T249 T131 | T12 T10 T11 | T12 T10 T11 | T12 T249 T131 | T249 T131 T252 | T249 T131 T252 | T62 T249 T131 | T62 T249 T131 | T249 T131 T252 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T249 T131 T252 | T62 T249 T131 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T65 T249 T131 | T65 T249 T131 | T249 T131 T252 | T65 T249 T131 | T65 T249 T131 | T65 T249 T131 | T65 T249 T131 | T65 T249 T131 | T249 T131 T252 | T64 T65 T249 | T64 T249 T131 | T249 T131 T252 | T64 T249 T131 | T64 T249 T131 | T64 T249 T131 | T66 T249 T131 | T66 T249 T131 | T249 T131 T252 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T249 T131 T252 | T66 T249 T131 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T5 T249 T131 | T5 T249 T131 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T45 T86 T87 | T45 T86 T87 | T45 T86 T87 | T45 T86 T87 | T10 T11 T249 | T10 T11 T249 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T2 T4 T6 | T72 T249 T131 | T145 T249 T131 | T45 T86 T87 | T45 T146 T86 | T249 T186 T131 | T249 T131 T252 | T124 T153 T253 | T124 T153 T253 | T124 T153 T253 | T124 T153 T253 | T124 T153 T253 | T249 T131 T252 | T254 T255 T249 | T254 T255 T249 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T168 T249 T131 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T4 T5 T6 | T5 T12 T26 | T26 T27 T134 | T5 T12 T27 | T4 T6 T25 | T26 T134 T133 | T26 T27 T70 | T12 T27 T62 | T5 T66 T64 | T4 T6 T25 | T124 T153 T253 | T134 T133 T135 | T26 T134 T68 | T26 T27 T70 | T27 T249 T131 | T12 T27 T62 | T62 T65 T249 | T66 T64 T65 | T5 T66 T198 | T45 T86 T87 | T4 T6 T25 | T124 T153 T253 | T249 T131 T252 | T133 T249 T131 | T134 T133 T135 | T134 T68 T135 | T26 T68 T70 | T26 T27 T70 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T10 T249 | T12 T62 T10 | T62 T249 T131 | T65 T249 T131 | T64 T65 T249 | T66 T64 T249 | T66 T249 T131 | T5 T198 T264 | T45 T10 T86 | T249 T131 T252 | T249 T131 T252 | T4 T6 T25 | T124 T153 T253 | T168 T249 T131 | T249 T131 T252 | T133 T249 T131 | T133 T249 T131 | T134 T133 T135 | T134 T135 T249 | T134 T68 T135 | T68 T249 T131 | T68 T249 T131 | T26 T70 T249 | T26 T70 T249 | T26 T27 T70 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T12 T27 T10 | T12 T10 T11 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T249 T131 T252 | T65 T249 T131 | T65 T249 T131 | T64 T65 T249 | T66 T64 T249 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T5 T249 T131 | T198 T264 T350 | T45 T86 T87 | T10 T11 T249 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T4 T6 T25 | T45 T146 T86 | T124 T153 T253 | T124 T153 T253 | T249 T131 T252 | T168 T249 T131 | T249 T131 T252 | T249 T131 T252 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T68 T135 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T27 T70 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T12 T27 T10 | T12 T249 T131 | T12 T10 T11 | T12 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T249 T131 T252 | T249 T131 T252 | T65 T249 T131 | T65 T249 T131 | T65 T249 T131 | T65 T249 T131 | T64 T65 T249 | T64 T249 T131 | T64 T249 T131 | T66 T64 T249 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T249 T131 T252 | T249 T131 T252 | T5 T249 T131 | T249 T131 T252 | T45 T86 T87 | T45 T86 T87 | T45 T10 T86 | T10 T11 T249 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T2 T4 T6 | T72 T145 T249 | T45 T146 T86 | T249 T186 T131 | T124 T153 T253 | T124 T153 T253 | T124 T153 T253 | T254 T255 T249 | T249 T131 T252 | T249 T131 T252 | T168 T249 T131 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T4 T5 T6 | T5 T12 T26 | T4 T6 T25 | T26 T27 T134 | T5 T12 T27 | T4 T6 T25 | T26 T134 T133 | T26 T27 T70 | T12 T27 T62 | T5 T66 T64 | T4 T6 T25 | T124 T153 T253 | T134 T133 T135 | T26 T134 T68 | T26 T27 T70 | T27 T261 T43 | T12 T27 T62 | T62 T65 T261 | T66 T64 T65 | T5 T66 T198 | T45 T86 T87 | T4 T6 T25 | T124 T153 T253 | T261 T273 T274 | T133 T252 T258 | T134 T133 T135 | T134 T68 T135 | T26 T68 T70 | T26 T27 T70 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T10 T131 | T12 T62 T131 | T62 T261 T63 | T65 T261 T144 | T64 T65 T261 | T66 T261 T67 | T66 T261 T67 | T5 T198 T264 | T45 T86 T87 | T252 T259 T260 | T252 T259 T260 | T4 T6 T25 | T124 T153 T253 | T168 T131 T261 | T261 T273 T274 | T261 T273 T274 | T133 T252 T258 | T133 T252 T258 | T134 T133 T135 | T134 T135 T252 | T134 T68 T135 | T68 T252 T69 | T68 T252 T69 | T26 T70 T252 | T252 T259 T260 | T26 T27 T70 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T10 T131 | T12 T131 T53 | T62 T131 T261 | T261 T262 T263 | T62 T261 T63 | T261 T262 T263 | T65 T261 T144 | T261 T262 T263 | T64 T65 T261 | T66 T261 T67 | T66 T261 T67 | T261 T262 T263 | T66 T261 T67 | T5 T131 T261 | T198 T264 T350 | T45 T86 T87 | T131 T252 T196 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T4 T6 T25 | T146 T269 T270 | T124 T153 T253 | T124 T153 T253 | T131 T261 T196 | T168 T131 T261 | T261 T262 T263 | T261 T273 T274 | T261 T273 T274 | T133 T252 T257 | T133 T252 T258 | T133 T252 T258 | T252 T259 T260 | T133 T252 T257 | T134 T135 T252 | T134 T135 T252 | T252 T259 T260 | T252 T259 T260 | T134 T68 T135 | T68 T252 T69 | T68 T252 T69 | T252 T259 T260 | T68 T252 T69 | T26 T70 T252 | T26 T70 T252 | T252 T259 T260 | T252 T259 T260 | T26 T27 T70 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T10 T131 | T131 T196 T197 | T131 T196 T197 | T12 T131 T53 | T62 T131 T261 | T62 T261 T63 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T62 T261 T63 | T261 T262 T263 | T261 T262 T263 | T65 T261 T144 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T64 T65 T261 | T261 T262 T263 | T261 T262 T263 | T66 T261 T67 | T66 T261 T67 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T66 T261 T67 | T261 T262 T263 | T261 T262 T263 | T5 T131 T140 | T131 T196 T197 | T198 T264 T350 | T86 T87 T266 | T45 T199 T131 | T131 T196 T197 | T131 T252 T196 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T4 T6 T25 | T72 T145 T252 | T146 T269 T270 | T186 T131 T272 | T124 T153 T253 | T153 T253 T261 | T124 T153 T253 | T254 T255 T261 | T131 T261 T196 | T131 T196 T197 | T168 T131 T152 | T261 T273 T274 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T273 T274 | T261 T273 T274
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T4 T5 T6 | T5 T12 T26 | T4 T6 T25 | T26 T27 T134 | T5 T12 T27 | T4 T6 T25 | T26 T134 T133 | T26 T27 T70 | T12 T27 T62 | T5 T66 T64 | T4 T6 T25 | T124 T153 T253 | T134 T133 T135 | T26 T134 T68 | T26 T27 T70 | T27 T261 T43 | T12 T27 T62 | T62 T65 T261 | T66 T64 T65 | T5 T66 T198 | T45 T199 T131 | T4 T6 T25 | T124 T153 T253 | T261 T273 T274 | T133 T252 T258 | T134 T133 T135 | T134 T68 T135 | T26 T68 T70 | T26 T27 T70 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T10 T131 | T12 T62 T131 | T62 T261 T63 | T65 T261 T144 | T64 T65 T261 | T66 T261 T67 | T66 T261 T67 | T5 T198 T264 | T45 T199 T131 | T252 T259 T260 | T252 T259 T260 | T4 T6 T25 | T124 T153 T253 | T168 T131 T261 | T261 T273 T274 | T261 T262 T263 | T133 T252 T258 | T252 T259 T260 | T134 T133 T135 | T134 T135 T252 | T134 T68 T135 | T68 T252 T69 | T68 T252 T69 | T26 T70 T252 | T252 T259 T260 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T10 T131 T236 | T12 T131 T53 | T62 T261 T63 | T261 T262 T263 | T62 T261 T63 | T261 T262 T263 | T65 T261 T144 | T261 T262 T263 | T64 T65 T261 | T66 T261 T67 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T5 T131 T261 | T198 T264 T350 | T45 T199 T131 | T131 T252 T196 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T4 T6 T25 | T146 T270 T350 | T124 T153 T253 | T254 T255 T261 | T131 T196 T197 | T131 T261 T273 | T261 T262 T263 | T261 T273 T274 | T261 T262 T263 | T133 T252 T257 | T133 T252 T258 | T252 T259 T260 | T252 T259 T260 | T133 T252 T257 | T134 T135 T252 | T134 T135 T252 | T252 T259 T260 | T252 T259 T260 | T68 T252 T69 | T68 T252 T69 | T252 T259 T260 | T252 T259 T260 | T68 T252 T69 | T26 T70 T252 | T26 T70 T252 | T252 T259 T260 | T252 T259 T260 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T27 T261 T43 | T10 T131 T236 | T131 T196 T197 | T131 T196 T197 | T131 T196 T197 | T62 T261 T63 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T65 T261 T144 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T64 T65 T261 | T261 T262 T263 | T261 T262 T263 | T66 T261 T67 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T5 T131 T140 | T131 T196 T197 | T198 T264 T350 | T261 T267 T262 | T131 T196 T197 | T131 T196 T197 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T252 T259 T260 | T4 T6 T25 | T145 T261 T268 | T146 T270 T350 | T131 T196 T197 | T124 T153 T253 | T153 T253 T261 | T261 T262 T263 | T261 T262 T263 | T131 T196 T197 | T131 T196 T197 | T131 T196 T197 | T261 T273 T274 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263 | T261 T262 T263
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T4 T5 T6 | T5 T12 T26 | T4 T6 T25 | T26 T27 T134 | T5 T12 T27 | T4 T6 T25 | T26 T134 T133 | T26 T27 T70 | T12 T27 T62 | T5 T66 T64 | T4 T6 T25 | T124 T153 T253 | T134 T133 T135 | T26 T134 T68 | T26 T27 T70 | T27 T249 T131 | T12 T27 T62 | T62 T65 T249 | T66 T64 T65 | T5 T66 T198 | T45 T86 T87 | T4 T6 T25 | T124 T153 T253 | T249 T131 T252 | T133 T249 T131 | T134 T133 T135 | T134 T68 T135 | T26 T68 T70 | T26 T27 T70 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T10 T249 | T12 T62 T10 | T62 T249 T131 | T65 T249 T131 | T64 T65 T249 | T66 T64 T249 | T66 T249 T131 | T5 T198 T264 | T45 T10 T86 | T249 T131 T252 | T249 T131 T252 | T4 T6 T25 | T124 T153 T253 | T168 T249 T131 | T249 T131 T252 | T249 T131 T252 | T133 T249 T131 | T133 T249 T131 | T134 T133 T135 | T134 T135 T249 | T134 T68 T135 | T68 T249 T131 | T68 T249 T131 | T26 T70 T249 | T26 T70 T249 | T26 T27 T70 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T12 T27 T10 | T12 T10 T11 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T249 T131 T252 | T65 T249 T131 | T65 T249 T131 | T64 T65 T249 | T66 T64 T249 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T5 T249 T131 | T198 T264 T350 | T45 T86 T87 | T10 T11 T249 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T4 T6 T25 | T45 T146 T86 | T124 T153 T253 | T124 T153 T253 | T249 T131 T252 | T168 T249 T131 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T133 T249 T131 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T135 T249 | T134 T68 T135 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T68 T249 T131 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T70 T249 | T26 T27 T70 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T27 T249 T131 | T12 T27 T10 | T12 T249 T131 | T12 T10 T11 | T12 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T62 T249 T131 | T249 T131 T252 | T249 T131 T252 | T65 T249 T131 | T65 T249 T131 | T65 T249 T131 | T65 T249 T131 | T64 T65 T249 | T64 T249 T131 | T64 T249 T131 | T66 T64 T249 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T66 T249 T131 | T249 T131 T252 | T249 T131 T252 | T5 T249 T131 | T249 T131 T252 | T45 T86 T87 | T45 T86 T87 | T45 T10 T86 | T10 T11 T249 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T2 T4 T6 | T72 T145 T249 | T45 T146 T86 | T249 T186 T131 | T124 T153 T253 | T124 T153 T253 | T124 T153 T253 | T254 T255 T249 | T249 T131 T252 | T249 T131 T252 | T168 T249 T131 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252 | T249 T131 T252
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T4 T5 T6
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T4 T5 T6
101 1/1 assign max_value_o = max_tree[0];
Tests: T4 T5 T6
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);