Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	164353	1			T91	3		T92	3		T97	23
values[2]	4286	1			T468	1		T470	1		T452	2
values[3]	2274	1			T538	84		T558	1		T568	1
values[4]	1682	1			T538	53		T559	32		T847	45
values[5]	1392	1			T538	47		T559	22		T847	40
values[6]	1118	1			T538	23		T559	9		T847	24
values[7]	962	1			T538	14		T559	9		T847	21
values[8]	872	1			T538	9		T559	23		T847	35
values[9]	789	1			T538	10		T559	12		T847	27
values[10]	727	1			T538	4		T559	13		T847	22
values[11]	602	1			T538	3		T559	5		T847	12
values[12]	467	1			T538	3		T559	1		T847	8
values[13]	375	1			T538	3		T847	9		T592	4
values[14]	327	1			T847	3		T592	2		T549	3
values[15]	299	1			T847	14		T592	1		T549	4
values[16]	269	1			T847	40		T592	3		T549	6
values[17]	300	1			T847	48		T592	6		T549	1
values[18]	258	1			T847	17		T592	9		T549	2
values[19]	184	1			T847	7		T592	13		T549	5
values[20]	188	1			T847	1		T592	1		T549	4
values[21]	245	1			T549	6		T672	2		T528	2
values[22]	197	1			T549	6		T672	2		T528	3
values[23]	166	1			T549	4		T672	4		T528	2
values[24]	194	1			T549	6		T672	2		T528	3
values[25]	167	1			T549	6		T672	1		T528	4
values[26]	192	1			T549	2		T672	3		T528	1
values[27]	174	1			T549	1		T672	2		T528	1
values[28]	171	1			T549	1		T672	1		T528	1
values[29]	157	1			T549	3		T672	1		T528	2
values[30]	183	1			T549	4		T672	10		T528	2
values[31]	156	1			T549	4		T672	7		T528	1
values[32]	128	1			T549	4		T672	1		T528	2
values[33]	127	1			T549	3		T672	1		T528	6
values[34]	99	1			T549	3		T672	2		T528	5
values[35]	106	1			T549	4		T672	3		T528	4
values[36]	91	1			T549	5		T672	2		T528	1
values[37]	82	1			T549	5		T672	4		T528	5
values[38]	61	1			T549	1		T672	3		T528	1
values[39]	49	1			T549	2		T672	2		T528	1
values[40]	40	1			T549	1		T672	1		T528	1
values[41]	39	1			T549	1		T672	1		T528	3
values[42]	46	1			T549	2		T672	1		T528	3
values[43]	46	1			T549	1		T672	5		T528	1
values[44]	46	1			T549	2		T672	3		T528	1
values[45]	43	1			T549	1		T672	2		T528	1
values[46]	59	1			T549	3		T672	6		T528	1
values[47]	40	1			T549	3		T672	1		T528	2
values[48]	39	1			T549	1		T672	3		T528	1
values[49]	42	1			T549	6		T672	2		T528	2
values[50]	40	1			T549	4		T672	1		T528	3
values[51]	47	1			T549	5		T672	3		T528	3
values[52]	38	1			T549	1		T672	1		T528	2
values[53]	46	1			T549	3		T672	3		T528	5
values[54]	46	1			T549	4		T672	4		T528	3
values[55]	49	1			T549	2		T672	6		T528	1
values[56]	42	1			T549	1		T672	1		T528	6
values[57]	44	1			T549	5		T672	2		T528	2
values[58]	47	1			T549	4		T672	2		T528	4
values[59]	42	1			T549	3		T672	2		T528	1
values[60]	43	1			T549	1		T672	2		T528	3
values[61]	59	1			T549	3		T672	3		T528	8
values[62]	46	1			T549	4		T672	5		T528	5
values[63]	51	1			T549	2		T672	2		T528	1
values[64]	48	1			T549	2		T672	1		T528	1
values[65]	38	1			T549	3		T672	1		T528	2
values[66]	48	1			T549	6		T672	3		T528	4
values[67]	48	1			T549	5		T672	2		T528	3
values[68]	50	1			T549	2		T672	3		T528	3
values[69]	55	1			T549	2		T672	6		T528	1
values[70]	36	1			T549	1		T672	2		T528	1
values[71]	46	1			T549	1		T672	3		T528	4
values[72]	50	1			T549	3		T672	3		T528	1
values[73]	49	1			T549	5		T672	1		T528	1
values[74]	46	1			T549	3		T672	1		T528	6
values[75]	64	1			T549	2		T672	5		T528	11
values[76]	44	1			T549	1		T672	3		T528	3
values[77]	46	1			T549	4		T672	5		T528	3
values[78]	41	1			T549	2		T672	1		T528	3
values[79]	46	1			T549	1		T672	1		T528	2
values[80]	52	1			T549	5		T672	2		T528	1
values[81]	57	1			T549	7		T672	4		T528	1
values[82]	55	1			T549	3		T672	2		T528	1
values[83]	61	1			T549	4		T672	2		T528	1
values[84]	61	1			T549	2		T672	3		T528	2
values[85]	51	1			T549	2		T672	3		T528	2
values[86]	51	1			T549	1		T672	1		T528	1
values[87]	50	1			T549	3		T672	4		T528	2
values[88]	51	1			T549	1		T672	2		T528	2
values[89]	70	1			T549	1		T672	4		T528	2
values[90]	49	1			T549	2		T672	1		T528	1
values[91]	67	1			T549	2		T672	5		T528	3
values[92]	65	1			T549	1		T672	1		T528	2
values[93]	66	1			T549	1		T672	1		T528	2
values[94]	63	1			T549	1		T672	4		T528	1
values[95]	69	1			T549	4		T672	1		T528	2
values[96]	43	1			T549	1		T672	2		T528	1
values[97]	62	1			T549	3		T672	2		T528	7
values[98]	75	1			T549	1		T672	3		T528	8
values[99]	74	1			T549	2		T672	2		T528	3
values[100]	71	1			T549	5		T672	2		T528	2
values[101]	60	1			T549	1		T672	1		T528	1
values[102]	64	1			T549	3		T672	4		T528	2
values[103]	59	1			T549	3		T672	1		T528	1
values[104]	77	1			T549	3		T672	5		T528	2
values[105]	74	1			T549	7		T672	1		T528	1
values[106]	63	1			T549	3		T672	4		T528	7
values[107]	78	1			T549	11		T672	7		T528	3
values[108]	74	1			T549	5		T672	5		T528	1
values[109]	66	1			T549	2		T672	5		T528	3
values[110]	72	1			T549	4		T672	3		T528	2
values[111]	77	1			T549	2		T672	3		T528	1
values[112]	89	1			T549	4		T672	8		T528	2
values[113]	94	1			T549	4		T672	5		T528	4
values[114]	84	1			T549	1		T672	6		T528	3
values[115]	85	1			T549	3		T672	4		T528	3
values[116]	75	1			T549	2		T672	1		T528	3
values[117]	72	1			T549	5		T672	1		T528	2
values[118]	93	1			T549	8		T672	4		T528	4
values[119]	90	1			T549	6		T672	5		T528	8
values[120]	74	1			T549	10		T672	2		T528	13
values[121]	71	1			T549	9		T672	3		T528	8
values[122]	79	1			T549	9		T672	6		T528	2
values[123]	103	1			T549	21		T672	14		T528	3
values[124]	197	1			T549	20		T672	42		T528	9
values[125]	395	1			T549	20		T672	53		T528	49
values[126]	708	1			T549	31		T672	62		T528	78
values[127]	1972	1			T549	18		T672	23		T528	33
values[128]	3110	1			T549	2		T672	2		T528	2