Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.14	95.44	93.98	95.48		94.84	97.57	99.55

Total tests in report: 2923

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.22	40.22	45.10	45.10	46.69	46.69	27.54	27.54			63.25	63.25	58.59	58.59	0.14	0.14	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.63477141
47.76	7.54	49.73	4.63	56.98	10.29	27.90	0.36			69.57	6.32	81.27	22.68	1.09	0.95	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3081850137
53.07	5.31	60.90	11.17	64.62	7.63	30.88	2.98			79.63	10.07	81.27	0.00	1.09	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.4060820438
57.23	4.16	70.09	9.19	65.56	0.95	37.86	6.98			79.81	0.17	81.27	0.00	8.79	7.70	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.382495979
60.82	3.59	70.09	0.00	65.56	0.00	37.86	0.00			79.81	0.00	81.27	0.00	30.34	21.55	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.4205307275
64.39	3.57	76.08	5.99	69.37	3.81	45.30	7.44			82.01	2.21	82.99	1.72	30.57	0.23	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1787205121
67.43	3.05	80.98	4.90	73.13	3.76	48.77	3.47			83.70	1.69	87.46	4.47	30.57	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1966673151
69.91	2.48	80.98	0.00	73.13	0.00	48.77	0.00			83.70	0.00	87.46	0.00	45.45	14.87	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3057422132
72.35	2.44	80.98	0.00	73.13	0.00	63.41	14.64			83.70	0.00	87.46	0.00	45.45	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3232945132
74.55	2.20	82.33	1.35	75.62	2.49	68.64	5.23			85.42	1.72	87.63	0.17	47.69	2.24	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.989457930
76.17	1.62	82.33	0.00	75.63	0.01	68.64	0.00			85.42	0.00	87.63	0.00	57.37	9.68	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.1243788675
77.55	1.38	84.75	2.42	77.61	1.98	69.79	1.15			88.15	2.73	87.63	0.00	57.37	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.117965495
78.89	1.34	84.87	0.12	77.71	0.10	77.25	7.46			88.32	0.17	87.80	0.17	57.37	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.4028808053
80.19	1.30	86.23	1.36	78.87	1.16	77.58	0.33			89.66	1.34	91.41	3.61	57.37	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1526045063
81.45	1.26	86.49	0.26	81.51	2.64	78.34	0.76			89.87	0.22	91.41	0.00	61.06	3.69	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1939247171
82.60	1.15	88.50	2.01	82.76	1.25	80.39	2.05			90.80	0.92	92.10	0.69	61.06	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.322581453
83.72	1.12	88.50	0.00	82.76	0.00	80.39	0.00			90.80	0.00	92.10	0.00	67.79	6.73	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2342741564
84.69	0.97	88.50	0.00	83.21	0.45	80.39	0.00			90.86	0.06	92.10	0.00	73.11	5.31	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1742485520
85.64	0.95	88.50	0.00	83.21	0.00	80.39	0.00			90.86	0.00	92.10	0.00	78.80	5.70	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2344228232
86.50	0.85	89.23	0.73	83.52	0.31	80.40	0.01			91.16	0.29	95.88	3.78	78.80	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3744860836
87.24	0.74	90.41	1.17	84.22	0.70	81.89	1.49			91.75	0.59	96.39	0.52	78.80	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.901979968
87.88	0.64	90.41	0.00	84.28	0.06	81.89	0.00			91.75	0.00	96.39	0.00	82.58	3.77	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2322218649
88.47	0.59	90.41	0.00	84.30	0.02	81.89	0.00			91.75	0.00	96.39	0.00	86.10	3.52	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1385321251
89.06	0.59	90.88	0.47	86.52	2.22	82.27	0.38			92.16	0.41	96.39	0.00	86.12	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.772511088
89.47	0.42	90.89	0.01	86.52	0.01	84.59	2.32			92.16	0.00	96.56	0.17	86.12	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.4048001179
89.87	0.39	90.89	0.00	86.79	0.27	84.59	0.00			92.16	0.00	96.56	0.00	88.22	2.09	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.788926254
90.25	0.38	92.12	1.23	87.30	0.51	84.68	0.09			92.60	0.44	96.56	0.00	88.22	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.385901733
90.59	0.34	92.12	0.00	87.30	0.00	84.68	0.00			92.60	0.00	96.56	0.00	90.27	2.06	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2081429921
90.92	0.33	92.12	0.00	87.38	0.07	84.68	0.00			92.60	0.00	96.56	0.00	92.20	1.93	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3951712292
91.25	0.33	92.12	0.00	87.38	0.00	86.63	1.95			92.60	0.00	96.56	0.00	92.20	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2692289165
91.53	0.29	92.26	0.13	87.93	0.55	87.05	0.42			93.18	0.58	96.56	0.00	92.23	0.04	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1478577856
91.81	0.28	92.72	0.46	88.39	0.47	87.34	0.29			93.64	0.46	96.56	0.00	92.23	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3137184389
92.07	0.25	93.29	0.57	88.65	0.25	87.86	0.52			93.80	0.16	96.56	0.00	92.23	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.663998796
92.32	0.25	93.29	0.00	88.68	0.03	87.86	0.00			93.80	0.00	96.56	0.00	93.71	1.48	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.283565714
92.55	0.23	93.71	0.42	88.86	0.18	88.53	0.67			93.91	0.11	96.56	0.00	93.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4113626266
92.77	0.22	93.72	0.01	89.78	0.93	88.53	0.00			93.91	0.00	96.56	0.00	94.11	0.40	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.170874681
92.99	0.22	93.77	0.06	89.79	0.01	89.77	1.25			93.91	0.01	96.56	0.00	94.11	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.4097770439
93.20	0.21	93.77	0.00	89.80	0.01	89.77	0.00			93.91	0.00	96.56	0.00	95.37	1.26	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2550504082
93.37	0.17	93.77	0.00	89.80	0.00	90.81	1.04			93.91	0.00	96.56	0.00	95.37	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1452797823
93.52	0.15	93.77	0.00	90.71	0.91	90.81	0.00			93.91	0.00	96.56	0.00	95.37	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.1123620256
93.68	0.15	93.77	0.00	90.71	0.00	90.81	0.00			93.91	0.00	96.56	0.00	96.28	0.90	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.1346535843
93.82	0.15	93.77	0.00	90.71	0.00	90.81	0.00			93.91	0.00	96.56	0.00	97.17	0.89	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1835510048
93.96	0.14	93.77	0.00	90.73	0.01	91.63	0.82			93.91	0.00	96.56	0.00	97.17	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3272175252
94.09	0.12	93.98	0.21	91.05	0.32	91.84	0.21			93.91	0.00	96.56	0.00	97.17	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2433615422
94.20	0.11	94.19	0.22	91.18	0.13	92.02	0.18			94.04	0.13	96.56	0.00	97.17	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.3817592951
94.29	0.10	94.19	0.00	91.18	0.00	92.60	0.58			94.04	0.00	96.56	0.00	97.17	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1303317139
94.38	0.09	94.19	0.00	91.22	0.04	92.60	0.00			94.04	0.00	96.56	0.00	97.67	0.51	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3496763125
94.47	0.08	94.20	0.01	91.30	0.08	92.92	0.32			94.14	0.10	96.56	0.00	97.67	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2172092302
94.54	0.08	94.22	0.02	91.50	0.20	92.94	0.02			94.37	0.23	96.56	0.00	97.67	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3803010805
94.61	0.06	94.25	0.03	91.52	0.02	93.06	0.13			94.39	0.02	96.74	0.17	97.69	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.694981659
94.67	0.06	94.25	0.00	91.89	0.37	93.06	0.00			94.39	0.00	96.74	0.00	97.69	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3502552777
94.73	0.06	94.25	0.00	91.90	0.01	93.42	0.36			94.39	0.00	96.74	0.00	97.69	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1355388643
94.78	0.05	94.25	0.00	91.90	0.00	93.74	0.31			94.39	0.00	96.74	0.00	97.69	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2325882743
94.83	0.05	94.37	0.12	91.95	0.05	93.85	0.11			94.42	0.02	96.74	0.00	97.69	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.3590728699
94.88	0.05	94.42	0.06	92.13	0.19	93.88	0.03			94.44	0.02	96.74	0.00	97.69	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2926140004
94.92	0.04	94.42	0.00	92.19	0.06	93.88	0.00			94.44	0.00	96.74	0.00	97.87	0.19	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.2351334023
94.96	0.04	94.42	0.00	92.30	0.11	93.88	0.00			94.57	0.13	96.74	0.00	97.87	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2055403041
95.00	0.04	94.43	0.01	92.32	0.01	93.88	0.00			94.60	0.02	96.91	0.17	97.89	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.3908824306
95.04	0.04	94.44	0.01	92.33	0.01	93.88	0.01			94.60	0.01	97.08	0.17	97.90	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.3459585668
95.07	0.04	94.44	0.00	92.33	0.00	94.10	0.22			94.60	0.00	97.08	0.00	97.90	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3420051991
95.11	0.04	94.44	0.01	92.34	0.01	94.11	0.01			94.61	0.01	97.25	0.17	97.91	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.833993446
95.15	0.04	94.45	0.01	92.35	0.01	94.11	0.00			94.62	0.01	97.42	0.17	97.92	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076099938
95.18	0.03	94.52	0.07	92.35	0.00	94.23	0.12			94.63	0.01	97.42	0.00	97.92	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2698237292
95.21	0.03	94.52	0.00	92.37	0.01	94.23	0.00			94.63	0.00	97.42	0.00	98.11	0.19	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2631106618
95.24	0.03	94.52	0.00	92.56	0.19	94.23	0.00			94.63	0.00	97.42	0.00	98.11	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.1728571096
95.28	0.03	94.52	0.00	92.60	0.04	94.23	0.00			94.65	0.02	97.42	0.00	98.24	0.13	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.160008438
95.31	0.03	94.54	0.02	92.61	0.01	94.37	0.14			94.65	0.01	97.42	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.3616981378
95.33	0.03	94.54	0.00	92.61	0.00	94.37	0.00			94.65	0.00	97.59	0.17	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.940325391
95.36	0.03	94.61	0.07	92.64	0.03	94.38	0.01			94.70	0.05	97.59	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.1141457985
95.38	0.02	94.61	0.00	92.67	0.03	94.49	0.11			94.70	0.00	97.59	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.960189788
95.41	0.02	94.64	0.02	92.76	0.09	94.52	0.03			94.70	0.00	97.59	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.3211175102
95.43	0.02	94.64	0.00	92.79	0.03	94.62	0.10			94.70	0.00	97.59	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2528632387
95.45	0.02	94.64	0.00	92.91	0.12	94.62	0.00			94.70	0.00	97.59	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.1921317599
95.47	0.02	94.64	0.00	92.91	0.01	94.73	0.11			94.70	0.00	97.59	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3645868443
95.49	0.02	94.64	0.00	92.91	0.00	94.73	0.00			94.70	0.00	97.59	0.00	98.36	0.12	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.552159743
95.51	0.02	94.69	0.05	92.96	0.05	94.73	0.00			94.72	0.02	97.59	0.00	98.36	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.75508744
95.53	0.02	94.69	0.00	93.03	0.07	94.73	0.00			94.72	0.00	97.59	0.00	98.39	0.04	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3636587253
95.54	0.02	94.69	0.01	93.05	0.02	94.82	0.08			94.72	0.00	97.59	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1041360213
95.56	0.01	94.72	0.03	93.08	0.03	94.83	0.01			94.73	0.01	97.59	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.2208316668
95.57	0.01	94.72	0.00	93.16	0.08	94.83	0.00			94.73	0.00	97.59	0.00	98.39	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1459340928
95.59	0.01	94.72	0.00	93.16	0.00	94.90	0.07			94.73	0.00	97.59	0.00	98.40	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2754030227
95.60	0.01	94.72	0.00	93.16	0.00	94.99	0.08			94.73	0.00	97.59	0.00	98.40	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2701857071
95.61	0.01	94.72	0.00	93.19	0.03	94.99	0.00			94.74	0.02	97.59	0.00	98.44	0.04	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1284666046
95.63	0.01	94.72	0.00	93.27	0.08	94.99	0.00			94.74	0.00	97.59	0.00	98.44	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.2141152835
95.64	0.01	94.73	0.01	93.32	0.05	94.99	0.00			94.76	0.02	97.59	0.00	98.44	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.3581879498
95.65	0.01	94.73	0.00	93.32	0.00	95.06	0.07			94.76	0.00	97.59	0.00	98.44	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2545881472
95.66	0.01	94.77	0.03	93.34	0.02	95.06	0.00			94.77	0.01	97.59	0.00	98.44	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.161736277
95.67	0.01	94.77	0.00	93.35	0.01	95.06	0.00			94.77	0.00	97.59	0.00	98.50	0.06	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.789762489
95.68	0.01	94.77	0.00	93.35	0.00	95.06	0.00			94.77	0.00	97.59	0.00	98.55	0.06	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3595073292
95.69	0.01	94.77	0.00	93.35	0.00	95.11	0.06			94.77	0.00	97.59	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.1966448514
95.70	0.01	94.77	0.00	93.40	0.05	95.11	0.00			94.77	0.00	97.59	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.3394187793
95.71	0.01	94.77	0.00	93.44	0.04	95.11	0.00			94.78	0.02	97.59	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.673932595
95.72	0.01	94.79	0.02	93.44	0.01	95.11	0.01			94.80	0.02	97.59	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.978424922
95.72	0.01	94.79	0.00	93.49	0.05	95.11	0.00			94.80	0.00	97.59	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.487584254
95.73	0.01	94.79	0.00	93.50	0.01	95.15	0.04			94.81	0.01	97.59	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.1011093153
95.74	0.01	94.79	0.00	93.50	0.01	95.19	0.04			94.81	0.00	97.59	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.576927496
95.75	0.01	94.79	0.00	93.54	0.04	95.19	0.00			94.81	0.00	97.59	0.00	98.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1428137907
95.75	0.01	94.79	0.00	93.54	0.00	95.20	0.01			94.81	0.00	97.59	0.00	98.59	0.04	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2189887450
95.76	0.01	94.80	0.01	93.56	0.02	95.21	0.01			94.82	0.01	97.59	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3690237558
95.77	0.01	94.80	0.00	93.57	0.01	95.21	0.00			94.82	0.00	97.59	0.00	98.61	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.701026626
95.77	0.01	94.80	0.00	93.60	0.02	95.21	0.00			94.82	0.00	97.59	0.00	98.63	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.57437758
95.78	0.01	94.80	0.00	93.62	0.02	95.22	0.01			94.82	0.00	97.59	0.00	98.63	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.2676722643
95.78	0.01	94.80	0.00	93.62	0.00	95.22	0.00			94.82	0.00	97.59	0.00	98.66	0.04	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3726496861
95.79	0.01	94.80	0.00	93.62	0.00	95.22	0.00			94.82	0.00	97.59	0.00	98.70	0.04	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.213546421
95.80	0.01	94.80	0.01	93.64	0.02	95.23	0.01			94.82	0.00	97.59	0.00	98.70	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.2646563790
95.80	0.01	94.80	0.00	93.64	0.00	95.26	0.03			94.82	0.00	97.59	0.00	98.70	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.583497264
95.81	0.01	94.80	0.00	93.67	0.03	95.26	0.01			94.82	0.00	97.59	0.00	98.70	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2853554190
95.81	0.01	94.80	0.00	93.67	0.00	95.28	0.02			94.82	0.00	97.59	0.00	98.71	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.574380530
95.82	0.01	94.80	0.00	93.70	0.03	95.28	0.00			94.82	0.00	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.4167713745
95.82	0.01	94.80	0.00	93.72	0.03	95.28	0.00			94.82	0.00	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2000931980
95.83	0.01	94.80	0.00	93.72	0.00	95.31	0.03			94.82	0.00	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2272961438
95.83	0.01	94.80	0.00	93.72	0.00	95.31	0.00			94.82	0.00	97.59	0.00	98.73	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.372121085
95.83	0.01	94.80	0.00	93.72	0.00	95.31	0.00			94.82	0.00	97.59	0.00	98.75	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2016592025
95.84	0.01	94.80	0.00	93.74	0.01	95.32	0.01			94.82	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1316309401
95.84	0.01	94.80	0.00	93.74	0.00	95.34	0.02			94.82	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2982850953
95.84	0.01	94.81	0.01	93.75	0.01	95.34	0.00			94.82	0.01	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.4071509662
95.85	0.01	94.81	0.00	93.77	0.02	95.34	0.00			94.82	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.2107982458
95.85	0.01	94.81	0.00	93.77	0.00	95.35	0.01			94.82	0.00	97.59	0.00	98.77	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2301776334
95.85	0.01	94.81	0.00	93.78	0.02	95.35	0.00			94.82	0.00	97.59	0.00	98.77	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.612830038
95.86	0.01	94.81	0.00	93.80	0.02	95.35	0.00			94.82	0.00	97.59	0.00	98.77	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.3334935344
95.86	0.01	94.81	0.00	93.80	0.00	95.36	0.01			94.82	0.00	97.59	0.00	98.78	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.1277032077
95.86	0.01	94.82	0.01	93.80	0.00	95.36	0.01			94.82	0.00	97.59	0.00	98.78	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3456419196
95.87	0.01	94.82	0.00	93.80	0.00	95.37	0.01			94.83	0.01	97.59	0.00	98.78	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1015212418
95.87	0.01	94.82	0.00	93.82	0.01	95.37	0.00			94.83	0.00	97.59	0.00	98.78	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.547101953
95.87	0.01	94.82	0.00	93.83	0.01	95.37	0.00			94.83	0.00	97.59	0.00	98.78	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1638405471
95.87	0.01	94.82	0.00	93.84	0.01	95.37	0.00			94.83	0.00	97.59	0.00	98.78	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.3844308834
95.88	0.01	94.82	0.00	93.84	0.00	95.37	0.01			94.83	0.00	97.59	0.00	98.79	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2047351673
95.88	0.01	94.82	0.00	93.84	0.00	95.37	0.01			94.83	0.00	97.59	0.00	98.80	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.1243703166
95.88	0.01	94.82	0.00	93.84	0.00	95.39	0.01			94.83	0.00	97.59	0.00	98.80	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.3952872129
95.88	0.01	94.82	0.00	93.84	0.00	95.40	0.01			94.83	0.00	97.59	0.00	98.80	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1527919740
95.88	0.01	94.82	0.01	93.85	0.01	95.40	0.01			94.83	0.00	97.59	0.00	98.80	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.1438662104
95.89	0.01	94.83	0.01	93.85	0.00	95.41	0.01			94.83	0.00	97.59	0.00	98.80	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1506699774
95.89	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.81	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2559481564
95.89	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.83	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.932717403
95.89	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.84	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3049446837
95.89	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.85	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.2879500668
95.90	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.86	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750606588
95.90	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.87	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.2218142320
95.90	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.88	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4121960563
95.90	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.90	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2288120092
95.90	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.91	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3530833637
95.91	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.92	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.98937668
95.91	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.93	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1842469662
95.91	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.94	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.4180481220
95.91	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.95	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017694820
95.91	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.97	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.1855143079
95.92	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.98	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3979033865
95.92	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	98.99	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3153470331
95.92	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.00	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3201583041
95.92	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.01	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626174679
95.92	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.02	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.3112104991
95.93	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.04	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1295760176
95.93	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.05	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2409093636
95.93	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.06	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3450344321
95.93	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.07	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1708870598
95.93	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.08	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4036494709
95.94	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.10	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.148072713
95.94	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.11	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.3750653851
95.94	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.12	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.3436967008
95.94	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.13	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.691356390
95.94	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.14	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1126024605
95.95	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.15	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2150604953
95.95	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.17	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2650925951
95.95	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.18	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2413397856
95.95	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.19	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1618977366
95.95	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.20	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.3335890446
95.96	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.21	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3127380906
95.96	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.22	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2200058308
95.96	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.24	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.352718133
95.96	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.25	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386670936
95.96	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.26	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1358757398
95.96	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.27	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1657081101
95.97	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.28	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3770845959
95.97	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.30	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.804591150
95.97	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.31	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2099097003
95.97	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.32	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1477991764
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95.98	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.34	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.139671458
95.98	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.35	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.3897115190
95.98	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.37	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2672609103
95.98	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.38	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.148731435
95.98	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.39	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1567019005
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95.99	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.41	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.956190191
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95.99	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.44	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363206843
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96.00	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.46	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604044984
96.00	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.47	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.701683494
96.00	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.48	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1075667308
96.00	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.49	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.471152993
96.00	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.51	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1370847770
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96.01	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.53	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4192933036
96.01	0.01	94.83	0.00	93.85	0.00	95.41	0.00			94.83	0.00	97.59	0.00	99.54	0.01	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.1923480856
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96.01	0.01	94.83	0.00	93.86	0.01	95.42	0.01			94.83	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.1990505425
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96.02	0.01	94.83	0.00	93.88	0.01	95.42	0.00			94.83	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3293993246
96.02	0.01	94.83	0.00	93.89	0.01	95.42	0.00			94.83	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1914038899
96.02	0.01	94.83	0.01	93.89	0.00	95.42	0.01			94.83	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.1746353281
96.02	0.01	94.83	0.00	93.90	0.01	95.43	0.01			94.83	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.4147234405
96.02	0.01	94.83	0.00	93.90	0.00	95.43	0.01			94.83	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.2554210140
96.03	0.01	94.83	0.00	93.90	0.00	95.43	0.00			94.84	0.01	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.3909600100
96.03	0.01	94.83	0.00	93.90	0.01	95.43	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4038183154
96.03	0.01	94.83	0.00	93.91	0.01	95.43	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.28873855
96.03	0.01	94.83	0.00	93.92	0.01	95.43	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.1202629876
96.03	0.01	94.83	0.00	93.93	0.01	95.43	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.507121713
96.03	0.01	94.83	0.00	93.93	0.01	95.43	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3138381700
96.03	0.01	94.83	0.00	93.94	0.01	95.43	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.1734844869
96.03	0.01	94.83	0.00	93.95	0.01	95.43	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.3603950230
96.03	0.01	94.83	0.00	93.95	0.01	95.43	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1421065729
96.04	0.01	94.83	0.00	93.95	0.00	95.44	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.4086503268
96.04	0.01	94.83	0.00	93.95	0.00	95.45	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.883935007
96.04	0.01	94.83	0.00	93.95	0.00	95.45	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.78460050
96.04	0.01	94.83	0.00	93.95	0.00	95.46	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1163823556
96.04	0.01	94.83	0.00	93.95	0.00	95.46	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2128832180
96.04	0.01	94.83	0.00	93.95	0.00	95.47	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2399537902
96.04	0.01	94.83	0.00	93.96	0.01	95.47	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.2899369860
96.04	0.01	94.83	0.00	93.96	0.01	95.47	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.1240652281
96.04	0.01	94.83	0.00	93.96	0.01	95.47	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.997323326
96.04	0.01	94.83	0.00	93.97	0.01	95.47	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3130768854
96.04	0.01	94.83	0.00	93.97	0.01	95.47	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.4278315723
96.04	0.01	94.83	0.00	93.98	0.01	95.47	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.1342061963
96.04	0.01	94.83	0.00	93.98	0.01	95.47	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.648062099
96.04	0.01	94.83	0.00	93.98	0.01	95.47	0.00			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.232456438
96.05	0.01	94.83	0.00	93.98	0.00	95.47	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.340025235
96.05	0.01	94.83	0.00	93.98	0.00	95.47	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.180879193
96.05	0.01	94.83	0.00	93.98	0.00	95.48	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2369196070
96.05	0.01	94.83	0.00	93.98	0.00	95.48	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4167565458
96.05	0.01	94.83	0.00	93.98	0.00	95.48	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.758166551
96.05	0.01	94.83	0.00	93.98	0.00	95.48	0.01			94.84	0.00	97.59	0.00	99.55	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.511577257

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2509025467
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.2656743511
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1879058808
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2160338104
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3005643287
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2185200285
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.84004255
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.4264217654
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3049700096
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2037084943
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3995463036
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.1544458945
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.1511102515
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.126729371
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2102255538
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3576587564
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2626323814
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.595604705
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2000634337
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1561057203
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2478141966
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2279730483
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.488495805
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3025447167
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.661772141
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.775016656
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3655622958
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1580066015
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2004179875
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.1970582742
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.3067777714
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2639863372
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.4028513091
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.4182618071
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.494128460
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1277996316
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2087069806
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3501564221
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.2109145883
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.62642930
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1831763087
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1245285058
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2596856221
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.95103612
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1291821313
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3725758996
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2054036916
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.53167184
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.644355513
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.4230615239
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3579296099
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.3618227390
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.269612100
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2963814735
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1707113992
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1943282247
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.257800613
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.4271625319
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.60852488
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4032583422
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2014115371
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.2122477752
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.699793687
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.3738447229
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.2675255108
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4089375424
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Total test records in report: 2923

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.785958054			Oct 03 04:06:14 PM UTC 24	Oct 03 04:08:19 PM UTC 24	3099784708 ps
T2	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.2756287531			Oct 03 04:06:17 PM UTC 24	Oct 03 04:09:26 PM UTC 24	2802623214 ps
T3	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.431894016			Oct 03 04:05:56 PM UTC 24	Oct 03 04:09:44 PM UTC 24	3540177640 ps
T4	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2904445226			Oct 03 04:06:17 PM UTC 24	Oct 03 04:10:25 PM UTC 24	2492745382 ps
T8	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.63477141			Oct 03 04:07:14 PM UTC 24	Oct 03 04:11:24 PM UTC 24	2336404605 ps
T102	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.643449959			Oct 03 04:07:57 PM UTC 24	Oct 03 04:11:40 PM UTC 24	2840382980 ps
T103	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.2740312155			Oct 03 04:07:05 PM UTC 24	Oct 03 04:11:41 PM UTC 24	2477651604 ps
T5	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.928445732			Oct 03 04:08:16 PM UTC 24	Oct 03 04:12:59 PM UTC 24	2849459064 ps
T6	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.901979968			Oct 03 04:08:01 PM UTC 24	Oct 03 04:13:29 PM UTC 24	3875027608 ps
T25	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.1011093153			Oct 03 04:05:47 PM UTC 24	Oct 03 04:13:49 PM UTC 24	6495777200 ps
T7	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2172092302			Oct 03 04:09:54 PM UTC 24	Oct 03 04:14:07 PM UTC 24	3042491885 ps
T32	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.1908575154			Oct 03 04:09:14 PM UTC 24	Oct 03 04:14:31 PM UTC 24	2979675088 ps
T46	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1787205121			Oct 03 04:05:28 PM UTC 24	Oct 03 04:14:50 PM UTC 24	6283119572 ps
T118	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1117488176			Oct 03 04:12:33 PM UTC 24	Oct 03 04:16:43 PM UTC 24	3125717496 ps
T119	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.3551456345			Oct 03 04:12:33 PM UTC 24	Oct 03 04:16:59 PM UTC 24	3253696082 ps
T30	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2528632387			Oct 03 04:08:10 PM UTC 24	Oct 03 04:17:02 PM UTC 24	4771922880 ps
T11	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.171198738			Oct 03 04:09:43 PM UTC 24	Oct 03 04:17:30 PM UTC 24	2827003100 ps
T9	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3690237558			Oct 03 04:07:25 PM UTC 24	Oct 03 04:18:04 PM UTC 24	4151099640 ps
T39	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.883935007			Oct 03 04:16:05 PM UTC 24	Oct 03 04:18:26 PM UTC 24	2767315000 ps
T28	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.2646563790			Oct 03 04:05:58 PM UTC 24	Oct 03 04:18:34 PM UTC 24	4252212780 ps
T29	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.663998796			Oct 03 04:11:26 PM UTC 24	Oct 03 04:18:45 PM UTC 24	4401244960 ps
T128	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.2676722643			Oct 03 04:06:34 PM UTC 24	Oct 03 04:18:46 PM UTC 24	4490364974 ps
T10	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.3616981378			Oct 03 04:07:29 PM UTC 24	Oct 03 04:18:58 PM UTC 24	3843616760 ps
T33	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.340039241			Oct 03 04:16:14 PM UTC 24	Oct 03 04:19:00 PM UTC 24	3247417769 ps
T34	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.440563365			Oct 03 04:16:13 PM UTC 24	Oct 03 04:19:06 PM UTC 24	3078804279 ps
T257	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3093942925			Oct 03 04:12:26 PM UTC 24	Oct 03 04:19:14 PM UTC 24	3220704600 ps
T47	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2754030227			Oct 03 04:08:07 PM UTC 24	Oct 03 04:19:14 PM UTC 24	4340462320 ps
T129	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.50511052			Oct 03 04:09:19 PM UTC 24	Oct 03 04:19:22 PM UTC 24	4784982537 ps
T81	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4172478105			Oct 03 04:17:47 PM UTC 24	Oct 03 04:19:35 PM UTC 24	2436243883 ps
T15	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.138170852			Oct 03 04:10:25 PM UTC 24	Oct 03 04:19:39 PM UTC 24	4021496379 ps
T41	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4141241931			Oct 03 04:16:11 PM UTC 24	Oct 03 04:20:05 PM UTC 24	3718137628 ps
T82	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3665524356			Oct 03 04:08:03 PM UTC 24	Oct 03 04:20:09 PM UTC 24	6096770664 ps
T12	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.3590728699			Oct 03 04:12:05 PM UTC 24	Oct 03 04:20:19 PM UTC 24	4548932949 ps
T187	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1966165413			Oct 03 04:15:34 PM UTC 24	Oct 03 04:20:25 PM UTC 24	2468689907 ps
T208	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3420051991			Oct 03 04:15:57 PM UTC 24	Oct 03 04:20:26 PM UTC 24	3364971254 ps
T197	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.244895908			Oct 03 04:17:47 PM UTC 24	Oct 03 04:20:35 PM UTC 24	2994767190 ps
T61	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2651921165			Oct 03 04:09:33 PM UTC 24	Oct 03 04:21:49 PM UTC 24	4715209320 ps
T146	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1105603593			Oct 03 04:11:45 PM UTC 24	Oct 03 04:22:22 PM UTC 24	4848080959 ps
T59	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.350873131			Oct 03 04:09:52 PM UTC 24	Oct 03 04:22:24 PM UTC 24	4897305850 ps
T188	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2618035195			Oct 03 04:13:00 PM UTC 24	Oct 03 04:22:29 PM UTC 24	4884780790 ps
T202	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2692289165			Oct 03 04:11:26 PM UTC 24	Oct 03 04:22:47 PM UTC 24	5259159304 ps
T130	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.1089101171			Oct 03 04:07:56 PM UTC 24	Oct 03 04:23:26 PM UTC 24	5220283480 ps
T62	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.84057116			Oct 03 04:10:05 PM UTC 24	Oct 03 04:24:14 PM UTC 24	4253214642 ps
T13	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3123099223			Oct 03 04:11:42 PM UTC 24	Oct 03 04:24:40 PM UTC 24	7220692576 ps
T330	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2853554190			Oct 03 04:11:24 PM UTC 24	Oct 03 04:24:55 PM UTC 24	4090712474 ps
T408	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.2493265726			Oct 03 04:21:18 PM UTC 24	Oct 03 04:25:25 PM UTC 24	3107088456 ps
T921	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_descrambling.333719619			Oct 03 04:16:05 PM UTC 24	Oct 03 04:26:21 PM UTC 24	3816846072 ps
T123	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.838393572			Oct 03 04:22:27 PM UTC 24	Oct 03 04:27:12 PM UTC 24	2583438656 ps
T38	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.3268132311			Oct 03 04:05:59 PM UTC 24	Oct 03 04:27:16 PM UTC 24	9141785800 ps
T191	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3272175252			Oct 03 04:16:06 PM UTC 24	Oct 03 04:28:20 PM UTC 24	4524012094 ps
T63	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3731148052			Oct 03 04:09:53 PM UTC 24	Oct 03 04:28:24 PM UTC 24	5308293468 ps
T225	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.2810098419			Oct 03 04:20:20 PM UTC 24	Oct 03 04:28:33 PM UTC 24	3877997096 ps
T329	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3575237128			Oct 03 04:23:14 PM UTC 24	Oct 03 04:29:02 PM UTC 24	3163422128 ps
T147	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1500149535			Oct 03 04:12:34 PM UTC 24	Oct 03 04:29:18 PM UTC 24	5432604402 ps
T31	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4194107467			Oct 03 04:22:44 PM UTC 24	Oct 03 04:29:20 PM UTC 24	2955283515 ps
T419	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2311153783			Oct 03 04:21:39 PM UTC 24	Oct 03 04:29:51 PM UTC 24	3751553257 ps
T268	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3058189542			Oct 03 04:21:52 PM UTC 24	Oct 03 04:30:22 PM UTC 24	4893393528 ps
T16	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1506699774			Oct 03 04:23:28 PM UTC 24	Oct 03 04:30:26 PM UTC 24	3252189876 ps
T163	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.574380530			Oct 03 04:21:36 PM UTC 24	Oct 03 04:30:28 PM UTC 24	8887366284 ps
T151	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1527919740			Oct 03 04:15:59 PM UTC 24	Oct 03 04:30:29 PM UTC 24	9350697549 ps
T148	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.348278883			Oct 03 04:11:53 PM UTC 24	Oct 03 04:30:35 PM UTC 24	5903099657 ps
T258	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.1990505425			Oct 03 04:24:05 PM UTC 24	Oct 03 04:30:38 PM UTC 24	4183357210 ps
T205	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.953130317			Oct 03 04:14:37 PM UTC 24	Oct 03 04:31:21 PM UTC 24	8768199700 ps
T206	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.790521412			Oct 03 04:14:35 PM UTC 24	Oct 03 04:32:32 PM UTC 24	8532918632 ps
T240	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3536769894			Oct 03 04:13:20 PM UTC 24	Oct 03 04:32:41 PM UTC 24	7643919250 ps
T155	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2399537902			Oct 03 04:21:45 PM UTC 24	Oct 03 04:32:42 PM UTC 24	6057625304 ps
T922	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.186332502			Oct 03 04:24:54 PM UTC 24	Oct 03 04:32:53 PM UTC 24	6754838120 ps
T705	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.4041585309			Oct 03 04:29:22 PM UTC 24	Oct 03 04:33:01 PM UTC 24	2702079168 ps
T68	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.48946418			Oct 03 04:22:10 PM UTC 24	Oct 03 04:33:21 PM UTC 24	8133434352 ps
T19	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3749910554			Oct 03 04:23:28 PM UTC 24	Oct 03 04:33:38 PM UTC 24	6188941976 ps
T706	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3363700027			Oct 03 04:29:22 PM UTC 24	Oct 03 04:33:45 PM UTC 24	2142434024 ps
T67	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2071409244			Oct 03 04:23:04 PM UTC 24	Oct 03 04:33:47 PM UTC 24	4540595083 ps
T923	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.2734915301			Oct 03 04:11:46 PM UTC 24	Oct 03 04:34:00 PM UTC 24	6134354888 ps
T239	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.694981659			Oct 03 04:20:35 PM UTC 24	Oct 03 04:34:15 PM UTC 24	7242723474 ps
T287	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3954302089			Oct 03 04:25:43 PM UTC 24	Oct 03 04:35:06 PM UTC 24	6015253688 ps
T139	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.576927496			Oct 03 04:26:06 PM UTC 24	Oct 03 04:35:09 PM UTC 24	18277089736 ps
T259	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4160777278			Oct 03 04:25:42 PM UTC 24	Oct 03 04:35:34 PM UTC 24	5253992858 ps
T288	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.2888431227			Oct 03 04:29:21 PM UTC 24	Oct 03 04:35:53 PM UTC 24	3134010553 ps
T289	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.3673004154			Oct 03 04:30:33 PM UTC 24	Oct 03 04:36:30 PM UTC 24	4256591490 ps
T20	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1201978282			Oct 03 04:08:46 PM UTC 24	Oct 03 04:36:41 PM UTC 24	8370492512 ps
T131	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1316309401			Oct 03 04:08:46 PM UTC 24	Oct 03 04:36:41 PM UTC 24	8106807684 ps
T215	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.2520189296			Oct 03 04:28:03 PM UTC 24	Oct 03 04:36:42 PM UTC 24	3731072822 ps
T290	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.2913586244			Oct 03 04:29:41 PM UTC 24	Oct 03 04:36:44 PM UTC 24	2562562782 ps
T99	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.482621900			Oct 03 04:32:31 PM UTC 24	Oct 03 04:37:00 PM UTC 24	2720062376 ps
T75	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.989457930			Oct 03 04:30:09 PM UTC 24	Oct 03 04:37:24 PM UTC 24	3138247240 ps
T399	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.930250443			Oct 03 04:32:30 PM UTC 24	Oct 03 04:37:37 PM UTC 24	3488023420 ps
T400	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1712495494			Oct 03 04:25:18 PM UTC 24	Oct 03 04:37:49 PM UTC 24	7158314200 ps
T137	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.275400629			Oct 03 04:22:42 PM UTC 24	Oct 03 04:38:28 PM UTC 24	7406395656 ps
T198	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.4028808053			Oct 03 04:17:23 PM UTC 24	Oct 03 04:38:40 PM UTC 24	8868000552 ps
T159	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.1477065814			Oct 03 04:34:39 PM UTC 24	Oct 03 04:39:06 PM UTC 24	3193736456 ps
T342	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2047351673			Oct 03 04:32:08 PM UTC 24	Oct 03 04:39:34 PM UTC 24	3775525788 ps
T401	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.1387574374			Oct 03 04:35:19 PM UTC 24	Oct 03 04:40:18 PM UTC 24	2017677720 ps
T402	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.648062099			Oct 03 04:28:38 PM UTC 24	Oct 03 04:40:33 PM UTC 24	5067521116 ps
T160	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2337157542			Oct 03 04:35:30 PM UTC 24	Oct 03 04:40:48 PM UTC 24	3218287792 ps
T161	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.3202508446			Oct 03 04:27:15 PM UTC 24	Oct 03 04:41:05 PM UTC 24	5767726022 ps
T224	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.1309392931			Oct 03 04:30:09 PM UTC 24	Oct 03 04:41:16 PM UTC 24	5687651140 ps
T708	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.4086503268			Oct 03 04:36:13 PM UTC 24	Oct 03 04:41:28 PM UTC 24	3210648536 ps
T331	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.4088746892			Oct 03 04:36:14 PM UTC 24	Oct 03 04:41:55 PM UTC 24	3196374874 ps
T332	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.280039236			Oct 03 04:36:14 PM UTC 24	Oct 03 04:42:16 PM UTC 24	3618700150 ps
T924	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.89377303			Oct 03 04:36:17 PM UTC 24	Oct 03 04:42:45 PM UTC 24	3271699508 ps
T462	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.4036866748			Oct 03 04:38:39 PM UTC 24	Oct 03 04:43:04 PM UTC 24	2381242362 ps
T423	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.3339402255			Oct 03 04:39:02 PM UTC 24	Oct 03 04:43:31 PM UTC 24	3183836960 ps
T156	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.3941312328			Oct 03 04:34:29 PM UTC 24	Oct 03 04:44:08 PM UTC 24	3083743456 ps
T463	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.3285489140			Oct 03 04:39:14 PM UTC 24	Oct 03 04:44:10 PM UTC 24	3147192504 ps
T925	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3039882398			Oct 03 04:38:51 PM UTC 24	Oct 03 04:44:16 PM UTC 24	3195187443 ps
T707	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3791710672			Oct 03 04:21:25 PM UTC 24	Oct 03 04:44:34 PM UTC 24	9242754974 ps
T179	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.3897942230			Oct 03 04:42:02 PM UTC 24	Oct 03 04:45:28 PM UTC 24	2816932394 ps
T216	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2521900556			Oct 03 04:35:22 PM UTC 24	Oct 03 04:45:39 PM UTC 24	4098732184 ps
T926	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.1702728567			Oct 03 04:38:48 PM UTC 24	Oct 03 04:46:00 PM UTC 24	2852150742 ps
T157	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.180879193			Oct 03 04:35:19 PM UTC 24	Oct 03 04:46:15 PM UTC 24	3093256394 ps
T203	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.3816341426			Oct 03 04:12:15 PM UTC 24	Oct 03 04:46:44 PM UTC 24	19073747440 ps
T343	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2138187810			Oct 03 04:21:33 PM UTC 24	Oct 03 04:47:22 PM UTC 24	8916725065 ps
T158	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2325882743			Oct 03 04:35:27 PM UTC 24	Oct 03 04:47:42 PM UTC 24	5165728920 ps
T267	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.3123556099			Oct 03 04:28:04 PM UTC 24	Oct 03 04:48:29 PM UTC 24	5121616504 ps
T292	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2066323242			Oct 03 04:39:18 PM UTC 24	Oct 03 04:48:55 PM UTC 24	9469972333 ps
T275	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3456419196			Oct 03 04:45:18 PM UTC 24	Oct 03 04:49:35 PM UTC 24	3173555800 ps
T192	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.2208316668			Oct 03 04:22:37 PM UTC 24	Oct 03 04:49:36 PM UTC 24	12024591682 ps
T164	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2433615422			Oct 03 04:42:06 PM UTC 24	Oct 03 04:49:51 PM UTC 24	4571654206 ps
T100	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4113626266			Oct 03 04:32:13 PM UTC 24	Oct 03 04:51:15 PM UTC 24	11223650920 ps
T210	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4054294068			Oct 03 04:41:26 PM UTC 24	Oct 03 04:51:40 PM UTC 24	8303230628 ps
T17	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.3817592951			Oct 03 04:23:32 PM UTC 24	Oct 03 04:51:58 PM UTC 24	23006426108 ps
T209	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.198688331			Oct 03 04:39:45 PM UTC 24	Oct 03 04:52:01 PM UTC 24	3815056386 ps
T124	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3137184389			Oct 03 04:43:44 PM UTC 24	Oct 03 04:52:22 PM UTC 24	3854433064 ps
T211	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2369196070			Oct 03 04:40:56 PM UTC 24	Oct 03 04:53:20 PM UTC 24	6122628469 ps
T323	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2337764233			Oct 03 04:45:21 PM UTC 24	Oct 03 04:53:24 PM UTC 24	4376492276 ps
T149	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.960189788			Oct 03 04:40:15 PM UTC 24	Oct 03 04:54:08 PM UTC 24	5319735533 ps
T238	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.784920922			Oct 03 04:22:13 PM UTC 24	Oct 03 04:54:17 PM UTC 24	16318189870 ps
T256	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.3324720121			Oct 03 04:35:30 PM UTC 24	Oct 03 04:54:22 PM UTC 24	6114104606 ps
T324	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3021198448			Oct 03 04:46:05 PM UTC 24	Oct 03 04:54:34 PM UTC 24	3699806124 ps
T325	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.286379713			Oct 03 04:50:37 PM UTC 24	Oct 03 04:54:34 PM UTC 24	2485889040 ps
T242	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.2663426210			Oct 03 04:38:05 PM UTC 24	Oct 03 04:54:38 PM UTC 24	5908350470 ps
T326	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1352258860			Oct 03 04:45:18 PM UTC 24	Oct 03 04:54:50 PM UTC 24	5032427320 ps
T279	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.4048001179			Oct 03 04:34:38 PM UTC 24	Oct 03 04:55:29 PM UTC 24	4890325474 ps
T143	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3747833076			Oct 03 04:35:25 PM UTC 24	Oct 03 04:56:06 PM UTC 24	7197070341 ps
T328	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.117965495			Oct 03 04:44:08 PM UTC 24	Oct 03 04:56:10 PM UTC 24	4977927924 ps
T152	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2545881472			Oct 03 04:48:01 PM UTC 24	Oct 03 04:57:11 PM UTC 24	3844136892 ps
T217	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.961710004			Oct 03 04:46:48 PM UTC 24	Oct 03 04:57:11 PM UTC 24	5895540508 ps
T927	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.157476809			Oct 03 04:41:11 PM UTC 24	Oct 03 04:58:03 PM UTC 24	9165594780 ps
T734	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.338725803			Oct 03 04:50:33 PM UTC 24	Oct 03 04:58:13 PM UTC 24	3033253874 ps
T360	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4017811382			Oct 03 04:32:11 PM UTC 24	Oct 03 04:58:30 PM UTC 24	7031468384 ps
T928	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.887519185			Oct 03 04:46:19 PM UTC 24	Oct 03 04:58:37 PM UTC 24	5404640020 ps
T35	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.26387985			Oct 03 06:04:47 PM UTC 24	Oct 03 06:09:25 PM UTC 24	5819962732 ps
T929	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4136588522			Oct 03 04:50:34 PM UTC 24	Oct 03 04:59:00 PM UTC 24	3408115996 ps
T346	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.4147234405			Oct 03 04:35:29 PM UTC 24	Oct 03 04:59:27 PM UTC 24	6581099252 ps
T153	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3434803503			Oct 03 04:48:21 PM UTC 24	Oct 03 04:59:29 PM UTC 24	5282085968 ps
T699	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.3560428097			Oct 03 04:32:15 PM UTC 24	Oct 03 04:59:36 PM UTC 24	8162891366 ps
T154	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1396006517			Oct 03 04:47:22 PM UTC 24	Oct 03 05:00:17 PM UTC 24	4463992964 ps
T930	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.544125191			Oct 03 04:49:36 PM UTC 24	Oct 03 05:00:19 PM UTC 24	4587875344 ps
T241	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3232945132			Oct 03 04:38:59 PM UTC 24	Oct 03 05:00:35 PM UTC 24	6039875500 ps
T931	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2337666633			Oct 03 04:46:52 PM UTC 24	Oct 03 05:00:49 PM UTC 24	4165903432 ps
T66	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.1461389452			Oct 03 04:08:04 PM UTC 24	Oct 03 05:00:59 PM UTC 24	12906702600 ps
T932	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1980579334			Oct 03 04:49:09 PM UTC 24	Oct 03 05:01:12 PM UTC 24	4167965988 ps
T73	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1526045063			Oct 03 04:54:10 PM UTC 24	Oct 03 05:02:28 PM UTC 24	7625148506 ps
T85	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3878569203			Oct 03 04:56:11 PM UTC 24	Oct 03 05:02:57 PM UTC 24	6159563748 ps
T361	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.4161480097			Oct 03 04:54:10 PM UTC 24	Oct 03 05:03:23 PM UTC 24	3524339424 ps
T165	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1359028698			Oct 03 04:55:53 PM UTC 24	Oct 03 05:03:34 PM UTC 24	5630215040 ps
T212	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3744860836			Oct 03 04:58:48 PM UTC 24	Oct 03 05:03:55 PM UTC 24	3105869960 ps
T317	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3293993246			Oct 03 04:56:12 PM UTC 24	Oct 03 05:04:02 PM UTC 24	5897288468 ps
T199	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1163823556			Oct 03 04:53:00 PM UTC 24	Oct 03 05:04:09 PM UTC 24	5014472910 ps
T318	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3373149442			Oct 03 04:51:54 PM UTC 24	Oct 03 05:04:26 PM UTC 24	4708029550 ps
T319	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.2064574157			Oct 03 04:59:18 PM UTC 24	Oct 03 05:04:30 PM UTC 24	2605397174 ps
T207	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1452797823			Oct 03 04:18:45 PM UTC 24	Oct 03 05:04:45 PM UTC 24	26825216467 ps
T213	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.225211182			Oct 03 04:59:17 PM UTC 24	Oct 03 05:04:46 PM UTC 24	3094979730 ps
T320	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3009892032			Oct 03 05:00:31 PM UTC 24	Oct 03 05:04:47 PM UTC 24	2883891152 ps
T86	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.4071509662			Oct 03 04:55:56 PM UTC 24	Oct 03 05:05:01 PM UTC 24	5340982224 ps
T166	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.1141457985			Oct 03 04:41:51 PM UTC 24	Oct 03 05:05:30 PM UTC 24	8982151392 ps
T87	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1015212418			Oct 03 04:56:12 PM UTC 24	Oct 03 05:05:31 PM UTC 24	5711537233 ps
T333	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.3855269497			Oct 03 04:45:18 PM UTC 24	Oct 03 05:06:06 PM UTC 24	8147940180 ps
T94	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3645868443			Oct 03 04:56:06 PM UTC 24	Oct 03 05:06:24 PM UTC 24	5023599880 ps
T345	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.4285772552			Oct 03 05:01:43 PM UTC 24	Oct 03 05:06:26 PM UTC 24	2947955998 ps
T338	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.4060820438			Oct 03 04:43:28 PM UTC 24	Oct 03 05:07:18 PM UTC 24	5975196094 ps
T236	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.99138535			Oct 03 04:32:09 PM UTC 24	Oct 03 05:07:23 PM UTC 24	8351320762 ps
T453	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.991226853			Oct 03 05:02:01 PM UTC 24	Oct 03 05:07:31 PM UTC 24	3579605031 ps
T454	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.1659346606			Oct 03 05:00:31 PM UTC 24	Oct 03 05:08:02 PM UTC 24	3212421328 ps
T933	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3354449490			Oct 03 05:01:45 PM UTC 24	Oct 03 05:08:04 PM UTC 24	3024435991 ps
T735	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.4101038874			Oct 03 04:52:41 PM UTC 24	Oct 03 05:08:06 PM UTC 24	7502667962 ps
T934	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.3144863591			Oct 03 04:36:32 PM UTC 24	Oct 03 05:08:21 PM UTC 24	8174637630 ps
T935	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.886921269			Oct 03 04:59:42 PM UTC 24	Oct 03 05:08:39 PM UTC 24	4976887400 ps
T936	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.739135200			Oct 03 04:22:36 PM UTC 24	Oct 03 05:08:40 PM UTC 24	22058513402 ps
T42	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.1746294663			Oct 03 04:07:03 PM UTC 24	Oct 03 05:09:01 PM UTC 24	12200359474 ps
T370	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4144144635			Oct 03 05:00:31 PM UTC 24	Oct 03 05:11:46 PM UTC 24	4857307636 ps
T422	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.1672975118			Oct 03 05:08:23 PM UTC 24	Oct 03 05:11:58 PM UTC 24	2229982648 ps
T150	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1930352343			Oct 03 05:03:09 PM UTC 24	Oct 03 05:13:18 PM UTC 24	4731572353 ps
T937	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.1263639929			Oct 03 04:35:16 PM UTC 24	Oct 03 05:14:07 PM UTC 24	8867857720 ps
T69	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.2280094201			Oct 03 05:06:37 PM UTC 24	Oct 03 05:15:02 PM UTC 24	4854648080 ps
T243	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.4227473094			Oct 03 04:38:59 PM UTC 24	Oct 03 05:15:58 PM UTC 24	11388234028 ps
T36	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.3909600100			Oct 03 04:56:44 PM UTC 24	Oct 03 05:16:42 PM UTC 24	13285453411 ps
T136	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.3912600136			Oct 03 05:07:11 PM UTC 24	Oct 03 05:16:57 PM UTC 24	4189531504 ps
T37	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2698237292			Oct 03 04:56:44 PM UTC 24	Oct 03 05:17:36 PM UTC 24	8716389094 ps
T144	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.4185100996			Oct 03 04:38:37 PM UTC 24	Oct 03 05:18:49 PM UTC 24	10748570204 ps
T938	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.618765596			Oct 03 05:01:56 PM UTC 24	Oct 03 05:19:13 PM UTC 24	7479886672 ps
T18	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2543862906			Oct 03 04:23:32 PM UTC 24	Oct 03 05:22:09 PM UTC 24	21037831384 ps
T244	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.432511086			Oct 03 04:38:51 PM UTC 24	Oct 03 05:22:55 PM UTC 24	11573746664 ps
T74	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1531832148			Oct 03 04:55:34 PM UTC 24	Oct 03 05:23:02 PM UTC 24	24177429714 ps
T90	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1319126554			Oct 03 04:55:54 PM UTC 24	Oct 03 05:23:54 PM UTC 24	22474964680 ps
T88	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.957951978			Oct 03 04:57:46 PM UTC 24	Oct 03 05:24:57 PM UTC 24	18791587702 ps
T280	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2012049506			Oct 03 04:34:52 PM UTC 24	Oct 03 05:30:22 PM UTC 24	12429372472 ps
T421	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.3733491630			Oct 03 04:07:58 PM UTC 24	Oct 03 05:31:20 PM UTC 24	18798411670 ps
T939	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.719538961			Oct 03 04:42:56 PM UTC 24	Oct 03 05:33:14 PM UTC 24	26406330860 ps
T940	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3494441290			Oct 03 05:08:36 PM UTC 24	Oct 03 05:33:33 PM UTC 24	5432709776 ps
T40	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.4097770439			Oct 03 04:52:23 PM UTC 24	Oct 03 05:35:38 PM UTC 24	23042404640 ps
T14	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.322581453			Oct 03 05:09:42 PM UTC 24	Oct 03 05:40:33 PM UTC 24	5756691964 ps
T95	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2871488263			Oct 03 04:52:05 PM UTC 24	Oct 03 05:40:40 PM UTC 24	19543020470 ps
T941	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.2578385186			Oct 03 04:57:47 PM UTC 24	Oct 03 05:40:53 PM UTC 24	24939898590 ps
T182	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2832414065			Oct 03 04:27:15 PM UTC 24	Oct 03 05:42:53 PM UTC 24	17060295468 ps
T204	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.3792010473			Oct 03 05:03:30 PM UTC 24	Oct 03 05:45:56 PM UTC 24	20087891570 ps
T145	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2619041751			Oct 03 05:01:58 PM UTC 24	Oct 03 05:51:04 PM UTC 24	12581105520 ps
T247	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.78460050			Oct 03 04:38:46 PM UTC 24	Oct 03 06:00:41 PM UTC 24	13638608966 ps
T252	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.3836240235			Oct 03 04:16:09 PM UTC 24	Oct 03 06:02:19 PM UTC 24	51546789076 ps
T183	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.382249389			Oct 03 04:27:48 PM UTC 24	Oct 03 06:04:07 PM UTC 24	19055947847 ps
T291	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.3856199883			Oct 03 06:02:58 PM UTC 24	Oct 03 06:04:52 PM UTC 24	2144447476 ps
T55	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1355388643			Oct 03 05:14:50 PM UTC 24	Oct 03 06:05:44 PM UTC 24	11538279300 ps
T56	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3699765364			Oct 03 05:18:20 PM UTC 24	Oct 03 06:09:56 PM UTC 24	11608557272 ps
T58	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.401518351			Oct 03 05:09:27 PM UTC 24	Oct 03 06:15:05 PM UTC 24	11981366390 ps
T942	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.3089123289			Oct 03 06:10:05 PM UTC 24	Oct 03 06:15:11 PM UTC 24	2695397494 ps
T943	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.1395569961			Oct 03 06:10:34 PM UTC 24	Oct 03 06:16:32 PM UTC 24	3830725792 ps
T944	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.136978102			Oct 03 06:14:09 PM UTC 24	Oct 03 06:17:58 PM UTC 24	3359508210 ps
T945	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.785310194			Oct 03 06:06:24 PM UTC 24	Oct 03 06:18:36 PM UTC 24	4150808144 ps
T946	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.2844702635			Oct 03 06:15:56 PM UTC 24	Oct 03 06:19:22 PM UTC 24	2314854204 ps
T57	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1994325088			Oct 03 05:15:49 PM UTC 24	Oct 03 06:20:07 PM UTC 24	15044950680 ps
T471	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1900527861			Oct 03 05:17:42 PM UTC 24	Oct 03 06:20:31 PM UTC 24	14353378824 ps
T412	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.2630565563			Oct 03 05:08:46 PM UTC 24	Oct 03 06:20:53 PM UTC 24	15040831135 ps
T140	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.3952872129			Oct 03 05:06:51 PM UTC 24	Oct 03 06:21:40 PM UTC 24	21554807394 ps
T43	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.3338658553			Oct 03 06:17:11 PM UTC 24	Oct 03 06:21:46 PM UTC 24	2982312129 ps
T947	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.319416816			Oct 03 05:13:04 PM UTC 24	Oct 03 06:23:15 PM UTC 24	11518786310 ps
T384	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.385901733			Oct 03 05:08:51 PM UTC 24	Oct 03 06:23:21 PM UTC 24	15406309760 ps
T948	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.3181901643			Oct 03 06:19:16 PM UTC 24	Oct 03 06:25:48 PM UTC 24	3062165856 ps
T335	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.2145729184			Oct 03 06:21:34 PM UTC 24	Oct 03 06:26:00 PM UTC 24	3384947960 ps
T949	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.3539715169			Oct 03 06:15:56 PM UTC 24	Oct 03 06:26:18 PM UTC 24	3422251696 ps
T950	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.278273578			Oct 03 06:20:47 PM UTC 24	Oct 03 06:26:18 PM UTC 24	3252600334 ps
T951	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.1621878368			Oct 03 06:18:37 PM UTC 24	Oct 03 06:26:25 PM UTC 24	3180996132 ps
T952	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.3907351598			Oct 03 06:22:28 PM UTC 24	Oct 03 06:26:35 PM UTC 24	2742371986 ps
T125	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.4211778646			Oct 03 06:22:28 PM UTC 24	Oct 03 06:26:41 PM UTC 24	2807006732 ps
T253	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2701857071			Oct 03 04:16:04 PM UTC 24	Oct 03 06:28:02 PM UTC 24	48854099414 ps
T953	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.2295391740			Oct 03 06:24:06 PM UTC 24	Oct 03 06:28:35 PM UTC 24	2980696700 ps
T954	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2520093428			Oct 03 05:16:34 PM UTC 24	Oct 03 06:29:13 PM UTC 24	14785871101 ps
T251	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.1401042734			Oct 03 04:18:10 PM UTC 24	Oct 03 06:29:17 PM UTC 24	46909214668 ps
T420	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2081873144			Oct 03 06:21:20 PM UTC 24	Oct 03 06:29:18 PM UTC 24	6227972130 ps
T955	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.2780948299			Oct 03 06:24:07 PM UTC 24	Oct 03 06:29:18 PM UTC 24	2245002950 ps
T956	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.2586191329			Oct 03 06:26:32 PM UTC 24	Oct 03 06:29:58 PM UTC 24	2662665326 ps
T957	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3461723891			Oct 03 05:12:23 PM UTC 24	Oct 03 06:30:19 PM UTC 24	15263854796 ps
T958	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.699353184			Oct 03 05:19:55 PM UTC 24	Oct 03 06:30:42 PM UTC 24	14719412695 ps
T959	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.2625610804			Oct 03 06:21:20 PM UTC 24	Oct 03 06:31:26 PM UTC 24	5052789040 ps
T960	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3623874070			Oct 03 05:12:28 PM UTC 24	Oct 03 06:32:14 PM UTC 24	15827472772 ps
T961	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.4203781098			Oct 03 05:17:28 PM UTC 24	Oct 03 06:32:16 PM UTC 24	14711842960 ps
T962	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.3742614407			Oct 03 06:26:32 PM UTC 24	Oct 03 06:32:20 PM UTC 24	3004785232 ps
T963	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.3591120386			Oct 03 06:27:40 PM UTC 24	Oct 03 06:32:41 PM UTC 24	2751393704 ps
T964	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.100317916			Oct 03 06:27:43 PM UTC 24	Oct 03 06:32:54 PM UTC 24	3336515944 ps
T381	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.3419096324			Oct 03 05:06:53 PM UTC 24	Oct 03 06:33:22 PM UTC 24	27304630592 ps
T965	/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.2360845188			Oct 03 06:27:32 PM UTC 24	Oct 03 06:33:24 PM UTC 24	3292618164 ps