Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145489	1			T91	4		T92	4		T97	22
values[2]	9844	1			T272	2		T468	4		T470	1
values[3]	3842	1			T485	24		T835	96		T682	60
values[4]	2256	1			T485	15		T835	66		T682	39
values[5]	1407	1			T485	9		T835	40		T682	22
values[6]	900	1			T485	12		T835	30		T682	16
values[7]	590	1			T485	12		T835	29		T682	7
values[8]	442	1			T485	3		T835	18		T682	2
values[9]	381	1			T485	9		T835	7		T880	8
values[10]	371	1			T485	1		T835	16		T880	11
values[11]	347	1			T835	9		T880	5		T696	11
values[12]	347	1			T835	30		T880	3		T696	3
values[13]	357	1			T835	5		T880	5		T696	6
values[14]	336	1			T880	15		T696	7		T500	4
values[15]	314	1			T880	6		T696	3		T500	11
values[16]	289	1			T880	3		T696	8		T500	11
values[17]	289	1			T880	6		T696	6		T500	13
values[18]	264	1			T880	8		T696	15		T500	11
values[19]	251	1			T880	3		T696	12		T500	10
values[20]	305	1			T880	5		T696	2		T500	5
values[21]	309	1			T880	5		T696	4		T500	5
values[22]	242	1			T880	6		T696	7		T500	5
values[23]	269	1			T880	11		T696	8		T500	4
values[24]	289	1			T880	6		T696	5		T500	8
values[25]	333	1			T880	12		T696	7		T500	3
values[26]	259	1			T880	17		T696	5		T500	3
values[27]	270	1			T880	7		T696	7		T500	5
values[28]	249	1			T880	8		T696	5		T500	5
values[29]	279	1			T880	4		T696	8		T500	16
values[30]	278	1			T880	6		T696	4		T500	18
values[31]	257	1			T880	3		T696	5		T500	12
values[32]	310	1			T880	7		T696	8		T500	9
values[33]	260	1			T880	12		T696	5		T500	12
values[34]	223	1			T880	8		T696	7		T500	4
values[35]	227	1			T880	5		T696	5		T500	2
values[36]	215	1			T880	13		T696	5		T871	5
values[37]	262	1			T880	3		T696	8		T871	13
values[38]	309	1			T880	7		T696	15		T871	10
values[39]	233	1			T880	7		T696	4		T502	4
values[40]	213	1			T880	3		T696	4		T502	5
values[41]	286	1			T880	5		T696	6		T502	2
values[42]	264	1			T880	10		T696	9		T502	6
values[43]	232	1			T880	9		T696	7		T502	4
values[44]	195	1			T880	1		T696	5		T502	2
values[45]	234	1			T696	5		T502	2		T881	2
values[46]	208	1			T696	9		T502	2		T881	2
values[47]	249	1			T696	4		T502	1		T881	1
values[48]	227	1			T696	6		T502	1		T881	4
values[49]	189	1			T502	2		T881	3		T479	10
values[50]	188	1			T502	1		T881	2		T479	4
values[51]	183	1			T502	4		T881	5		T479	2
values[52]	222	1			T502	1		T881	1		T479	24
values[53]	196	1			T502	2		T881	3		T479	12
values[54]	162	1			T502	1		T881	1		T479	7
values[55]	175	1			T502	3		T881	4		T479	6
values[56]	213	1			T502	4		T881	1		T479	12
values[57]	165	1			T502	2		T881	3		T479	6
values[58]	184	1			T502	2		T881	4		T479	11
values[59]	169	1			T502	1		T881	2		T479	6
values[60]	141	1			T502	3		T881	4		T479	6
values[61]	137	1			T502	3		T881	8		T479	9
values[62]	174	1			T502	2		T881	12		T479	7
values[63]	208	1			T502	3		T881	42		T479	11
values[64]	224	1			T502	5		T881	51		T479	7
values[65]	230	1			T502	1		T881	19		T479	12
values[66]	136	1			T502	1		T479	4		T841	1
values[67]	81	1			T502	1		T479	3		T841	1
values[68]	89	1			T502	5		T841	1		T842	1
values[69]	88	1			T502	3		T841	1		T842	1
values[70]	84	1			T502	2		T841	1		T842	1
values[71]	54	1			T502	3		T841	1		T842	1
values[72]	42	1			T502	2		T841	1		T842	1
values[73]	41	1			T502	5		T841	1		T842	1
values[74]	41	1			T502	1		T841	1		T842	1
values[75]	32	1			T502	2		T841	1		T842	1
values[76]	31	1			T502	3		T841	1		T842	1
values[77]	28	1			T502	3		T841	1		T842	1
values[78]	25	1			T502	1		T841	1		T842	1
values[79]	32	1			T502	1		T841	1		T842	1
values[80]	33	1			T502	1		T841	1		T842	1
values[81]	44	1			T502	2		T841	1		T842	1
values[82]	40	1			T502	2		T841	1		T842	1
values[83]	28	1			T502	1		T841	1		T842	1
values[84]	34	1			T502	2		T841	1		T842	1
values[85]	38	1			T502	4		T841	1		T842	1
values[86]	29	1			T502	3		T841	1		T842	1
values[87]	29	1			T502	1		T841	1		T842	1
values[88]	44	1			T502	2		T841	1		T842	1
values[89]	46	1			T502	2		T841	1		T842	1
values[90]	34	1			T502	3		T841	1		T842	1
values[91]	34	1			T502	3		T841	1		T842	1
values[92]	28	1			T502	4		T841	1		T842	1
values[93]	33	1			T502	6		T841	1		T842	1
values[94]	32	1			T502	5		T841	1		T842	1
values[95]	39	1			T502	3		T841	1		T842	1
values[96]	31	1			T502	3		T841	1		T842	1
values[97]	30	1			T502	2		T841	1		T842	1
values[98]	27	1			T502	1		T841	1		T842	1
values[99]	39	1			T502	1		T841	1		T842	1
values[100]	53	1			T502	3		T841	1		T842	2
values[101]	49	1			T502	7		T841	1		T842	2
values[102]	43	1			T502	2		T841	1		T842	1
values[103]	44	1			T502	2		T841	1		T842	1
values[104]	47	1			T502	4		T841	1		T842	1
values[105]	54	1			T502	3		T841	1		T842	2
values[106]	31	1			T502	2		T841	1		T842	1
values[107]	30	1			T502	2		T841	1		T842	4
values[108]	40	1			T502	1		T841	1		T842	1
values[109]	55	1			T502	4		T841	1		T842	4
values[110]	52	1			T502	12		T841	1		T842	2
values[111]	47	1			T502	4		T841	1		T842	3
values[112]	52	1			T502	7		T841	1		T842	2
values[113]	60	1			T502	7		T841	1		T842	2
values[114]	48	1			T502	6		T841	1		T842	3
values[115]	51	1			T502	3		T841	1		T842	2
values[116]	47	1			T502	6		T841	2		T842	1
values[117]	40	1			T502	4		T841	1		T842	2
values[118]	39	1			T502	5		T841	3		T842	1
values[119]	34	1			T502	3		T841	2		T842	1
values[120]	61	1			T502	9		T841	1		T842	3
values[121]	43	1			T502	5		T841	3		T842	1
values[122]	52	1			T502	10		T841	3		T842	2
values[123]	48	1			T502	5		T841	7		T842	3
values[124]	51	1			T502	16		T841	3		T842	2
values[125]	64	1			T502	24		T841	3		T842	2
values[126]	123	1			T502	33		T841	2		T842	2
values[127]	602	1			T502	40		T841	34		T842	22
values[128]	5101	1			T502	24		T841	352		T842	297