Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145236	1			T91	12		T92	3		T97	14
values[2]	10390	1			T98	2		T467	1		T468	2
values[3]	4259	1			T485	24		T537	1		T843	1
values[4]	2538	1			T485	9		T843	2		T582	18
values[5]	1714	1			T843	1		T582	14		T874	9
values[6]	1263	1			T843	1		T582	17		T874	2
values[7]	743	1			T843	1		T582	6		T549	36
values[8]	555	1			T843	1		T582	7		T549	5
values[9]	440	1			T843	1		T582	5		T838	3
values[10]	394	1			T843	1		T582	11		T838	2
values[11]	386	1			T843	1		T582	10		T838	4
values[12]	331	1			T843	1		T582	9		T838	3
values[13]	349	1			T843	1		T582	12		T838	7
values[14]	305	1			T843	1		T582	4		T838	1
values[15]	353	1			T843	1		T582	5		T838	6
values[16]	365	1			T843	1		T582	25		T838	2
values[17]	355	1			T843	1		T582	4		T838	3
values[18]	292	1			T843	1		T582	6		T838	2
values[19]	343	1			T843	1		T582	3		T838	3
values[20]	318	1			T843	1		T582	4		T838	4
values[21]	319	1			T843	1		T582	4		T838	4
values[22]	291	1			T843	1		T582	4		T838	3
values[23]	316	1			T843	1		T582	3		T838	1
values[24]	340	1			T843	1		T582	6		T646	6
values[25]	343	1			T843	1		T582	24		T646	2
values[26]	308	1			T843	1		T582	4		T646	17
values[27]	287	1			T843	1		T582	20		T646	16
values[28]	288	1			T843	1		T582	3		T646	5
values[29]	287	1			T843	1		T582	4		T646	3
values[30]	318	1			T843	1		T582	5		T646	3
values[31]	320	1			T843	1		T582	7		T646	7
values[32]	289	1			T843	1		T582	4		T646	7
values[33]	250	1			T843	1		T582	9		T646	9
values[34]	299	1			T843	1		T582	8		T646	6
values[35]	323	1			T843	1		T582	9		T646	7
values[36]	320	1			T843	1		T582	13		T646	10
values[37]	298	1			T843	1		T582	7		T646	9
values[38]	293	1			T843	1		T582	8		T646	5
values[39]	308	1			T843	1		T582	5		T646	7
values[40]	292	1			T843	1		T582	7		T646	7
values[41]	278	1			T843	1		T582	4		T646	6
values[42]	317	1			T843	1		T582	3		T646	8
values[43]	287	1			T843	1		T582	4		T646	6
values[44]	329	1			T843	1		T582	4		T646	3
values[45]	254	1			T843	1		T582	8		T646	8
values[46]	210	1			T843	1		T582	8		T646	3
values[47]	278	1			T843	1		T582	9		T646	14
values[48]	293	1			T843	1		T582	7		T646	8
values[49]	275	1			T843	1		T582	21		T646	3
values[50]	283	1			T843	1		T582	10		T646	11
values[51]	261	1			T843	1		T582	8		T646	9
values[52]	272	1			T843	1		T582	5		T646	13
values[53]	266	1			T843	1		T582	14		T646	4
values[54]	242	1			T843	1		T582	1		T646	5
values[55]	226	1			T843	1		T646	4		T845	1
values[56]	230	1			T843	1		T646	13		T845	1
values[57]	237	1			T843	1		T646	9		T845	1
values[58]	256	1			T843	1		T646	3		T845	1
values[59]	215	1			T843	1		T646	4		T845	1
values[60]	266	1			T843	1		T646	8		T845	1
values[61]	179	1			T843	1		T646	7		T845	1
values[62]	164	1			T843	1		T646	4		T845	1
values[63]	145	1			T843	2		T646	5		T845	1
values[64]	154	1			T843	1		T646	4		T845	1
values[65]	172	1			T843	1		T646	6		T845	1
values[66]	132	1			T843	1		T646	5		T845	1
values[67]	156	1			T843	1		T646	6		T845	1
values[68]	157	1			T843	1		T646	7		T845	1
values[69]	144	1			T843	1		T646	8		T845	1
values[70]	149	1			T843	1		T646	5		T845	1
values[71]	122	1			T843	1		T646	8		T845	1
values[72]	85	1			T843	1		T646	3		T845	1
values[73]	98	1			T843	1		T646	1		T845	1
values[74]	120	1			T843	1		T845	1		T890	1
values[75]	95	1			T843	1		T845	1		T890	1
values[76]	102	1			T843	1		T845	1		T890	8
values[77]	112	1			T843	1		T845	1		T890	5
values[78]	79	1			T843	1		T845	1		T890	4
values[79]	83	1			T843	2		T845	1		T890	4
values[80]	96	1			T843	6		T845	1		T890	10
values[81]	93	1			T843	2		T845	1		T890	6
values[82]	89	1			T843	2		T845	1		T890	4
values[83]	94	1			T843	6		T845	1		T890	6
values[84]	83	1			T843	9		T845	1		T890	1
values[85]	89	1			T843	3		T845	1		T890	1
values[86]	89	1			T843	3		T845	1		T890	2
values[87]	78	1			T843	3		T845	1		T890	1
values[88]	80	1			T843	4		T845	1		T890	4
values[89]	85	1			T843	8		T845	1		T890	4
values[90]	103	1			T843	3		T845	1		T890	5
values[91]	102	1			T843	7		T845	1		T890	3
values[92]	90	1			T843	1		T845	1		T890	2
values[93]	94	1			T843	3		T845	1		T890	2
values[94]	106	1			T843	2		T845	1		T890	3
values[95]	83	1			T843	2		T845	1		T890	2
values[96]	83	1			T843	1		T845	1		T890	4
values[97]	86	1			T843	3		T845	1		T890	11
values[98]	77	1			T843	4		T845	1		T890	7
values[99]	66	1			T843	1		T845	1		T890	1
values[100]	82	1			T843	4		T845	1		T890	4
values[101]	76	1			T843	2		T845	1		T890	5
values[102]	94	1			T843	1		T845	1		T890	6
values[103]	92	1			T843	1		T845	1		T890	7
values[104]	87	1			T843	1		T845	1		T890	4
values[105]	69	1			T843	2		T845	1		T890	3
values[106]	69	1			T843	2		T845	1		T890	3
values[107]	61	1			T843	1		T845	2		T890	4
values[108]	65	1			T843	2		T845	1		T890	6
values[109]	92	1			T843	3		T845	2		T890	1
values[110]	88	1			T843	3		T845	8		T890	3
values[111]	76	1			T843	2		T845	1		T890	10
values[112]	67	1			T843	1		T845	4		T890	5
values[113]	70	1			T843	2		T845	1		T890	3
values[114]	66	1			T843	3		T845	1		T890	5
values[115]	60	1			T843	1		T845	1		T890	1
values[116]	60	1			T843	3		T845	2		T890	4
values[117]	71	1			T843	3		T845	2		T890	9
values[118]	59	1			T843	2		T845	1		T890	2
values[119]	67	1			T843	2		T845	2		T890	3
values[120]	89	1			T843	6		T845	2		T890	3
values[121]	65	1			T843	4		T845	1		T890	9
values[122]	57	1			T843	1		T845	2		T890	7
values[123]	51	1			T843	1		T845	3		T890	6
values[124]	50	1			T843	2		T845	1		T890	2
values[125]	66	1			T843	2		T845	2		T890	3
values[126]	100	1			T843	3		T845	4		T890	7
values[127]	789	1			T843	32		T845	27		T890	14
values[128]	7468	1			T843	242		T845	330		T890	5