Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
117689 | 
1 | 
 | 
 | 
T91 | 
6 | 
 | 
T92 | 
1 | 
 | 
T97 | 
11 | 
| auto[1] | 
67034 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T92 | 
1 | 
 | 
T97 | 
15 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
47510 | 
1 | 
 | 
 | 
T91 | 
3 | 
 | 
T97 | 
5 | 
 | 
T98 | 
13 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
129462 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
55261 | 
1 | 
 | 
 | 
T91 | 
2 | 
 | 
T92 | 
1 | 
 | 
T97 | 
10 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
14861 | 
1 | 
 | 
 | 
T97 | 
2 | 
 | 
T98 | 
3 | 
 | 
T272 | 
1 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
128849 | 
1 | 
 | 
 | 
T91 | 
4 | 
 | 
T92 | 
7 | 
 | 
T93 | 
246 | 
| auto[1] | 
66785 | 
1 | 
 | 
 | 
T92 | 
1 | 
 | 
T93 | 
81 | 
 | 
T98 | 
7 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
51025 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T92 | 
4 | 
 | 
T93 | 
123 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
136919 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
58715 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T92 | 
2 | 
 | 
T93 | 
93 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15973 | 
1 | 
 | 
 | 
T92 | 
1 | 
 | 
T93 | 
35 | 
 | 
T97 | 
2 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
123373 | 
1 | 
 | 
 | 
T91 | 
4 | 
 | 
T92 | 
10 | 
 | 
T97 | 
11 | 
| auto[1] | 
64768 | 
1 | 
 | 
 | 
T97 | 
11 | 
 | 
T98 | 
13 | 
 | 
T162 | 
4 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
48809 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T92 | 
2 | 
 | 
T97 | 
7 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
131892 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
56249 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T92 | 
2 | 
 | 
T97 | 
9 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15175 | 
1 | 
 | 
 | 
T97 | 
4 | 
 | 
T98 | 
4 | 
 | 
T162 | 
1 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
118939 | 
1 | 
 | 
 | 
T91 | 
2 | 
 | 
T92 | 
4 | 
 | 
T97 | 
8 | 
| auto[1] | 
63720 | 
1 | 
 | 
 | 
T92 | 
1 | 
 | 
T97 | 
8 | 
 | 
T98 | 
8 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
47099 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T92 | 
1 | 
 | 
T97 | 
6 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
128182 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
54477 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T92 | 
1 | 
 | 
T97 | 
8 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
14736 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T97 | 
4 | 
 | 
T98 | 
6 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
121160 | 
1 | 
 | 
 | 
T91 | 
6 | 
 | 
T92 | 
2 | 
 | 
T97 | 
26 | 
| auto[1] | 
59934 | 
1 | 
 | 
 | 
T92 | 
1 | 
 | 
T97 | 
5 | 
 | 
T98 | 
27 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
46482 | 
1 | 
 | 
 | 
T91 | 
2 | 
 | 
T92 | 
2 | 
 | 
T97 | 
13 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
125731 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
55363 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T97 | 
10 | 
 | 
T98 | 
14 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
14867 | 
1 | 
 | 
 | 
T91 | 
1 | 
 | 
T97 | 
5 | 
 | 
T98 | 
4 |