Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	508	1			T510	4		T680	2		T717	2
all_values[1]	498	1			T510	4		T680	3		T717	1
all_values[2]	503	1			T510	2		T680	3		T835	1
all_values[3]	479	1			T510	1		T680	6		T657	2
all_values[4]	512	1			T538	2		T510	1		T680	2
all_values[5]	478	1			T510	1		T680	5		T717	1
all_values[6]	464	1			T510	2		T680	3		T717	1
all_values[7]	477	1			T510	2		T680	4		T717	3
all_values[8]	517	1			T538	1		T510	4		T680	4
all_values[9]	507	1			T510	7		T680	3		T657	3
all_values[10]	504	1			T510	1		T866	1		T680	1
all_values[11]	478	1			T510	4		T657	2		T481	1
all_values[12]	499	1			T510	1		T680	2		T717	1
all_values[13]	485	1			T510	8		T680	3		T717	3
all_values[14]	468	1			T510	3		T680	3		T717	1
all_values[15]	498	1			T510	3		T680	1		T717	1
all_values[16]	500	1			T510	3		T680	8		T717	1
all_values[17]	501	1			T538	1		T510	1		T680	5
all_values[18]	521	1			T510	2		T680	2		T682	3
all_values[19]	491	1			T510	6		T680	4		T717	1
all_values[20]	507	1			T510	1		T680	2		T717	3
all_values[21]	481	1			T538	1		T510	4		T866	1
all_values[22]	508	1			T510	2		T680	5		T717	1
all_values[23]	492	1			T510	5		T680	3		T717	2
all_values[24]	505	1			T93	1		T538	1		T510	2
all_values[25]	448	1			T538	1		T510	3		T866	1
all_values[26]	468	1			T538	1		T510	4		T680	2
all_values[27]	495	1			T510	4		T657	2		T682	1
all_values[28]	464	1			T510	2		T680	5		T717	2
all_values[29]	486	1			T510	4		T680	5		T717	1
all_values[30]	516	1			T510	3		T680	5		T657	1
all_values[31]	480	1			T510	1		T680	3		T717	1
all_values[32]	477	1			T510	5		T680	5		T717	1
all_values[33]	479	1			T538	1		T510	2		T680	2
all_values[34]	484	1			T510	3		T717	1		T657	5
all_values[35]	494	1			T510	5		T680	1		T717	2
all_values[36]	500	1			T510	4		T680	4		T657	2
all_values[37]	491	1			T510	4		T717	1		T657	4
all_values[38]	496	1			T468	1		T538	1		T510	5
all_values[39]	504	1			T510	2		T680	4		T717	2
all_values[40]	500	1			T510	5		T680	3		T717	2
all_values[41]	490	1			T510	1		T680	2		T717	2
all_values[42]	434	1			T510	1		T680	4		T657	2
all_values[43]	493	1			T680	2		T717	4		T657	4
all_values[44]	479	1			T510	1		T680	3		T717	1
all_values[45]	495	1			T510	1		T680	3		T717	1
all_values[46]	459	1			T538	2		T510	4		T680	2
all_values[47]	512	1			T510	1		T680	2		T717	1
all_values[48]	500	1			T510	2		T834	1		T680	2
all_values[49]	493	1			T510	3		T680	4		T717	1