Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3682	1			T468	1		T452	2		T510	26
all_values[1]	3725	1			T468	6		T452	1		T510	26
all_values[2]	3674	1			T162	1		T510	13		T562	3
all_values[3]	3688	1			T452	2		T510	25		T562	2
all_values[4]	3756	1			T468	2		T510	21		T562	2
all_values[5]	3763	1			T162	1		T468	4		T510	19
all_values[6]	3752	1			T468	4		T452	2		T510	18
all_values[7]	3657	1			T468	1		T452	1		T510	21
all_values[8]	3692	1			T468	4		T452	4		T510	20
all_values[9]	3683	1			T468	1		T452	4		T510	35
all_values[10]	3822	1			T468	1		T452	3		T510	24
all_values[11]	3616	1			T452	1		T510	19		T562	2
all_values[12]	3668	1			T162	1		T468	2		T510	19
all_values[13]	3627	1			T162	1		T468	3		T452	2
all_values[14]	3786	1			T162	1		T468	1		T510	28
all_values[15]	3797	1			T468	1		T452	1		T510	15
all_values[16]	3565	1			T468	4		T452	5		T510	21
all_values[17]	3700	1			T468	4		T452	3		T510	25
all_values[18]	3697	1			T468	2		T452	5		T510	26
all_values[19]	3740	1			T468	1		T452	3		T510	18
all_values[20]	3780	1			T468	1		T452	2		T510	20
all_values[21]	3691	1			T468	3		T452	2		T510	19
all_values[22]	3789	1			T468	2		T510	24		T558	1
all_values[23]	3810	1			T468	2		T452	1		T510	37
all_values[24]	3663	1			T468	2		T452	4		T510	25
all_values[25]	3696	1			T468	1		T452	6		T510	9
all_values[26]	3811	1			T162	2		T468	3		T452	2
all_values[27]	3733	1			T468	3		T452	5		T510	23
all_values[28]	3742	1			T468	2		T510	18		T562	3
all_values[29]	3753	1			T468	1		T452	5		T510	26
all_values[30]	3721	1			T468	3		T452	2		T510	18
all_values[31]	3685	1			T468	2		T452	1		T510	18
all_values[32]	3750	1			T468	4		T452	1		T510	24
all_values[33]	3786	1			T452	4		T510	27		T562	3
all_values[34]	3742	1			T468	2		T452	2		T510	18
all_values[35]	3752	1			T468	2		T452	4		T510	23
all_values[36]	3800	1			T468	1		T452	6		T510	18
all_values[37]	3766	1			T452	4		T510	19		T562	2
all_values[38]	3685	1			T468	2		T452	1		T510	27
all_values[39]	3878	1			T468	2		T452	3		T510	16
all_values[40]	3707	1			T468	3		T452	2		T510	28
all_values[41]	3717	1			T468	1		T452	2		T510	17
all_values[42]	3767	1			T468	3		T452	3		T510	21
all_values[43]	3817	1			T468	4		T510	21		T562	2
all_values[44]	3680	1			T452	2		T510	15		T562	1
all_values[45]	3781	1			T468	3		T452	1		T510	32
all_values[46]	3696	1			T468	2		T452	1		T510	20
all_values[47]	3699	1			T468	2		T510	31		T562	3
all_values[48]	3641	1			T468	3		T452	1		T510	22
all_values[49]	3779	1			T510	21		T558	1		T562	5
all_values[50]	3731	1			T468	1		T452	2		T510	21
all_values[51]	3631	1			T468	1		T452	2		T510	15
all_values[52]	3607	1			T468	1		T452	4		T510	22
all_values[53]	3682	1			T468	2		T510	22		T562	2
all_values[54]	3720	1			T468	1		T452	2		T510	20
all_values[55]	3726	1			T468	2		T452	1		T510	18
all_values[56]	3689	1			T468	1		T452	4		T510	18
all_values[57]	3696	1			T162	1		T468	2		T452	3
all_values[58]	3649	1			T468	1		T452	1		T510	22
all_values[59]	3659	1			T468	4		T452	4		T510	25
all_values[60]	3639	1			T468	5		T452	3		T510	29
all_values[61]	3685	1			T468	1		T452	1		T510	16
all_values[62]	3638	1			T162	1		T468	2		T452	4
all_values[63]	3771	1			T162	1		T468	1		T452	5