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 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91,T97,T98
1	1	Covered	T46,T47,T82

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T269,T270,T271
1	0	Not Covered

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T269,T270,T271
0	1	0	Covered	T274,T469,T468
1	0	0	Covered	T269,T270,T271

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[128:159]}) ? 1'b0 : 1'b1)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T274,T469,T468
0	1	0	Covered	T92,T97,T467
1	0	0	Covered	T91,T97,T98

 LINE       447
 EXPRESSION (ibus_addr_en_0_we & ibus_regwen_0_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T407,T406
1	1	Covered	T212,T262,T70

 LINE       479
 EXPRESSION (ibus_addr_en_1_we & ibus_regwen_1_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T70,T169,T407
1	1	Covered	T212,T262,T263

 LINE       511
 EXPRESSION (ibus_addr_matching_0_we & ibus_regwen_0_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T407,T427
1	1	Covered	T212,T262,T70

 LINE       543
 EXPRESSION (ibus_addr_matching_1_we & ibus_regwen_1_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T70,T169,T407
1	1	Covered	T212,T262,T263

 LINE       575
 EXPRESSION (ibus_remap_addr_0_we & ibus_regwen_0_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T407,T176
1	1	Covered	T212,T262,T70

 LINE       607
 EXPRESSION (ibus_remap_addr_1_we & ibus_regwen_1_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T407,T176
1	1	Covered	T212,T262,T70

 LINE       697
 EXPRESSION (dbus_addr_en_0_we & dbus_regwen_0_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T70,T169,T406
1	1	Covered	T212,T262,T263

 LINE       729
 EXPRESSION (dbus_addr_en_1_we & dbus_regwen_1_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T174,T427
1	1	Covered	T212,T262,T70

 LINE       761
 EXPRESSION (dbus_addr_matching_0_we & dbus_regwen_0_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T70,T169,T176
1	1	Covered	T212,T262,T263

 LINE       793
 EXPRESSION (dbus_addr_matching_1_we & dbus_regwen_1_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T174,T427,T170
1	1	Covered	T212,T262,T70

 LINE       825
 EXPRESSION (dbus_remap_addr_0_we & dbus_regwen_0_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T406,T170
1	1	Covered	T212,T262,T70

 LINE       857
 EXPRESSION (dbus_remap_addr_1_we & dbus_regwen_1_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T427,T170,T418
1	1	Covered	T212,T262,T70

 LINE       1175
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ALERT_TEST_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1176
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_RECOV_ERR_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T91,T469

 LINE       1177
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_FATAL_ERR_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T264,T265,T266

 LINE       1178
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1179
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1180
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1181
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1182
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1183
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1184
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1185
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1186
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1187
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1188
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1189
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1190
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1191
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1192
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1193
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T212,T262,T70

 LINE       1194
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_ENABLE_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T47,T82

 LINE       1195
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_STATE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T47,T82

 LINE       1196
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ERR_STATUS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T301,T694

 LINE       1197
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_DATA_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T5,T6

 LINE       1198
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_STATUS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T5,T6

 LINE       1199
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_FPGA_INFO_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1202
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1202
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T46,T47,T82
1	0	Covered	T2,T3,T4

 LINE       1206
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T47,T82
1	1	Covered	T92,T97,T467

 LINE       1206
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
25 (addr_hit[24] & ((\|(4'...	Covered	T92,T469,T468
24 (addr_hit[23] & ((\|(4'...	Covered	T98,T468,T415
23 (addr_hit[22] & ((\|(4'...	Covered	T467,T468,T415
22 (addr_hit[21] & ((\|(4'...	Covered	T98,T274,T467
21 (addr_hit[20] & ((\|(4'...	Covered	T468,T415,T560
20 (addr_hit[19] & ((\|(4'...	Covered	T97,T469,T566
19 (addr_hit[18] & ((\|(4'...	Covered	T97,T274,T468
18 (addr_hit[17] & ((\|(4'...	Covered	T98,T273,T566
17 (addr_hit[16] & ((\|(4'...	Covered	T273,T468,T560
16 (addr_hit[15] & ((\|(4'...	Covered	T92,T274,T469
15 (addr_hit[14] & ((\|(4'...	Covered	T98,T468,T470
14 (addr_hit[13] & ((\|(4'...	Covered	T92,T469,T468
13 (addr_hit[12] & ((\|(4'...	Covered	T98,T274,T467
12 (addr_hit[11] & ((\|(4'...	Covered	T98,T468,T415
11 (addr_hit[10] & ((\|(4'...	Covered	T97,T467,T272
10 (addr_hit[9] & ((\|(4'b...	Covered	T97,T467,T468
9 (addr_hit[8] & ((\|(4'b...	Covered	T468,T572,T415
8 (addr_hit[7] & ((\|(4'b...	Covered	T98,T274,T467
7 (addr_hit[6] & ((\|(4'b...	Covered	T92,T98,T468
6 (addr_hit[5] & ((\|(4'b...	Covered	T274,T468,T470
5 (addr_hit[4] & ((\|(4'b...	Covered	T97,T415,T560
4 (addr_hit[3] & ((\|(4'b...	Covered	T98,T468,T415
3 (addr_hit[2] & ((\|(4'b...	Covered	T97,T467,T415
2 (addr_hit[1] & ((\|(4'b...	Covered	T469,T468,T415
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T2,T3

 LINE       1206
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T91,T92,T97
1	0	Covered	T75,T224,T192
1	1	Covered	T1,T2,T3

 LINE       1206
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T70,T91,T468
1	1	Covered	T469,T468,T415

 LINE       1206
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T264,T265,T266
1	1	Covered	T97,T467,T415

 LINE       1206
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T98,T468,T415

 LINE       1206
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T97,T415,T560

 LINE       1206
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T274,T468,T470

 LINE       1206
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T92,T98,T468

 LINE       1206
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T98,T274,T467

 LINE       1206
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T468,T572,T415

 LINE       1206
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T97,T467,T468

 LINE       1206
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T97,T467,T272

 LINE       1206
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T98,T468,T415

 LINE       1206
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T98,T274,T467

 LINE       1206
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T92,T469,T468

 LINE       1206
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T98,T468,T470

 LINE       1206
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T92,T274,T469

 LINE       1206
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T273,T468,T560

 LINE       1206
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T98,T273,T566

 LINE       1206
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T262,T70
1	1	Covered	T97,T274,T468

 LINE       1206
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T47,T82
1	1	Covered	T97,T469,T566

 LINE       1206
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T47,T82
1	1	Covered	T468,T415,T560

 LINE       1206
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T301,T694
1	1	Covered	T98,T274,T467

 LINE       1206
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T5,T6
1	1	Covered	T467,T468,T415

 LINE       1206
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T5,T6
1	1	Covered	T98,T468,T415

 LINE       1206
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T92,T469,T468

 LINE       1235
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T598,T579,T622
1	1	1	Covered	T75,T224,T192

 LINE       1244
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T415,T452,T510
1	1	0	Covered	T481,T581,T582
1	1	1	Covered	T70,T91,T558

 LINE       1247
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T97,T467,T415
1	1	0	Covered	T562,T569,T695
1	1	1	Covered	T264,T265,T266

 LINE       1250
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T212,T262,T70
1	1	0	Covered	T415,T568,T581
1	1	1	Covered	T70,T452,T563

 LINE       1253
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T212,T262,T70
1	1	0	Covered	T500,T488,T632
1	1	1	Covered	T70,T452,T563

 LINE       1256
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T470,T415
1	1	0	Covered	T452,T579,T481
1	1	1	Covered	T212,T262,T70

 LINE       1259
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T98,T415
1	1	0	Covered	T92,T485,T696
1	1	1	Covered	T212,T262,T70

 LINE       1262
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T98,T467
1	1	0	Covered	T273,T452,T485
1	1	1	Covered	T212,T262,T70

 LINE       1265
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T572,T415
1	1	0	Covered	T563,T589,T596
1	1	1	Covered	T212,T262,T70

 LINE       1268
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T97,T467
1	1	0	Covered	T562,T567,T589
1	1	1	Covered	T212,T262,T70

 LINE       1271
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T467,T272
1	1	0	Covered	T97,T560,T510
1	1	1	Covered	T212,T262,T70

 LINE       1274
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T212,T262,T70
1	1	0	Covered	T563,T582,T496
1	1	1	Covered	T70,T91,T560

 LINE       1277
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T212,T262,T70
1	1	0	Covered	T415,T563,T579
1	1	1	Covered	T70,T452,T562

 LINE       1280
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T92,T415
1	1	0	Covered	T558,T586,T583
1	1	1	Covered	T212,T262,T70

 LINE       1283
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T98,T470
1	1	0	Covered	T598,T582,T555
1	1	1	Covered	T212,T262,T70

 LINE       1286
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T92,T572
1	1	0	Covered	T634,T569,T485
1	1	1	Covered	T212,T262,T70

 LINE       1289
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T273,T560
1	1	0	Covered	T560,T452,T629
1	1	1	Covered	T212,T262,T70

 LINE       1292
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T98,T566
1	1	0	Covered	T273,T452,T568
1	1	1	Covered	T212,T262,T70

 LINE       1295
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T70,T97,T470
1	1	0	Covered	T560,T558,T589
1	1	1	Covered	T212,T262,T70

 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T75,T402,T224
1	0	1	Covered	T46,T47,T82
1	1	0	Covered	T97,T470,T415
1	1	1	Covered	T46,T47,T82